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Advanced Information Preliminary DatasheetOV7640 Color CMOS VGA (640 x 480) C AMERA C HIP TM OV7141 B&W CMOS VGA (640 x 480) C AMERA C HIP TMO mniTMisionGeneral DescriptionThe OV7640 (color) and OV7141 (black and white)TM Applications•Cellular and Picture PhonesOV7640/OV7141CMOS VGA (640 x 480) C AMERA C HIP™OFunctional DescriptionFigure2 shows the functional block diagram of the OV7640/OV7141 image sensor. The OV7640/OV7141 includes:•Image Sensor Array (640x480 resolution)•Timing Generator•Analog Processing Block•A/D Converters•Output Formatter•Digital Video PortFunctional DescriptionOImage Sensor ArrayThe OV7640/OV7141 C AMERA C HIPS has an active image array size of 640 columns x 480 rows (307,200 pixels).However, the full array contains 652 columns and 488rows, with the extra 6 rows used for black-level calibration (“Optical Black”) and color interpolation information.However, the maximum output valid image window size is 652 columns by 482 rows. Figure 3 shows a cross-section–Anti-blooming –Zero smearingA/D ConvertersAfter the Analog Processing Block, the color channel data signal is fed to two 8-bit Analog-to-Digital (A/D) converters via the multiplexers, one for the Y/G channel and one shared by the CbCr/BR channels. These A/D converters operate at speeds up to 12MHz, and are fully synchronous to the pixel rate (actual conversion rate is related to the frame rate).[6] increase I OL / I OH OmniVisionOV7640/OV7141CMOS VGA (640 x 480) C AMERA C HIP ™ORESET TimingThe RESET pin (pin 15) is active high. There is an internal pull-down (weak) resistor in the sensor so the default status of the RESET pin is low.Figure 4 RESET Timing DiagramPWDN TimingThe PWDN pin (pin 5) is active high. There is an internal pull-down (weak) resistor in the sensor so the default status of the PWDN pin is low.Figure 5 PWDN Timing DiagramPin DescriptionOPin DescriptionTable 1Pin DescriptionPin NumberName Pin Type Function/Description01VSS_A Ground Analog ground 02VDD_A V DD Analog VDD 03NC —No connection 04NC —No connection05PWDN Input (0)aa.Input (0) represents an internal pull-down resistor.Sets device to power down standby mode 06NC —No connection07VREF V REF Internal voltage reference (2.3V). Connect to ground through 1µF capacitor 08VDD_C V DD Core VDD09VSYNC Output Vertical sync output 10HREF Output HREF output 11PCLK Output Pixel clock output 12VDD_IO V DD I/O VDD 13CLK Input External clock 14NC —No connection15RESET Input (0)Clears all registers and resets them to their default values.16NC —No connection 17VSS_D Ground Digital ground18Y7Output Digital video output bit[7]19Y6Output Digital video output bit[6]20Y5Output Digital video output bit[5]21Y4Output Digital video output bit[4]22Y3Output Digital video output bit[3]23Y2Output Digital video output bit[2]24Y1Output Digital video output bit[1]25Y0Output Digital video output bit[0]26SIO_C Input SCCB serial interface clock 27SIO_D I/O SCCB serial interface data I/O 28NC—No connectionOV7640/OV7141CMOS VGA (640 x 480) C AMERA C HIP ™OElectrical CharacteristicsNOTE:Exceeding the Absolute Maximum ratings shown above invalidates all AC and DC electrical specifications and may result in permanent device damage.Table 2Absolute Maximum RatingsAmbient Storage Temperature-40ºC to +125ºCSupply Voltages (with respect to Ground)V DD-A5V V DD-C 5V V DD-IO5VAll Input/Output Voltages (with respect to Ground)-0.3V to VDD_IO+1V Lead Temperature, Surface-mount process +230ºC ESD Rating, Human Body model 2000VTable 3DC Characteristics (0°C < T A < 70°C)Symbol ParameterConditionMin Typ Max Unit V DD-A DC supply voltage – Analog — 2.40 2.5 2.60V V DD-C DC supply voltage – Core — 2.25 2.5 2.75V V DD-IO DC supply voltage – I/O — 2.25— 3.3V I DDA Active (Operating) Current See Note a a. V DD-A = V DD-C = 2.5V, V DD-IO = 3.0VI DDA = ∑{I DD-IO + I DD-C + I DD-A }, f CLK = 24MHz at 30 fps, no I/O loading15mA I DDS-SCCB Standby Current See Note b b. V DD-A = V DD-C = 2.5V, V DD-IO = 3.0VI DDS:SCCB refers to a SCCB-initiated Standby, while I DDS:PWDN refers to a PWDN pin-initiated Standby 1mA I DDS-PWDN Standby Current 10µA V IH Input voltage HIGH CMOS0.7 x V DD-IOV V IL Input voltage LOW 0.3 x V DD-IOV V OH Output voltage HIGH CMOS (I OH / I OL )0.9 x V DD-IOV V OL Output voltage LOW 0.1 x V DD-IOV I OH Output current HIGH See Note cc.Standard Output Loading = 25pF, 1.2K Ω to 3V8mA I OL Output current LOW 15mA I LInput/Output LeakageGND to V DD-IO ± 1µAElectrical CharacteristicsOTable 4Functional and AC Characteristics (0°C < T A < 70°C)SymbolParameterMinTyp MaxUnit Functional CharacteristicsA/D Differential Non-Linearity + 1/2LSB A/D Integral Non-Linearity +1LSB AGCRange21dB Red/Blue Adjustment Range12dBInputs (PWDN, CLK, RESET)f CLK Input Clock Frequency 102427MHz t CLK Input Clock Period 1004237ns t CLK:DC Clock Duty Cycle455055%t S:RESET Setting time after software/hardware reset1ms t S:REG Settling time for register change (10 frames required)300msSCCB (SIO_C and SIO_D - see Figure 6)f SIO_C Clock Frequency 400KHz t LOW Clock Low Period 1.3µs t HIGH Clock High Period600ns t AA SIO_C low to Data Out valid 100900ns t BUF Bus free time before new START 1.3µs t HD:STA START condition Hold time 600ns t SU:STA START condition Setup time 600ns t HD:DAT Data-in Hold time 0µs t SU:DAT Data-in Setup time 100ns t SU:STO STOP condition Setup time 600ns t R, t F SCCB Rise/Fall times 300ns t DH Data-out Hold time50nsOutputs (VSYNC, HREF, PCLK, and Y[7:0] - see Figure 7, Figure 8, and Figure 9)t PDV PCLK[↓] to Data-out Valid 5ns t SU Y[7:0] Setup time 15ns t HD Y[7:0] Hold time 8ns t PHH PCLK[↓] to HREF[↑]05ns t PHLPCLK[↓] to HREF[↓]5nsACConditions:• V DD : V DD-A = V DD-C = 2.5V, V DD-IO = 3.3V • Rise/Fall Times: I/O: 5ns, MaximumSCCB: 300ns, Maximum• Input Capacitance: 10pf• Output Loading: 25pF, 1.2K Ω to 3V • f CLK : 24MHzOV7640/OV7141CMOS VGA (640 x 480) C AMERA C HIP™OTiming Specifications Figure 6 SCCB Timing DiagramTiming SpecificationsOFigure 8 VGA Frame Timing DiagramNote:OV7640/OV7141CMOS VGA (640 x 480) C AMERA C HIP™OFigure 10 RGB:565 Output Timing DiagramTiming SpecificationsOOV7640 Light ResponseFigure 12 OV7640 Light ResponseOV7640/OV7141CMOS VGA (640 x 480) C AMERA C HIP™ORegister Set Table5 provides a list and description of the Device Control registers contained in the OV7640/OV7141. For all register Enable/Disable bits, ENABLE=1 and DISABLE=0. The device slave addresses for the OV7640/OV7141 are 42 for write and43 for read.Table 5 SCCB Register ListAddress (Hex)RegisterNameDefault(Hex)R/W Description00GAIN00RW AGC – Gain control gain settingBit[7:6]:ReservedBit[5:0]:Gain control gain setting •Range: [00] to [3F]01BLUE80RW AWB – Blue channel gain setting•Range: [00] to [FF]Note: This function is not available on the B&W OV7141.02RED80RW AWB – Red channel gain setting•Range: [00] to [FF]Note: This function is not available on the B&W OV7141.03SAT84RW Image Format – Color saturation valueBit[7:4]:Saturation value•Range: [0] to [F]Bit[3:0]:ReservedNote: This function is not available on the B&W OV7141.04HUE34RW Image Format – Color hue controlBit[7:6]:ReservedBit[5]:Hue EnableBit[4:0]:Hue settingNote: This function is not available on the B&W OV7141.05CWF3E RW AWB – Red/Blue Pre-Amplifier gain settingBit[7:4]:Red channel pre-amplifier gain setting•Range: [0] to [F]Bit[3:0]:Blue channel pre-amplifier gain setting•Range: [0] to [F]Note: This function is not available on the B&W OV7141.06BRT80RW ABC – Brightness setting •Range: [00] to [FF]07-09RSVD XX–Reserved0A PID76R Product ID number (Read only)0B VER48R Product version number (Read only) 0C-0F RSVD XX–Reserved10AECH41RW Exposure ValueRegister SetOTable 5SCCB Register ListOV7640/OV7141CMOS VGA (640 x 480) C AMERA C HIP™OTable 5 SCCB Register ListRegister SetO1F FACT 01RWOutput Format – Format ControlBit[7:5]:Reserved Bit[4]:RGB:565/555 Enable Control0:Disabled 1:EnabledNote: Bit[4] is not programmable on the B&W OV7141.Bit[3]:ReservedBit[2]:RGB:565/555 Mode Select 0:RGB:565 output format 1:RGB:555 output formatNote: Bit[2] is not programmable on the B&W OV7141.Bit[1:0]:Reserved20COME C0RWCommon Control EBit[7]:Reserved Bit[6]:AEC – Digital Averaging Enable Bit[5]:Reserved Bit[4]:Image Quality – Edge Enhancement Enable Bit[3:1]:Reserved Bit[0]:Y[7:0] 2X I OL / I OH Enable 21-23RSVD XX –Reserved24AEW 10RW AGC/AEC – Stable Operating Region – Upper Limit 25AEB8ARWAGC/AEC – Stable Operating Region – Lower Limit26COMF A2RWCommon Control FBit[7:3]:Reserved Bit[2]:Data Format – Output Data MSB/LSB Swap Enable(LSB → MSB (Y[7]) and MSB → LSB (Y[0])Bit[1:0]:Reserved27COMG E2RWCommon Control GBit[7:5]:Reserved Bit[4]:Color Matrix – RGB Crosstalk Compensation Disable(Used to increase each color filter’s efficiency)Note: Bit[4] is not programmable on the B&W OV7141.Bit[3:2]:ReservedBit[1]:Data Format – Output Full Range Enable 0:Output Range = [10] to [F0] (224 bits)1:Output Range = [01] to [FE] (254/256 bits) Bit[0]:ReservedTable 5SCCB Register ListAddress (Hex)Register NameDefault (Hex)R/WDescriptionOV7640/OV7141CMOS VGA (640 x 480) C AMERA C HIP ™O28COMH 20RWCommon Control HBit[7]:Output Format – RGB Output Select0:RGB1:Raw RGBNote: Bit[7] is NOT programmable when COMA [3] = 0.Bit[6]:Device Select 0:OV76401:OV7141Bit[5]:Output Format – Scan Select 0:Interlaced 1:Progressive Bit[4:0]:Reserved29COMI00RCommon Control IBit[7:2]:ReservedBit[1:0]:Device Version (Read-only)2A FRARH 00RWOutput Format – Frame Rate Adjust HighBit[7]:Data Format – Frame Rate Adjust EnableBit[6:5]:Data Format – Frame Rate Adjust Setting MSBFRA[9:0] = MSB + LSB = FRARH[6:5] + FRARL[7:0]Bit[4]:A/D – UV Channel ‘2 Pixel Delay’ Enable Note: Bit[4] is not programmable on the B&W OV7141.Bit[3:0]:Reserved2B FRARL 00RW Data Format – Frame Rate Adjust Setting LSBFRA[9:0] = MSB + LSB = FRARH[6:5] + FRARL[7:0]2CRSVDXX–Reserved2D COMJ 81RWCommon Control JBit[7:3]:Reserved Bit[2]:AEC – Band Filter Enable Bit[1:0]:Reserved 2E-5F RSVD XX –Reserved60SPCB 06RW Signal Process Control BBit[7]:AGC – 1.5x Multiplier (Pre-amplifier) Enable Bit[6:0]:Reserved 61-6B RSVD XX –Reserved6CRMCO11RWColor Matrix – RGB Crosstalk Compensation – R ChannelNote: This function is not available on the B&W OV7141.6DGMCO01RWColor Matrix – RGB Crosstalk Compensation – G ChannelNote: This function is not available on the B&W OV7141.6E BMCO 06RWColor Matrix – RGB Crosstalk Compensation– B ChannelNote: This function is not available on the B&W OV7141.6FRSVDXX–ReservedTable 5SCCB Register ListAddress (Hex)Register NameDefault (Hex)R/WDescriptionRegister SetO70COMK 01RWCommon Mode Control KBit[7]:Reserved Bit[6]:Y[7:0] 2X I OL / I OH Enable Bit[5:0]:Reserved71COML 00RWCommon Mode Control LBit[7]:Reserved Bit[6]:Data Format – PCLK output gated by HREF Enable Bit[5]:Data Format – Output HSYNC on HREF Pin Enable Bit[4]:ReservedBit[3:2]:Data Format – HSYNC Rising Edge Delay MSB Bit[1:0]:Data Format – HSYNC Falling Edge Delay MSB 72HSDYR 10RWData Format – HSYNC Rising Edge Delay LSBHSYNCR[9:0] = MSB + LSB = COML[3:2] + HSDYR[7:0]•Range 000 to 762 pixel delays73HSDYF 50RWData Format – HSYNC Falling Edge Delay LSBHSYNCF[9:0] = MSB + LSB = COML[1:0] + HSDYF[7:0]•Range 000 to 762 pixel delays74COMM 20RWCommon Mode Control MBit[7]:ReservedBit[6:5]:AGC – Maximum Gain Select00:+6 dB 01:+12 dB 10:+6 dB 11:+18 dBBit[4:0]:Reserved 75COMN 02RWCommon Mode Control NBit[7]:Output Format – Vertical Flip Enable Bit[6:0]:Reserved 76COMO 00RWCommon Mode Control OBit[7:6]:Reserved Bit[5]:Standby Mode Enable Bit[4:0]:Reserved 77-7D RSVD XX –Reserved7EAVGY00RWAEC – Digital Y/G Channel Average(Automatically updated by AGC/AEC, user can only read the values)7F AVGR 00RWAEC – Digital R/V Channel Average(Automatically updated by AGC/AEC, user can only read the values)Note: This function is not available on the B&W OV7141.80AVGB 00RWAEC – Digital B/U Channel Average(Automatically updated by AGC/AEC, user can only read the values)Note: This function is not available on the B&W OV7141.NOTE: All other registers are factory-reserved. Please contact OmniVision Technologies for reference register settings.Table 5SCCB Register ListAddress (Hex)Register NameDefault (Hex)R/WDescriptionOV7640/OV7141CMOS VGA (640 x 480) C AMERA C HIP™OPackage Specifications The OV7640/OV7141 uses either a 28-pin ceramic package or 28-pin plastic package. Refer to Figure13 for ceramic package information, Figure14 for plastic package information, and Figure15 for the array center on the chip.Figure 13 OV7640/OV7141 Ceramic Package SpecificationsPackage SpecificationsOFigure 14 OV7640/OV7141 Plastic Package SpecificationsOV7640/OV7141CMOS VGA (640 x 480) C AMERA C HIP™OSensor Array CenterFigure 15 OV7640/OV7141 Sensor Array CenterPackage Specifications Version 1.7, October 27, 2003Proprietary to OmniVision Technologies 21OIR Reflow Ramp Rate RequirementsFigure 16 IR Reflow Ramp Rate RequirementsOV7640/OV7141CMOS VGA (640 x 480) C AMERA C HIP™ONote:•All information shown herein is current as of the revision and publication date. Please refer to the OmniVision web site () to obtain the current versions of alldocumentation.•OmniVision Technologies, Inc. reserves the right to make changes to their products or to discontinue any product or service without further notice (It is advisable to obtain current product documentation prior to placing orders).•Reproduction of information in OmniVision product documentation and specifications is permissible only if reproduction is without alteration and is accompanied by all associatedwarranties, conditions, limitations and notices. In such cases, OmniVision is not responsibleor liable for any information reproduced.•This document is provided with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any warrantyotherwise arising out of any proposal, specification or sample. Furthermore, OmniVisionTechnologies Inc. disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this document. No license, expressed or implied, byestoppels or otherwise, to any intellectual property rights is granted herein.•‘OmniVision’, ‘CameraChip’ are trademarks of OmniVision Technologies, Inc. All other trade, product or service names referenced in this release may be trademarks or registered trademarks of their respective holders. Third-party brands, names, and trademarks are the property of theirrespective owners.For further information, please feel free to contact OmniVision at info@.OmniVision Technologies, Inc.1341 Orleans DriveSunnyvale, CA USA(408) 542-300022Proprietary to OmniVision Technologies Version 1.7, October 27, 2003。