JESD22-B102E 可焊性规范

JEDECSTANDARD SolderabilityJESD22-B102E(Revision of JESD22-B102D, September 2004)OCTOBER 2007JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONNOTICEJEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and approvedby the JEDEC legal counsel.JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is tobe used either domestically or internationally.JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or processes. 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For information, contact:JEDEC Solid State Technology Association2500 Wilson BoulevardArlington, Virginia 22201-3834or call (703) 907-7559TEST METHOD B102ESOLDERABILITYContentsPage1 Scope 12 General Summary2.1 Preconditioning 12.2 Solderability Testing 23 Apparatus2 3.1 Precondition Equipment 2 3.2 Solder Pot 2 3.3 Dipping Device 3 3.4 Optical Equipment 3 3.5 Lighting Equipment 3 3.6 Surface Mount Process Simulation Test Equipment 33.7 Materials 44 Solderability Test Conditions 55 Test Procedures 7 5.1 Preconditioning 7 5.2 Method 1. Dip and Look Test 95.3 Method 2. Surface Mount Process Simulation Test 126 Summary16 Annex A 17 TablesTable 1 Precondition Conditions for Solderability Testing 1 Table 2 Maximum Limits of Solder Bath Contaminant 4 Table 3a Solderability Test Conditions for Method 1, Dip and Look Test 5 Table 3b Solderability Test Conditions for Method 2, SMD Process Simulation Test6 Table 4 Altitude versus Steam Temperature 7 FiguresFigure 1 Inspection Area for Dual Inline Packages 13 Figure 2 Inspection Area for Gull Wing Packages 14 Figure 3 Inspection Area for J-Lead Packages 14 Figure 4 Inspection Area for Tantalum Chip Capacitors 15 Figure 5 Inspection Area for Rectangular Passive Components 15-i-Page 1Test Method B102E(Revision of Test Method B102D)TEST METHOD B102E SOLDERABILITY(From JEDEC Board Ballot JCB-04-77 and JCB-07-79, formulated under the cognizance of the JC-14.1 Subcommittee on Reliability Test Methods for Packaged Devices.)1 ScopeThis test method provides optional conditions for preconditioning and soldering for the purpose of assessing the solderability of device package terminations. It provides procedures for dip & look solderability testing of through hole, axial and surface mount devices and a surface mount process simulation test for surface mount packages.The purpose of this test method is to provide a means of determining the solderability of device package terminations that are intended to be joined to another surface using lead- (Pb-) containing or Pb-free solder for the attachment.2 General summary2.1 PreconditioningAn accelerated precondition is generally used before Solderability testing to simulate package storage. The following are options for preconditioning. The user and supplier need to agree on the precondition requirements.Table 1 — Precondition conditions for solderability testing Condition PreconditiontypeExposure time Use guidelinesA 1 Hour ± 5 min.Intended for nontin and nontin-alloy leadfinishes that will be soldered after an extended storage time.B 4 Hours ± 10 minOptional legacy condition. C 8 Hours ± 15 minIntended for tin and tin-alloy leadfinishes thatwill be soldered after an extended storage time.D SteamPrecondition16 Hours ± 30 min Optional legacy condition.E 150 °C DryBake16 Hours ± 30 min Alternative to steam precondition.JEDEC Standard No. 22-B102E Page 2Test Method B102E(Revision of Test Method B102-D)2 General summary (cont’d)2.2 Solderability testingThis test standard describes methods by which package terminations may be evaluated for solderability. Typically Pb containing terminations are evaluated using SnPb solderability test conditions and Pb-free terminations use Pb-free test conditions. If Pb-free terminations are to be used in an SnPb solder process (backward compatibility) then they should be evaluated using test parameters consistent with standard SnPb SMT reflow conditions. The backward compatibility test does not apply to Pb-free BGA type packages.Method 1 - Dip and Look Test: This test is for leaded and leadless terminations.Method 2 - Surface Mount Process Simulation Test: This method may be used for SMD packages as an alternative to the dip and look test method 1.3 Apparatus3.1 Precondition equipment3.1.1 Steam precondition equipmentA noncorrodible container and cover of sufficient size to allow the placement of specimensinside the vessel shall be used. The specimens shall be placed such that the lowest portion of the specimen is a minimum of 38 mm (1.5 inches) above the surface of the water. Equipment should be designed to minimize steam condensate from dripping onto the test specimens. A suitable method of supporting the specimens shall be improvised using noncontaminating material.3.1.2 High temperature bake equipmentA bake oven of sufficient size and capable of continuously maintaining 150 °C ± 5 °C temperature control shall be used.3.2 Solder potA static solder pot of sufficient size to accommodate the test specimens containing at least 8.9 N (2 lb) of solder shall be used. The apparatus shall be capable of maintaining the solder at the specified temperature within +/- 5 o C.JEDEC Standard No. 22-B102EPage 3Test Method B102E(Revision of Test Method B102D)3 Apparatus (cont’d)3.3 Dipping deviceA mechanical dipping device capable of controlling the rates of immersion and emersion of the terminations and providing a dwell time (time of total immersion to the required depth) in the solder bath as specified shall be used.3.4 Optical equipmentAn optical microscope capable of providing magnification inspection from 10x to 20x shall be used.3.5 Lighting equipmentA lighting system shall be used that will provide a uniform, nonglare, nondirectional illumination of the specimen.3.6 Surface mount process simulation test equipment3.6.1 Stencil or screenA stencil or screen with pad geometry opening that is appropriate for the terminals being tested. Unless otherwise agreed upon between vendor and user, nominal stencil thickness should be 0.102 mm (0.004 in) for terminals with less than 0.508 mm (0.020 in) component lead pitch,0.152 mm (0.006 in) for a component with lead pitch of 0.508 mm to 0.635 mm (0.020 in to 0.025 in), and 0.203 mm (0.008 in) for a component with lead pitch greater than 0.635 mm (0.025 in).3.6.2 Rubber squeegee or metal spatula3.6.3 SubstrateA thin unmetallized ceramic substrate with a typical thickness range of 0.635 mm to 0.889 mm (0.025 to 0.035 in) shall be used for testing. Other nonwettable substrates may be used by agreement between the user and supplier.3.6.4 Reflow equipmentConvection/Infrared reflow oven, vapor phase reflow system, or storage oven capable of reaching the reflow requirements of Table 3b.JEDEC Standard No. 22-B102E Page 4Test Method B102E(Revision of Test Method B102-D)3.7 Materials3.7.1 FluxThe flux for all Solderability tests shall be a standard activated rosin flux (type ROL1 perJ-STD-004, Requirements for Soldering Fluxes) having a composition of 25% ± 0.5% by weight of colophony and 0.15% ± 0.01% by weight Diethylammonium Hydrochloride (CAS 660-68-4), in 74.85% ± 0.5% by weight of isopropyl alcohol. The specific gravity of the standard activated rosin flux shall be 0.843 ± 0.005 at 25 ± 2 °C [77 ± 3.6 °F].3.7.2 SolderThe solder shall conform to J-STD-006, Requirements for Electronic Grade Solder Alloys and Fluxed and Non-Fluxed Solid Solders for Electronic Soldering Applications.SnPb alloy composition: Sn60Pb40A or Sn63Pb37A (Sn ± 1%)Pb-free solder alloy composition: Sn95.5Ag3.9Cu0.6, allowing variation of the Ag content between 3.0 – 4.0 wt% and Cu content between 0.5 – 1.0 wt % with the balance being Sn. Other Pb-free alloy compositions may be used by agreement between the user and supplier.3.7.2.1 Solder bath contaminants controlThe solder in solder baths used for solderability testing shall be chemically or spectrographically analyzed or replaced each 30 operating days. The levels of contamination must be maintained within those listed in Table 2.Table 2 — Maximum limits of solder bath contaminantContaminant Weight Percentage LimitMaximum ContaminantSnPb Solder SnAgCu SolderCopper 0.300NA Gold 0.2000.200 Cadmium 0.0050.005 Zinc 0.0050.005 Aluminum 0.0060.006 Antimony 0.5000.500 Iron 0.0200.020 Arsenic 0.0300.030 Bismuth 0.2500.250 Silver 0.100NA Nickel 0.0100.010 Lead (Pb) NA 0.1NOTE 1 The tin content of the solder shall be maintained within +/-1% of the nominal alloy being used.Tin content shall be tested at the same frequency as testing for contaminants.NOTE 2 The total of copper, gold, cadmium, zinc, and aluminum contaminants shall not exceed 0.4% for SnPb solder pot.JEDEC Standard No. 22-B102EPage 5Test Method B102E(Revision of Test Method B102D)3.7 Materials (cont’d)3.7.3 Surface mount process simulation test materials3.7.3.1 Solder pasteThe solder paste shall use a rosin flux system (type ROL1 or ROL0 per J-STD-004,Requirements for Soldering Fluxes), solder conforming to 3.7.2 and shall have a mesh size of -325/+500 (per J-STD-005, Requirements for Soldering Pastes). Table 3b defines which flux type to use.NOTE Paste storage and shelf life shall be in accordance with manufacturer’s specifications.3.7.3.2 Flux removal solventMaterial used for cleaning flux from leads and terminations shall be capable of removing visible flux residues and meet local environmental regulations. 4 Solderability test conditionsTable 3a — Solderability test conditions for Method 1, Dip and Look TestTest typeSnPb solderability testPb-free solderability testSolder Process Wave Soldering Reflow Soldering Pb-free ReflowSolderingbackwardcompatibilityAll ProcessesFlux TypeROL1 ROL1 ROL1 ROL1Flux Immersion Time5 - 10 s5 - 10 s5 - 10 s5 - 10 sSolder Type SnPb SnPb SnPb Pb-free SolderTemperature245 °C ± 5 °C 215 °C ± 5 °C 215 °C 1 245 °C ± 5 °C Solder Immersion Time5 ± 0.5 s5 ± 0.5 s5 ± 0.5 s5 ± 0.5 sSolder Immersion / Emersion Rate 1.00 ± 0.25 in/s (25.4 ± 6.4 mm/s)1.00 ± 0.25 in/s (25.4 ± 6.4 mm/s)1.00 ± 0.25 in/s (25.4 ± 6.4 mm/s)1.00 ± 0.25 in/s (25.4 ± 6.4 mm/s)NOTE 1 Tolerance for reflow temperature is defined as component supplier maximum and user minimum.JEDEC Standard No. 22-B102E Page 6Test Method B102E(Revision of Test Method B102-D)4 Solderability test conditions (cont’d)Table 3b — Solderability test conditions for Method 2, SMD Process Simulation TestTest type SnPbsolderability test Pb-free backward compatibilityPb-free solderability testPackage Type SMD SMD SMD Flux Type ROL1 ROL1 ROL0 Solder Type SnPb SnPbSnAgCuReflow Process (Recommended)Convection/IROven Convection/IR OvenConvection/IR OvenPreheat Temperature 150 – 170 °C 150 – 170 °C 160 – 180 °C Preheat Time 50 – 70 s50 – 70 s50 – 70 s Reflow Temperature 215 – 230 °C 215 °C 1 230 – 245 °C Reflow Time 50 – 70 s 50 – 70 s50 – 70 sReflow Process (alternate)Vapor Phase Vapor Phase (Not typically used) Reflow Temperature 215 – 219 °C 230 – 245 °C Reflow Time 30 – 60 sNot recommended forPb-free backward compatibility testing30 – 60 sReflow Process (alternate)Storage Oven Reflow Temperature 215 – 230 °C Reflow Time 2-5 min (until reflow is assured)Not recommended for Pb-free backward compatibility testingNot recommended for Pb-free testingNOTE 1 Tolerance for reflow temperature is defined as component supplier maximum and user minimum.5 Test proceduresThe test procedures shall be performed on the number of terminations specified in the applicable procurement document. During handling, care shall be exercised to prevent the surface to be tested from being abraded or contaminated by grease, perspirants, etc.All solderability testing shall be done under a fume hood in accordance with applicable safety rules and procedures.No wiping, cleaning, scraping or abrasive cleaning of the terminations shall be performed. Any special preparation of the terminations, such as bending or reorientation prior to test, shall be specified in the applicable procurement document.Solderability tests shall be considered destructive unless otherwise specified in the applicable procurement document.5.1 Preconditioning5.1.1 Preconditioning by steam soakPrior to the application of the flux and subsequent solder dipping, all specimens shall be subjected to aging by exposure of the surfaces to be tested to steam in the container specified in 3.1. The specimens shall be suspended so that no portion of the specimen is less than 38 mm (1.5 inches) above the boiling distilled or deionized water for the specified exposure time. If an exposure time is not specified, condition C of Table 1 shall be used. The water vapor temperature at the component lead level shall be in accordance with Table 4.Table 4 — Altitude versus Steam Temperature.Altitude (feet) Steam Temperature (o C +3, -5)0 - 2,000 93 2,001 - 4,000 91 4,001 - 6,000 89 Greater than 6,000 87(cont’d)5.1 Preconditioning5.1.1 Preconditioning by steam soak (cont’d)5.1.1.1 Specimen handlingThe test components shall be placed (“Dead Bug”) into the steam preconditioning equipment such that no specimens have their leads/terminations touching other specimens or the steam preconditioning equipment. All test specimens must be handled using finger cots or gloves.5.1.1.2 DryingThe test specimens shall be removed from the steam preconditioning equipment immediately after the steam exposure has been completed. Solderability testing shall be completed within 72 hours of removal from the steam preconditioning equipment. The parts shall be dried using one of the following procedures:a) Bake at 100 o C maximum for no more than 1 hour in a dry atmosphere (dry nitrogenatmosphere is recommended).b) Air dry at ambient temperature for a minimum of 15 minutes.5.1.1.3 Cleaning of the systemThe apparatus shall be drained and cleaned on a regular basis to insure consistent steam precondition results. DI or distilled water shall be used. No contaminating solvents shall be used.5.1.2 Preconditioning by high temperature bake (alternate method)Prior to the application of the flux and subsequent solder dipping, all specimens shall be subjected to a 150 °C high temperature bake.5.1.2.1 Specimen handlingThe test components shall be placed (“Dead Bug”) into the high temperature bake equipment on high temperature trays such that no specimens have their leads/terminations touching other specimens or the bake tray. All test specimens must be handled using finger cots or gloves. Solderability testing shall be completed within 72 hours of removal from the high temperature bake equipment.5 Test procedures (cont’d)5.2 Method 1 - dip and look testThe test procedure shall consist of the following operations:a) Preparation of the terminations, if applicable.b) Preconditioning, if applicable.c) Application of flux and immersion of the terminations into molten solder.d) Examination and evaluation of the tested portions of the terminations.5.2.1 Preparation of terminationsIf the insulation on stranded wires must be removed, it shall be done in a manner so as not to loosen the strands in the wire.5.2.2 Preconditioning (if applicable)Precondition the test parts per 5.1.5.2.3 Application of fluxType ROL1 flux shall be used, unless otherwise specified (see 3.7.1). Terminations shall be immersed (using a mechanical dipper) in the flux, which is at room ambient temperature, to the minimum depth necessary to cover the surface to be tested. The fixturing should be designed to avoid trapping of excess flux. The surface to be tested shall be immersed in the flux per the time specified in Table 3, and shall be drained 5 to 20 seconds prior to dipping into the solder pot. The flux shall be covered when not in use and discarded a minimum of once a day.5.2.3.1 Surface mounted devicesFor surface mount packages, that portion of the package lead that will be inspected shall be covered by the flux application. Perform the test using the leads on only one side of the package at a time. The fluxing and solder dipping operations shall be performed sequentially on the leads of the package side under test.5.2.3.2 All other devicesUnless otherwise specified in the applicable procurement document, terminations shall be immersed to the seating plane or to within 1.27 mm (0.05 inch) of the body of the device under test.5.2 Method 1 - dip and look test (cont’d)5.2.3 Application of flux (cont’d)5.2.3.3 Component termination attitude relative to flux and solder surfacesLeaded (THM) Through Hole Mount 90 degLeaded (SM) Surface Mount 20 to 45 deg or 90 degLeadless (SM) Surface Mount 20 to 45 deg5.2.4 Solder dipThe dross and burned flux shall be skimmed from the surface of the molten solder specified in 3.7.2. The molten solder shall be maintained at the specified temperature in Table 3. The surface of the molten solder shall be skimmed again just prior to immersing the terminations into the solder. The part shall be attached to a dipping device (see 3.3) and the flux-covered terminations immersed once in the molten solder to the same depth specified in 5.2.3. The dip conditions are specified in Table 3. After the dipping process, the part shall be allowed to cool in the air. Residual flux shall be removed from the terminations either by sequential rinses in isopropyl alcohol, or by a rinse in a suitable commercial non-CFC solvent. If necessary, a soft damp cloth or cotton swab moistened with clean isopropyl alcohol or solvent may be used to remove all remaining flux.5.2.5 Inspection and failure criteriaAll flux is to be removed prior to visual inspection of the terminal surface.•Inspect all devices at 10x to 20x magnification.•The inspected area of each lead must have 95% solder coverage minimum.•Pinholes, voids, porosity, nonwetting, or dewetting shall not exceed 5 percent of the total inspected area.•There shall be no solder bridging between any termination area and any other metallization not connected to it by design. In the event that the solder dipping causes bridging, the testshall not be considered a failure provided that a local application of heat (e.g., gas,soldering iron, or redipping) results in solder pullback and no wetting of the dielectric area as indicated by microscopic examination.NOTE The total area of the surface to be tested (including all faces for rectangular leads) as specified in Figures 1 through 5 shall be examined. In the case of a dispute, the percentage of coverage with pinholesor voids shall be determined by the actual measurement of those areas, compared to the total area(s).5.2 Method 1 - dip and look test (cont’d)5.2.5 Inspection and failure criteria (cont’d)5.2.5.4 Definition of the inspected area (Critical Area)a) Dual Inline Packages - For Dual Inline Packages the inspected area is from the terminationtip to a plane 0.51 mm (0.020 inch) above the seating plane (see Figure 1). Areas normally designed to be unplated (trim areas) are excluded.b) Gull Wing Packages - For Gull Wing packages the inspected area is defined as all surfaces ofthe termination at or below the plane of the top of the foot, excluding the top of the foot (see Figure 2). Areas normally designed to be unplated (trim areas) are excluded.c) J-lead Packages: For J-lead packages the inspected area is the narrow portion of thetermination below the transition from the termination shoulder (see Figure 3). Only the three visible surfaces are to be included. The termination tip is excluded.d) Tantalum Chip Capacitors: For these packages the inspected area is defined as the bottom ofthe termination and one times the lead thickness up the side of the termination (see Figure 4).Termination edges are excluded.e) Rectangular Passive Components (Resistor/Capacitor/Inductor): The inspected area isdefined as the underside of the termination and side of the termination up to the solder paste minimum thickness (see Figure 5). Termination edges are excluded.f) Other Packages: For packages other than described in (a through e) the inspected area is thatwhich is 1.27 mm (0.05 inch) from the body and extends away from the body to the end of the lead or for a distance of 25.4 mm (1 inch).5.3 Method 2 - surface mount process simulation testThis procedure may be used for surface mounted devices as an alternative to the Method 1 Dip and Look procedure of section 5.2. Fine pitch gull wing leads (spacing < 0.51 mm (20 mils)) sometimes cannot be tested adequately with the dip & look method. The Dip and Look test is also inappropriate for BGA’s.NOTE This procedure comes from EIA-638, “Surface Mount Solderability Test”The test procedure shall consist of the following operations:a) Preconditioning, if applicable.b) Print solder paste.c) Place component on solder paste.d)Reflow, cool and remove flux.e)Examination and evaluation of the tested terminations.5.3.1 Preconditioning (if applicable)Precondition the test parts per 5.1.5.3.2 Specimen preparation and surface conditionAll component leads or terminations shall be tested under the condition that they would normally be in at the time of assembly soldering. The specimens to be tested shall not be touched by fingers or otherwise contaminated, nor shall the leads or terminations being tested be wiped, cleaned, scraped or abraded. The steps are listed.1) Place solder paste onto screen and print the terminal pattern onto the substrate by wiping thepaste over the screen using either a spatula for fine pitch or a squeegee for standard pitch.Nominal stencil thickness is described in section 3.6.1.2) Remove the screen carefully so as to avoid smearing the paste print. Verify a paste printequivalent in geometry to the terminal of the device to be tested.3) Using tweezers, place the terminals of the unit on the solder paste print. Avoid touching theunit so that the terminals will not be contaminated with skin oils. Verify part placement by appropriate magnification.4) Place the substrate on the applicable reflow equipment and subject the substrate andcomponents to the reflow process condition per Table 3b.5) After reflow, carefully remove substrate with components and allow to cool.6) After specimen has cooled to room temperature, remove component from substrate usingtweezers. Terminals may adhere slightly to substrate due to flux residue.7) Remove any flux residue by using appropriate cleaning solution.5.3 Method 2 - surface mount process simulation test (cont’d)5.3.3 Visual inspection5.3.3.1 Visual magnification criteriaEach termination shall be examined using a magnification of 10x to 20x.5.3.3.2 Accept/reject criteriaAll terminations shall exhibit a continuous solder coating free from defects for a minimum of 95% of the critical surface area of any individual termination. Anomalies other than dewetting, nonwetting, and pinholes are not cause for rejection. Exposed terminal base metal is allowable on the end toe of surface mount components.Examples of the critical areas for various devices are shown in Figure 2, Gull Wing Packages; Figure 3, J-Lead Packages; Figure 4, Tantalum Chip Capacitors; and Figure 5, Rectangular Passive Components.SeatingPlaneCritical AreaFigure 1 — Inspection area for dual inline packages5.3 Method 2 - surface mount process simulation test (cont’d) 5.3.3.2 Accept/reject criteria (cont’d)2X2XT2X2XTFigure 3 — Inspection area for J-Lead packages5.3 Method 2 - surface mount process simulation test (cont’d)5.3.3.2 Accept/reject criteria (cont’d)Figure 4 — Inspection area for tantalum chip capacitorsFigure 5 — Inspection area for rectangular passive components6 SummaryThe following details shall be specified in the applicable procurement document:a) The number of terminations of each part to be tested and the quality level.b) Special preparation of terminations, if applicable.c) Preconditioning type and exposure time used.d) Depth of immersion if other than specified in 5.2.3.e) Solderability test conditions if other than specified in Tables 3a and 3b.f) Electrical measurements (parameters, conditions, subgroups, etc.) where required after test.JEDEC Standard No. 22-B102EPage 17 Annex A (informative) Differences between JESD22-B102E and JESD22-B102-DThis table briefly describes most of the changes made to entries that appear in this standard, JESD22-B102E, compared to its predecessor, JESD22-B102-D (August 2004). If the change to a concept involves any words added or deleted (excluding deletion of accidentally repeated words), it is included. Some punctuation changes are not included.Page Description of changeAdded Pb-free backward compatibility test and test conditions, section 2.2 and Tables 3aand 3b.Test Method B102E。