Allegro转PADS

allegro转pads的方法（原创实用版3篇）目录（篇1）1.引言：介绍 Allegro 和 PADS2.Allegro 转 PADS 的流程3.Allegro 转 PADS 的技巧与注意事项4.结论：总结 Allegro 转 PADS 的方法及其在电子设计自动化中的应用正文（篇1）一、引言随着电子技术的快速发展，电子设计自动化（EDA）工具在现代电子设计中扮演着越来越重要的角色。

在众多 EDA 软件中，Allegro 和 PADS 是两种常用于印刷电路板（PCB）设计的工具。

熟练掌握 Allegro 转 PADS 的方法，对于提高电子设计效率具有重要意义。

二、Allegro 转 PADS 的流程1.备份 Allegro 设计文件：在转出之前，务必对 Allegro 设计文件进行备份，以防止转出过程中出现意外丢失数据。

2.导出 Allegro 设计文件：在 Allegro 中选择“File”>“Export”>“PCB Layout”，选择输出格式为 Gerber RS-274X，并设置好输出路径。

3.导入 PADS 设计文件：启动 PADS 软件，选择“File”>“Open”，找到刚才导出的 Gerber 文件并打开。

4.PADS 设计文件的检查与修复：检查 PADS 中的设计是否与Allegro 中的设计一致，如有不一致的地方，需进行修复。

5.保存 PADS 设计文件：在 PADS 中选择“File”>“Save”，将设计文件保存为 PADS 格式。

三、Allegro 转 PADS 的技巧与注意事项1.技巧一：在 Allegro 中设置好设计规则，避免在 PADS 中出现设计错误。

2.技巧二：在导出 Gerber 文件时，选择适当的输出分辨率，以提高PADS 中设计的精度。

3.注意事项一：在导入 PADS 设计文件时，确保 PADS 软件的版本与Gerber 文件的版本兼容。

Allgro to PADS（Windows 7版）一、首先在PADS安装目录下找到文件拷贝到SPB_DATA下
C:\MentorGraphics\9.5PADS\SDD_HOME\translators\skill_
scripts下15个文件拷贝到C:\SPB_Data\pcbenv
二、将放在其它盘中的Allgro的原图，后缀为.brd，注意文件名
不能有空格存在，文件拷贝到SPB_DATA下
E:\ZDC PRODUCT_2012-2014\ZDC_Hisilicon\海思项目的原理&PCB\Hi3716C-A_0525\HI3716_A_v1.0-PCB\HI3716 v1.0-PCB 下文件Hi3716.brd拷贝到C:\SPB_Data\convert(新建的)的文件夹下
三、建立环境变量
打开控制面板-系统和安全-系统-高级系统设置-系统变量-用户变量
系统变量设置：
skill load
C:\SPB_Data\pcbenv\dfl_main.il 用户变量一：
AEX_BIN_ROOT
C:\MentorGraphics\9.5PADS\SDD_HOME\translators\win32\bin 用户变量二：
AEX_ENABLE_JOBPREFS_LAYER_FIX
1
四、用Allgro打开文件
开启Cadence下文件：
打开制板文件下目录：
单击确定
勾选TOP和All
skill load “dfl_main.il” main out
选择Start one way Translation
五、打开PADS程序，导入.brd文件
六、 PADS内参数调整另存目录。

PCB系列之All egro文件转P ADS格式XLBaymax整理
使用软件：Altium Designer10 Allegro16.6 PADS9.5
先看下allegro文件的预览图
步骤如下：打开Altium Designer10 ，File—Import wizard
选择Allegro文件类型，然后next
选择需要转换的allegro文件（brd格式），多个的话可以一起选，一起转换，选好之后点next
PCB层的映射，如果你觉得分配的不对，可以手工更改层，一般没问题，next
轮到PADS上场了，直接导入
文件类型选择PcbDoc，选择文件之后点打开就OK
大功告成，来看下最后的样子，转换之后有些地方属性可能有些不对，需要自行更改。

补充：
如果你在打开Altium Designer10 ，执行File—Import wizard之后是下图这样子的，不要急，你只是没装导入插件。

DXP—Plug-ins and updates,然后点Importers and Exporters 36plugs
可以挑选自己需要的插件进行安装，但是我这里选择install all，然后点apply即可，然后可以愉快的转文件了。

Allegro文件转换成PADS文件(2009-07-02 22:27:10)方法一一、用Altium Designer8.3转换Allegro文件二、用pads9自带的转换器，把PROTEL文件转换成pads，区别网原创整理，/Altium Designer8.3转ALLEGRO的方法如果嫌pads和Altium Designer8.3安装麻烦，请使用绿色版本pads9绿色精简版下载/Upload/PCB/PADS9.rarpads2007sp4绿色精简版下载/Upload/PCB/PADS2007sp4.rarAltium Designer8.0绿色精简版下载/Upload/PCB/AltiumDesigner8.0.rar包括allegro转AD模块，建议在转换前，把铺铜，无关紧要的文字，等都删除……方法二一、Allegro导出成gerber二、CAM350导入gerber，并设置层，按Y设置层；至少要Top和Bottom三、CAM350导出成pads格式的asc文件四、pads导入asc文件。

区别网原创整理，/转载请注明出处。

方法三allegro to PADS转换，我的方法是：allegro => WG =>PADS转是可以的，但不是同一家公司，不可能十全十美的转换，可能有些东西会丢掉。

转换的可用度在95％以上。

例如丝印、铜皮有时很难转过来。

最好在用网表进行验证网络是否正确。

此方法估计好多人都是在用，如用第3方软件CAMCAD转换，丢的东西更多，我转的时候就丢了很多。

allegro to WG 是通过SKILL来进行的，先输出mgc文件然后转成PCB文件。

PADS to allegro转换无需其他工具他们自己可以户转非常好转，但封装可能会有部分参数丢失，例如热盘和反盘等。

WG to allegro转换，我的方法是：WG =>PADS=>allegro。

备注：所有的软件互转的PCB只能用来参考，不能当做最终文件输出。

laikelang 2009‐8‐21目录1PADS 文件导入Allegro 的步骤 ...................................................................................................................... 1 1.1 在PADS 软件中输出ASCII 文件 ....................................................................................................... 1 1.2 在Allegro 中输入ASCII 文件 ............................................................................................................. 2 2 Allegro 文件导入PADS 的方法 . (4)2.1 通过CAMCAD PCB Translator 软件进行转换 (4)2.2 通过Specctra 程序进行转换 (5)2.3 编写SKILL 程序进行转换 .................................................................................................................. 6 3 Allegro 文件导入PADS 的步骤 . (7)3.1 在PADS 软件中输出原始设计文件的ASCII 文件 (7)3.2 在Allegro 软件中更新ASCII 文件 (8)3.3 在PADS 软件中导入更新后的ASCII 文件 (9)1 PADS 文件导入Allegro 的步骤Allegro 程序有自带一个PADS IN 的接口，可以直接读取PADS 输出的PowerPCB V5.0版本ASCII 文件。

1.1准备工作：将PADS安装目录下的skill_scripts里面的文件全部复制到pcbenv(Allegro安装时生成文件夹)里面。

1. 电脑安装好Cadence 和PADS软件，本人安装的是Cadence 16.6和最新的PADS VX2. 添加用户变量变量名：AEX_BIN_ROOT值： PADS软件中translators软件的bin目录路径比如我的AEX_BIN_ROOT = C:\MentorGraphics\PADSVX.0\SDD_HOM E\translators\win32\bin2.33.添加用户变量变量名：AEX_ENABLE_JOBPREFS_LAYER_FIX值： 1比如我的AEX_ENABLE_JOBPREFS_LAYER_FIX =14.44.添加用户变量，变量名：Home值：Cadence软件的pcbenv文件夹所在目录的路径如我的Home=C:\SPB_Data5.5打开allegro PCB editor，打开PCB editor时选择XL版本，在Allegro 软件的Setup下的user preferences Editor 中的Skill选项里，在telskill选项中打√ ,这时软件会弹出一个对话框，不用理会，关闭就是6.6将PADS软件skill_scripts目录里面的文件全部复制到Cadence软件的pebenv目录里面如我的将C:\MentorGraphics\PADSVX.0\SDD_HOME\translators\skill_scripts 里面的文件全部复制到C:\SPB_Data\pcbenv里面到这里转换的准备工作已经做完了7.7打开要转换的Allegro PCB文件8.8command命令栏中输入skill load "dfl_main.il",回车后，会看到返回T。

注意，输入时，引号不能少，load和引号间是有空格的9.9执行完后，在Command中输入：main out ，回车，这时会弹出一个对话框：点击“Star One Way Translation” ，等待运行结束，运行过程中不能有报错，如果有报错请查找原因并修正，运行成功后commend命令栏提示成功，DONE到这一步完成后，刚刚打开的这份PCB就已经被软件处理过了，做完了PADS导入前的处理工作，可以不用关掉allegro软件10.10打开 PADS layout软件，文件-导入，导入文件选择类型选择allgro PCB文件，然后找到刚刚打开的allgro 文件，导入，等待完成即可，layout中就打开了该PCB文件。

Allegro转PADS步骤梁勇军2013‐8‐12Allegro转PADS步骤1、Allegro版本必须是16.3;PADS版本必须是9.4.1;操作系统为Window 7SP1专业版;2、将PADS安装文件夹下的\MentorGraphics\9.4PADS\SDD_HOME\translators\skill_scri pts里的东西全部COPY 到Cadence下面的\SPB_Data\pcbenv里面;3、设置以下两个系统变量:AEX_BIN_ROOT=%SDD_HOME%\translators\win32\binAEX_ENABLE_JOBPREFS_LAYER_FIX=14、在任意盘中新建一个文件夹，将待转的Allegro .brd文件放入其中，用AllegroPCB Design XL以上版本打开，将所有层全部打开显示出来，然后在命令栏输入：Command> skill load “dfl_main.il”Command> main out5、此时会弹出Allegro to Expedition Translator 对话框，点击Start One WayTranslation 按钮进行转换；如果命令栏弹出任何错误提示，则必须将错误全部解决才能顺利转换，警告可以忽略不理；6、点击开始—程序‐‐Mentor Graphics SDD‐‐PADS9.4—Translators‐‐Allegro to PADSTranslator,在弹出的Allegro Designs Translator对话框中，Place translated 栏选择将要转成PADS格式的新文件放置文件夹，点击Add，选中那个待转的.brd文件，再点击translate，转换成功则会在刚才那个新文件放置文件夹中出现design_##########.pcb.。

Allegro to PADS® TranslatorUser’s GuidePADS 9.4© 1987-2012 Mentor Graphics CorporationAll rights reserved.This document contains information that is proprietary to Mentor Graphics Corporation. The original recipient of this document may duplicate this document in whole or in part for internal business purposes only, provided that this entire notice appears in all copies. In duplicating any part of this document, the recipient agrees to make every reasonableThis document is for information and instruction purposes. Mentor Graphics reserves the right to make changes in specifications and other information contained in this publication without prior notice, and the reader should, in all cases, consult Mentor Graphics to determine whether any changes have been made.The terms and conditions governing the sale and licensing of Mentor Graphics products are set forth in written agreements between Mentor Graphics and its customers. No representation or other affirmation of fact contained in this publication shall be deemed to be a warranty or give rise to any liability of Mentor Graphics whatsoever.MENTOR GRAPHICS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.MENTOR GRAPHICS SHALL NOT BE LIABLE FOR ANY INCIDENTAL, INDIRECT, SPECIAL, OR CONSEQUENTIAL DAMAGES WHATSOEVER (INCLUDING BUT NOT LIMITED TO LOST PROFITS) ARISING OUT OF OR RELATED TO THIS PUBLICATION OR THE INFORMATION CONTAINED IN IT, EVEN IF MENTOR GRAPHICS CORPORATION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.RESTRICTED RIGHTS LEGEND 03/97U.S. Government Restricted Rights. The SOFTWARE and documentation have been developed entirely at private expense and are commercial computer software provided with restricted rights. Use, duplication or disclosure by the U.S. Government or a U.S. Government subcontractor is subject to the restrictions set forth in the license agreement provided with the software pursuant to DFARS 227.7202-3(a) or as set forth in subparagraph (c)(1) and (2) of the Commercial Computer Software - Restricted Rights clause at FAR 52.227-19, as applicable.Contractor/manufacturer is:Mentor Graphics Corporation8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777.Telephone: 503.685.7000Toll-Free Telephone: 800.592.2210Website: SupportNet: /Send Feedback on Documentation: /doc_feedback_form TRADEMARKS: The trademarks, logos and service marks ("Marks") used herein are the property of Mentor Graphics Corporation or other third parties. No one is permitted to use these Marks without the prior written consent of Mentor Graphics or the respective third-party owner. The use herein of a third-party Mark is not an attempt to indicate Mentor Graphics as a source of a product, but is intended to indicate a product from, or associated with, a particular third party. A current list of Mentor Graphics’ trademarks may be viewed at: /trademarks.Table of ContentsChapter 1Migrating Cadence Allegro Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Method 1—PADS and Allegro on the Same Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Method 2—PADS and Allegro on Different Machines. . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Allegro Designs Translator Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Chapter 2Allegro to PADS Layout Translation Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Zero Size Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Decals and Design Graphics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Board Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 SMD Edge Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Lack of Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Create_devices Failure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..12 Exclamation mark (!) in the Design Board Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Disabling Board Refresh while Exporting Data with SKILL Scripts . . . . . . . . . . . . . . . . . .12 Allegro to PADS Mapping Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Chapter 3Error Codes and Log Messages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Third-Party InformationEnd-User License AgreementTable of ContentsChapter 1Migrating Cadence Allegro DesignsThe Cadence Allegro to PADS Layout design translator is one of a group of translators included with the PADS PCB Design Tools. It installs with PADS Layout.Tip: To find the version number of the translator, click the translator icon in the title bar, and select About Allegro Designs Translator.Supported VersionsThe translator supports up to version 16.3 of Allegro PCB.Restrictions•You must have access to both PADS Layout and to the Cadence Allegro PCB Editor in at least the XL version.•Only the “electrical” type data is translated.Choosing a MethodIf both applications reside on the same machine, use Method 1 to migrate the design. If they are on different machines, use Method 2.Method 1—PADS and Allegro on the Same MachinePerform the following steps to migrate an Allegro design to PADS Layout when PADS Layout and Allegro PCB Editor reside on the same machine.Procedure1.To prepare the Allegro design(s) for migration, copy the contents of the<PADS installdir>\SDD_HOME\translators\skill_scripts folder to:o Unix—the $HOME\pcbenv folder.o Windows—the %HOME% folder. For example, C:\SPB_Data\pcbenv2.Verify that the following "System" Variables are set prior to running "skill loaddfl_main.il" otherwise translator executable files do not properly generate correct output files and folders in the background.Migrating Cadence Allegro DesignsMethod 2—PADS and Allegro on Different MachinesAEX_BIN_ROOT=%SDD_HOME%\translators\win32\binAEX_ENABLE_JOBPREFS_LAYER_FIX=1Tip: Some environments remove the above Variables when you run The MGC SDDConfigurator. If this happens add them to "User" variables.3.For each design you want to translate:a.Create a new folder (for example C:\SPB_Data\convert_1), and copy into it theAllegro design (.brd) file you want to migrate.b.Open the .brd file, and in the Allegro command prompt window enter thesecommand lines:Command> skill load “dfl_main.il” (include quotes)Command> main outc.The “main out” opens the Allegro to Expedition Translator dialog box. Click theStart One Way Translation button.d.After the SKILL script has completed, any errors reported must be fixed, then rerunthe SKILL script. The migration will not complete correctly if all errors are notfixed. When completed, numuerous folders and files are generated under the newdesign folder you created in step a.4.Migrate the prepared Allegro design(s) (for example C:\SPB_Data\convert_1) to PADSLayout using one of the following steps:• A single design—In PADS Layout, use File > Import. This procedure automatically includes attributes. When migration completes, it is automatically opened in PADSLayout.•Multiple designs or to control attribute translation—Perform the following steps:i.From the Start Menu, run the Allegro to PADS Translator.ii.In the Allegro Designs Translator dialog box:a.Identify the location where you want the translated files placed.e the Add button to specify the files you want to translate.c.Specify whether or not to translate attributes.d.Click the Translate button. The output filename(s) will be in the formatdesign_##########.pcb.Method 2—PADS and Allegro on Different MachinesPerform the following steps to migrate an Allegro design to PADS Layout when PADS Layout and Allegro PCB Editor reside on different machines.Migrating Cadence Allegro DesignsMethod 2—PADS and Allegro on Different Machines Procedure1.On the PADS machine, copy..•The contents of the <PADS install dir>\SDD_HOME\translators\skill_scripts folder •The <PADS install dir>\SDD_HOME\translators\win32\bin\tech_translator.exe..to the Allegro machine in the $HOME\pcbenv folder (for exampleC:\SPB_Data\pcbenv).2.Set the AEX_BIN_ROOT environment variable to point to $HOME\pcbenv.3.Verify that the following "System" Variables are set prior to running "skill loaddfl_main.il" otherwise translator executable files do not properly generate correct output files and folders in the background.AEX_BIN_ROOT=%SDD_HOME%\translators\win32\binAEX_ENABLE_JOBPREFS_LAYER_FIX=1Tip: Some environments remove the above Variables when you run The MGC SDDConfigurator. If this happens add them to "User" variables.4.For each design you want to translate:a.Create a new folder (for example C:\SPB_Data\convert_1), and copy into it theAllegro design (.brd) file you want to migrate.b.Open the .brd file, and in the Allegro command prompt window enter thesecommand lines:Command> skill load “dfl_main.il” (include quotes)Command> main outc.The “main out” opens the Allegro to Expedition Translator dialog box. Click theStart One Way Translation button.d.After the SKILL script has completed, any errors reported must be fixed, then rerunthe SKILL script. The migration will not complete correctly if all errors are notfixed. When completed, numuerous folders and files are generated under the newdesign folder you created in step a.e.Zip-up and transfer the entire design folder (for example, C:\SPB_Data\convert_1)to the PADS machine.f.On the PADS machine, unzip to any location to migrate the prepared Allegrodesign(s) to PADS Layout.5.Migrate the prepared Allegro design(s) (for example C:\SPB_Data\convert_1) to PADSLayout using one of the following steps:• A single design—In PADS Layout, use File menu > Import. This procedure automatically includes attributes. When migration completes, it is automaticallyopened in PADS Layout.Migrating Cadence Allegro DesignsAllegro Designs Translator Dialog Box•Multiple designs or to control attribute translation—Perform the following steps:i.From the Start Menu, run the Allegro to PADS Translator.ii.In the Allegro Designs Translator dialog box:a.Identify the location where you want the translated files placed.e the Add button to specify the files you want to translate.c.Specify whether or not to translate attributes.iii.Click the Translate button. The output filename(s) will be in the formatdesign_##########.pcb.Related TopicsError Codes and Log MessagesAllegro Designs Translator Dialog BoxUse the Allegro Designs Translator dialog box to translate multiple Allegro designs and/or control attribute translation. When using the File > Import transtlation method, attributes are automatically translated.Accessing•Start menu > All Programs > Mentor Graphics SDD > PADS (version) > Translators > Allegro to PADS TranslatorMigrating Cadence Allegro DesignsAllegro Designs Translator Dialog BoxFigure 1-1. Designs TabTable 1-1. Designs Tab ContentsName DescriptionPlace translated files in Type the pathname of the folder where you want thetranslated files to be placed, or click the browse button tofind the folder.Log file Displays the location of the translation log file. When thetranslation completes, the Translation Results dialog boxdisplays the translation log.Migrating Cadence Allegro DesignsAllegro Designs Translator Dialog BoxRelated TopicsMigrating Cadence Allegro Designs Allegro files to translate Click the Add button to browse for Allegro .brd designfiles.Select and click Remove to take a design file out of thelist of designs that can be translated.Restrictions:•Filenames must be unique in the list.•Only designs whose check box is selected aretranslated.Update mapping Click to update the attribute mapping.Restriction: This button is unavailable until you add oneor more designs to translate.Translation Options area Translate attributesSelect this check box to translate Allegro attributes intoPADS attributes.Table 1-1. Designs Tab ContentsNameDescriptionChapter 2 Allegro to PADS Layout Translation NotesThis chapter describes differences between Allegro file content and PADS Layout file content, and possible discrepancies that can occur in translation.Zero Size PadsAllegro zero size pads are not supported by the translator. As a workaround, you can resize them to make them as small as possible (1 DBU), and put a message in the log file stating what these pads are.Decals and Design GraphicsDecals generated during the translation do NOT contain all the pertinent information that existed in Allegro (for example, notes, some graphics, etc). Therefore check the translated design closely.Board OutlineBoard outlines must be contiguous in Allegro to successfully translate into PADS. Check the board outline in Allegro to ensure that there are no gaps or opens.SMD Edge ConnectorsAn outstanding bug exists when sometimes the translator does not handle double-sided SMD edge connectors correctly. If the design has one of these connectors please double-check it after the translation in PADS. This problem typically occurs on designs that have an AGP / PCI type connector.Lack of MemoryDue to Windows OS limitations, the translator cannot allocate more than 2GB of memory. If you are translating a very large design, the translator may run out of memory and display an “Unable to allocate enough memory to translate current design” message.The suggested workaround is to configure Windows to provide 3GB virtual address space. To do this:Allegro to PADS Layout Translation NotesCreate_devices Failure1.Add /3GB to the Windows boot.ini file as described at/whdc/system/platform/server/PAE/PAEmem.mspx.2.Reboot your computer and start the translation again.Create_devices FailureSKILL scripts use the Allegro create_devices command to export device files to ...\devices in the design directory. If this command fails, data export cannot complete successfully. To complete the data export process, you must fix the design board to make the create_devices command work.One example of this problem is Allegro device names containing an equals sign (=). When the SKILL script encounters such a name, it removes the equals sign, which causes the Allegro create_devices command to fail. To resolve this problem, you must do one of the following: •Edit the device name in the Allegro schematic and forward annotate it to the board.•Remove the device from the Allegro design.Another example is device names longer than 32 characters. This causes a problem with exporting devices. If your job has device names that are longer than 32 characters, set the Allegro environment variable ALLEGRO_LONG_PACKAGE_NAME to TRUE.Exclamation mark (!) in the Design Board Path SKILL scripts create a temporary Allegro macro file with commands exporting part of the data. If the design board path contains an exclamation mark (!), the temporary macro file name also contains an exclamation mark; this causes the SKILL script to try to execute the temporary macro file with the replay command.Disabling Board Refresh while Exporting Data with SKILL ScriptsFor better performance, design board refresh is disabled while exporting data from Allegro with SKILL scripts.Allegro to PADS Layout Translation NotesAllegro to PADS Mapping Table Allegro to PADS Mapping TableThe following table shows the translation mapping of Allegro elements to PADS.Table 2-1. Allegro to PADS Mapping TableFrom Allegro Element: To PADS Element:LayersSupportedAssy_Line NotBoard Outline Board Outline objectBreak Outs Traces & Vias (Fanouts)Component_Body Outline_1User layer (Component Body Outline_1)Component_Body Outline_2User layer (Component Body Outline_2)DAM Not SupportedDielectric Not SupportedDimension_Keepout Not SupportedDrill Not SupportedError Not SupportedFixture_Outline Not SupportedForce Not SupportedGlue_Mask_1Not SupportedGlue_Mask_2Not SupportedHead_Insertion Not SupportedInsertion_Machine_Keepout User layer (Insertion)Milling Not SupportedOne-Way_Region User layer (One Way Region)Panel_Outline Not SupportedPaste_Mask_1Paste Mask TopPaste_Mask_2Paste Mask BottomPlace_1Layer 20 (Placement Outline)Place_2Layer 20 (Placement Outline)Placement_Keepout_1User layerPlacement_Keepout_2User layerAllegro to PADS Layout Translation NotesAllegro to PADS Mapping TableTable 2-1. Allegro to PADS Mapping Table From Allegro Element: To PADS Element:Placement_Region_1User layerPlacement_Region_2User layerPower Plane LayerPrepreg Not SupportedProbe_1 and Probe_2Not SupportedProbe_Area Not SupportedProbe_Symbol Not SupportedRouting_Keepout Keepout (Trace & Via)Shape_Edit Not SupportedSheet_Dielectric Not SupportedSignal_X Layer (Signal)Silkscreen_1Silkscreen Outline TopSilkscreen_2Silkscreen Outline BottomSolder_Paste_1Paste Mask TopSolder_Paste_2Paste Mask BottomSoldermask_1Soldermask TopSoldermask_2Soldermask BottomTest Points Test PointsTestPoint_Keepout Not SupportedTestPoint_Outline Not SupportedTestPoint_Reference Not SupportedThermal SupportedTrace Keepout Keepout (Trace)User Defined Layer User layerVia Keepout Keepout (Via)FabricationAperture Table Not SupportedArtwork Format Not SupportedArtwork Simulation Not SupportedArtwork Stackup Not SupportedAllegro to PADS Layout Translation NotesAllegro to PADS Mapping TableTable 2-1. Allegro to PADS Mapping TableFrom Allegro Element: To PADS Element:Drill Data Not SupportedDrill Simulation Not SupportedDrill Table Not SupportedMill Table Not SupportedFills, Keepouts, PlanesArea Fills Copper Pour or Plane AreaArea Fills (Protected)Copper Pour or Plane AreaArea Fill Tie Bar and Cutouts Not SupportedClassic Area Fills Copper Pour or Plane AreaCutouts Copper KeepoutCutouts (Protected)Copper KeepoutNo Connect Rules Not supportedPlacement Outline Not SupportedPower Fill Plane LayerRoute Keepout Keepout (Trace)Signal Layer Electrical LayerSplit Power Planes Plane LayerTrace Keepout Keepout (Trace)Via Keepout Keepout (Via)Visual-Text, Shapes, etc.Color map settings Not SupportedComponent Ref. Des. (Top)Ref. Des. on Silkscreen TopComponent Ref. Des. (Bottom)Ref. Des. on Silkscreen Bottom Dimensioning Not SupportedDrill Symbols SupportedGuides Not supportedNet Type Patterns Not SupportedPart Name Not SupportedPin Ref. Des.Pin NumbersShapes on User Defined Layers Shapes on User LayersAllegro to PADS Layout Translation NotesAllegro to PADS Mapping TableTable 2-1. Allegro to PADS Mapping TableFrom Allegro Element: To PADS Element:Shapes on Route Layers Shapes on Routing LayersTargets/Registration Marks Graphics on User LayersText on User Defined Layer Text on User LayerText on Route Layer Text (Keepout)Parts, Traces & ViasBlind Padstacks SMD PadstacksBlind/Buried Vias Buried ViasBlind/Buried Vias (Protected)Buried ViasBreak Outs Traces & ViasBreak Outs (Protected)Traces & ViasBreakouts (Component)TracesBuried Padstacks Only for 2 pin parts, maps to Buried PartComponent Type Rules Not SupportedComponents PartsComponents (Fixed)PartsComponents (Protected)PartsDrilled Holes Part HolesFixed Components PartsJumpers PartsMicroVias Vias (small diameter)MicroVias (Protected)Vias (small diameter)Mounting Holes Additional pins in decalNo Cleanup Vias ViasPins (Protected)PartsReuse Block (Primitive)Treated as single componentReuse Block (Replica linked)Components and tracesReuse Block (Replica un-linked)Treated as editable components & tracesReuse Block (Smashed linked)Components and tracesReuse Block (Smashed un-linked)Treated as editable components & tracesShield Trace TracesAllegro to PADS Layout Translation NotesAllegro to PADS Mapping TableTable 2-1. Allegro to PADS Mapping TableFrom Allegro Element: To PADS Element:Shield Trace (Protected)TracesTeardrops Not SupportedTest Coupon Not SupportedTest Points Test PointsThrough Padstacks Through PadstacksThrough Vias Through ViasThrough Vias (Protected)Through ViasTraces TracesTraces (Protected)TracesTraces in Cell Not supportedOtherComponent to Component Rules SupportedComponent Type Rules Not SupportedHighspeed Rules Not supportedHybird Objects Not SupportedMCM Objects Not SupportedNet Types Net ClassesPin Type, SLT Not SupportedRF Objects Not SupportedThermal Not SupportedVariants Not SupportedAllegro to PADS Layout Translation Notes Allegro to PADS Mapping TableChapter 3Error Codes and Log MessagesTable 3-1 is a list of error codes and translator log messages.Table 3-1. Error Codes and Log MessagesError code Explanation[F] A fatal error. The translator will terminate. A file was not created due to aproblem, setting, or switch that would not allow the file to be translated. Atranslated file is not created due to the fatal error that was encountered.[E] A serious, but non-fatal error. The translator will continue, but you must resolvethe problem, and the problem encountered might prevent the file from beinguseable by Expedition.[I]Current status information.[W] A warning.Error Codes and Log MessagesThird-Party InformationThis section provides information on open source and third-party software that may be included in the Allegro to PADS Translator product.•This software application may include BOOST version1.46.0third-party software.BOOST version1.46.0is distributed under the terms of the BOOST Software License version1.0and is distributed on an"AS IS"basis, WITHOUT WARRANTY OF ANY KIND,either express or implied.See the license for the specific language governingrights and limitations under the license.You can view a copy of the license at:<your_Mentor_Graphics_documentation_directory>/legal/boost_1.0.pdf.End-User License AgreementThe latest version of the End-User License Agreement is available on-line at:/eulaEND-USER LICENSE AGREEMENT (“Agreement”)This is a legal agreement concerning the use of Software (as defined in Section 2) and hardware (collectively “Products”)between the company acquiring the Products (“Customer”), and the Mentor Graphics entity that issued the corresponding quotation or, if no quotation was issued, the applicable local Mentor Graphics entity (“Mentor Graphics”). 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电子设计开发平台PADS2Allegro切换方案推荐设计平台：Cadence Allegro电子产品设计开发平台推荐产品类型：原理图设计+ 原理图功能仿真+高速PCB设计平台切换前提：见1.1详细说明电子设计平台切换方案概要1.1 设计平台切换方案软件要求软件要求：PADS Logic原理图工具DxDesigner原理图工具PADS Layout布局布线工具Cadence Design Entry CIS原理图工具Cadence Allegro PCB Designer布局布线工具1.2 原理图切换方案PADS Logic原理图可以通过EDIF格式的原理图数据，直接导入Cadence Design Entry CIS 原理图环境中，可以实现PADS Logic原理图向Design Entry CIS原理图的数据切换，其具体过程如下所述。

（1）PADS Logic环境中设计原理图（2）DxDesigner环境中导入PADS Logic原理图数据执行File/Import/PADS命令，在Symbol &Schematic Translators: PADS Logic to DxDesignerNetlist对话框中，设置转换参数即可将PADS Logic设计的原理图*.sch文件，转换为DxDesigner原理图。

其中转换窗口中的设置如下：Schematics——设置需要转换的PADS Logic原理图设计；Libraries——设置器件库；Mapping——设置PADS Logic环境中符号属性与DxDesigner环境中符号属性的对应关系。

（3）DxDesigner原理图导出EDIF原理图在DxDesigner环境中执行File/Export/EDIF Schematic命令，将DxDesigner原理图导出EDIF格式原理图数据*.eds。

（4）Design Entry CIS环境导入EDIF原理图在Cadence Design Entry CIS原理图设计环境中，执行File/Import Design命令，在弹出的Import Design窗口中，选择需要切换的原理图数据*.eds文件，如下图所示：其中Import Design转换设置如下：Open——需要转换的原理图EDIF格式数据；Save As——指定EDIF原理图切换至Design Entry CIS原理图的设置；Configuration——选择原理图切换进程的配置文件EDI2CAP.CFG。

1，ALLEGRO- WG2005/EE2007- PADS2，allegro转到pads可以通过CAM350转。

allegro转出ODB++的档案,然后用CAM350 import，再用cam350 export 出PowerPCB4.0的asc档即可。

3，CAMCAD,如果要转换Cadence Allegro文件到PADS,所有必须的设计信息都会包含在新的文件中。

不过，Cadence Allegro允许板子上的铜箔重叠，PADS却不允许。

Allegro 文件可以正常导入到CAMCAD。

4，在Altium Designer中导入Allegro的brd文件基本思想是用CAM文件，具体步骤：1、从Allegro PCB Editor中导出Gerber文件和IPC网表文件（不要IPC网表也可以，不过那样导入的PCB网络名是AD随机命名的）。

也可以导出ODB++文件（可能还是需要IPC 网表），我觉得这个比Gerber方便。

Allegro需要安装第三方软件才能输出ODB++，这个在导出时会提示下载的（软件是free的）。

2、在AD中新建一个CAM文件。

3、通过AD的File/Import导入Allegro输出的Gerber/ODB++，（可选）通过File/Import/Net List导入IPC网表。

4、使用Tool/Netlist/Extract提取导入的Gerber/ODB++的网络（将相连的Track视为同一网络，网络名随机生成）。

5、（可选）通过File Import/NetList导入IPC网表。

如果3中已导入，忽略本步。

6、通过Tool/NetList/Campare将Extrat的网表和IPC网表进行比较，从而将网络（大部分）命名为Allegro中原来的网络名。

7、通过File/Export/Export to PCB，将CAM文件导出到PCB。

至此基本完成了导入功能，但是所有的元件已经分解成了Pad，overlay上的Designator也已经不再是Text型。