Application of an ESD-MOS Compact Model for IC Design

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Application of an ESD-MOS Compact Modelfor IC Design

Markus Mergens1, Wolfgang Wilkening1, Heinrich Wolf 2, Wolfgang Fichtner31 Robert Bosch GmbH, Tübingerstr.123, D-72703 Reutlingen, Germany,

markus.mergens@de.bosch.com, voice +49 7121 35 4810, fax +49 7121 35 2687.2 Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration (IZM), Angewandter Test Integrierter

Systeme (ATIS), Hansastr.27d, D-80686 München, Germany.3 Integrated System Laboratory, Swiss Federal Institute of Technology (ETHZ), Gloriastr.35,

CH-8092 Zürich, Switzerland.

Abstract - Ein modulares Konzept zur flexiblen Modellierung von ESD-MOS Kompaktmodellen für dieNetzwerksimulation wird vorgestellt. Zwei Anwendungsbeispiele des Modells werden diskutiert: ein ESD-Schutz-Netzwerk eines CMOS-Ausgangstreibers und ein ESD-geschützter Stromspiegel. DieSimulationsergebnisse wurden anhand von Meßdaten (TLP/HBM) validiert und stimmen gut mitSchaltverhalten und Ausfallgrenzen überein. Die Relevanz des dynamischen Gate-Kopplungs-Effekts fürdas ESD-Verhalten der Netzwerke wird eindrucksvoll belegt.A modular strategy for highly flexible modeling of ESD - capable MOS compact models is introduced.Two application examples are reported: an ESD protected CMOS output driver and a current mirrorprotection circuit. Experimental data (TLP/HBM) and simulations of the two cases are in a very goodagreement with regard to switching behavior and failure thresholds. Furthermore, the relevance of dynamicgate coupling for the ESD - reliability of the circuit is clearly underlined.

I INTRODUCTION

The input/output (I/O) buffers and power suppliesconstitute the most ESD sensitive sections of an ICsince the devices are directly connected to thebondpads. In order to preserve this weak areas fromdamage, ESD protection elements are placed inparallel to divert the stress current safely to ground.Especially in ASICs, device configurations directlylinked to the pad may vary depending on the specificapplication. In view of first silicon success, lessiterations, and all in all optimized design cycles times,this aspect makes ESD level circuit simulation aninevitable tool in the future to speed up theverification of the protection level of critical pins. Aprerequisite are ESD-capable MOS models [1, 2, 3, 4]which accurately cover the high current regime underESD stress conditions.

p+n+n+

groundVgs > VthVds > 0IDS

|VDsat -IBEIholeVD|aval.region

ID

Figure 1 Schematic NMOS cross-section with currentcomponents under ESD-stress including the influence of the gatesource voltage. The arrows indicate the carrier flow.

In this contribution, we present the application of amodular ESD-MOS compact model [10] (including

the implementation of the gate coupling effect[5, 6, 7]). This model is employed for ESD-levelcircuit simulation in two application examples of aSmart Power Technology: 1. output driver protectioncircuit. 2. current mirror protection circuit. Thesimulation results quantitatively explain why transientgate coupling has a strong impact on the ESDreliability of the circuits. Moreover, ESD sensitivedesign parameters are identified and discussed.

II ESD-MOS COMPACT MODEL

In order to support the following discussion, Figure 1shows schematically the NMOS cross-section with thecurrent components under ESD-stress.

Figure 2 presents the detailed schematic of the highcurrent MOS compact model. It consists of threedifferent modules which account for all possibleoperation modes of a MOS device under HBM stressconditions. In order to reproduce the parasitic lateralbipolar transistor of a MOS device, an extendedsnapback transistor model is connected in parallel tothe MOS module. This bipolar element is based on the‘π-form’ of a modified transport version Ebers-Mollapproach [8]. The avalanche current source within theBJT module is placed between the internal collectorand base node and models impact ionization withinthe reverse biased BC-junction. To consider the gatecoupling between MOS and inherent parasitic BJT,the following gate controlled avalanche current sourcewas implemented into the snapback transistor model