TI AM5728芯片创龙TL5728-IDK开发板规格书

全球LED驱动集萃目录台湾地区部分： (3)点晶科技股份有限公司 (3)台湾聚积科技公司 (3)台湾广鹏（富晶）科技公司 (4)台湾台晶科技 (4)台湾易亨电子公司 (4)台湾圆创科技股份有限公司 (4)台湾晶锜科技公司 (5)天鈺科技股份有限公司 (5)台湾飞虹积体电路有限公司 (5)台湾芯瑞科技股份有限公司 (5)台湾茂达电子公司 (5)日本部分： (5)东芝公司 (5)松下电器产业株式会社半导体社 (6)美国部分： (6)IR国际整流器公司 (6)ON安森美半导体 (6)美国超科公司(S UPERTEX) (6)TI美国德州仪器公司屏幕驱动部分 (7)TI美国德州仪器公司白光LED驱动器 (7)美国美信集成产品公司白光LED驱动器 (8)美国美信集成产品公司高亮度LED驱动器 (8)美国国家半导体公司新产品: (9)美国国家半导体公司白色LED低功率驱动部分 (9)美国国家半导体公司照明管理单元（LMU） (10)美国凌特公司白光背光及背光指示部分： (11)美国凌特公司全彩背光部分： (11)美国凌特公司大电流驱动及LED闪光灯部分： (12)飞兆半导体公司 (12)ADI美国模拟器件公司 (13)美国SIPEX公司 (13)美国PI(P OWER I NTEGRATIONS)公司 (13)美国PI(P OWER I NTEGRATIONS)公司数据手册 (13)美国PI(P OWER I NTEGRATIONS)公司IC产品系列参考 (13)美国加州Z YWYN 公司(美商齐荣)小屏背光部分 (14)美国加州Z YWYN 公司(美商齐荣)大尺寸嵌入式背光部分 (14)美国加州Z YWYN 公司(美商齐荣)工业照明部分 (14)美国灿瑞科技公司 (14)美商茂力公司(MPS) (14)美国CATALYST (15)欧洲英国IXYS半导体公司 (16)美国迈瑞半导体公司 (16)欧洲部分： (16)德国英飞凌 (16)奥地利微电子 (16)NXP荷兰皇家飞利浦公司I²C LED显示控制 (16)NXP荷兰皇家飞利浦公司高功率系统用SMPS芯片 (16)ST意法半导体公司显示器驱动器 (16)英国Z ETEX（捷特科）公司 (17)国内部分： (17)杭州士兰微电子有限公司 (17)深圳泉芯电子技木有限公司 (17)深圳光华源科技有限公司 (17)深圳国微电子股份有限公司 (17)深圳市彩拓科技开发有限公司 (17)华润矽威科技（上海）有限公司 (17)深圳市安联创科技有限公司 (18)LED屏幕配套部分逻辑IC，飞利浦些列： (18)LED 驱动配套部分 MOS管： (18)台湾地区部分：点晶科技股份有限公司DD311 单信道大功率恒流驱动IC最大1A最高耐压36V线性恒流IC 规格书DD312 单信道大功率恒流驱动IC最大1A最高耐压18V线性恒流IC 规格书DD313 三信道大功率恒流驱动IC 500mA R/G/B恒流驱动IC 规格书DM412 三通道装饰照明专用可直接数据级联恒流IC 200mA R/G/B恒流驱动IC 规格书DM413 三通道装饰照明专用PWM输出驱动IC 100mA R/G/B恒流驱动IC 规格书DM114A,DM115A 新版8位驱动IC 主要是用于屏幕及灯饰规格书DM115B通用8位恒流驱动IC 恒流一致性及稳定性高规格书DM11C 8位驱动IC 具有短断点侦测及温度保护功能，屏幕灯饰使用规格书DM13C 16位驱动IC 具有短断点侦测及温度保护功能，屏幕灯饰使用规格书DM13A 16位恒流驱动，面对低端屏幕客户规格书DM134,DM135, DM136 16位驱动IC 主要用于LED屏幕及护栏管规格书DM132 16位1024级PWM输出驱动IC 规格书DM137 16位开,短路,过温智能侦测驱动IC 规格书DM133 16位开路检测&64级电流调整&过温警示驱动IC 规格书DM163 8x3信道4096级PWM驱动IC 规格书DM621 4×3装饰照明专用PWM输出驱动恒流IC 规格书DM631 12比特内置PWM+实时检测恒流驱动IC 规格书DM632 16比特内置PWM+实时检测恒流驱动IC 规格书DM163 8×3通道4096级PWM输出恒流驱动IC 规格书DM164 8×3通道4096级PWM输出恒流驱动IC 规格书DD211 二倍升压驱动IC 2-3.3V 最大升压100mA固定式恒流IC 规格书DD231 3信道驱动IC 5-30mA 可设置小体上电即亮型IC 规格书DD233 4信道驱动IC 5-30mA 可设置小体、可开关型IC 规格书DD212 1.5-5.5V二倍升压最大400mA电流输出驱动单颗LED恒流IC 规格书PC112,PC113 2.8-5V四倍升压驱动20mA小功率多颗LED恒流IC 规格书ST2225A 35输出信道之数字/字母LED驱动芯片规格书台湾聚积科技公司MBI1801 1路恒流驱动1.2A电流可设定PWM信号灰度调节规格书MBI1802 2路恒流驱动360mA电流可两路单独设定PWM信号灰度调节规格书MBI1804 4路恒流驱动240mA电流可设定PWM信号灰度调节规格书MBI1816 16路恒流驱动电流可设定PWM信号灰度调节规格书MBI5016 16位最大90mA LED屏幕、护栏灯管恒流驱动IC 已停产规格书MBI5024 面对低端客户16位LED屏幕、护栏灯管恒流驱动IC 规格书MBI5025 16位最大45mALED屏幕、护栏灯管恒流驱动IC 规格书MBI5026 16位最大90mA LED屏幕、护栏灯管恒流驱动IC 规格书MBI5028 16位最大90mA LED屏幕、护栏灯管恒流驱动IC，具电流增益功能规格书MBI5030 16位内置PWM高灰阶LED恒流驱动IC 规格书MBI5031 16位内置PWM高灰阶LED恒流驱动IC，相对5030低端客户规格书MBI5039MBI5168 8位LED屏幕、护栏灯管恒流驱动IC 规格书MBI6010 3位级联式LED灯饰屏幕，R/G/B单独电流可设置恒流驱动IC 规格书台湾广鹏（富晶）科技公司A701、A702 固定式5-30mA灯饰恒流规格书A703 120mA可开式6-50V降压型恒流IC 规格书A705 220mA、2.7-12V固定降压型单路恒流IC 规格书A706 5-40mA、5-50V/PWM多路可开关型恒流IC 规格书AMC711x 固定式小电流灯饰应用规格书AMC711x_E 固定式小电流灯饰应用规格书AMC7135 2-6V 低压差固定式恒流驱动IC 1颗LED 规格书AMC7140 5-50V DC&DC 最大500mA电流可调，1颗或多颗LED驱动IC 规格书AMC7150 5-24V DC&DC 最大1.5A固定式， 1-3颗LED驱动IC 规格书AMC7169 LED保护IC 规格书台湾台晶科技T6309A 手机背光规格书T6309B 手机背光规格书T6313A 手机背光规格书T6319A 手机背光 LED并联固定电压背光驱动IC 规格书T6311A 路灯规格书T6316A/B 路灯规格书T6326A 手电式设备低压差电流多路可调400mA 规格书T6335A 矿灯低压差恒流式与AMC7135相同规格书T6336A 草坪灯用于主付灯矿灯规格书T6315A 草坪灯规格书T6317A MR16-1W 7-24V 350mA 1W多颗驱动IC 规格书T6325A MR16-3/5W 7-24V 700mA 多颗LED驱动IC 规格书T6327A 矿灯主付灯多电流可选固定式低压差是LED恒流驱动规格书T6329A磷酸铁锂电池矿灯升压式LED驱动恒流IC 规格书台湾易亨电子公司台湾圆创科技股份有限公司AT1325 8-bit Constant Current LED Sink Driver 规格书AT1326 16-bit Constant Current LED Sink Driver 规格书AT1313 Constant current LED driver 规格书AT1312 Boost constant current LED driver 规格书AT1314 Buck constant current LED driver 规格书台湾晶锜科技公司SCT2024 16位移位LED恒流驱动，适合目前LED大屏幕使用3-40mA 规格书SCT2026 16位移位LED恒流驱动，适合目前LED大屏幕使用3-90mA规格书SCT2210 16位移位LED恒流驱动，适合LED大屏幕及插件护栏管使用3-120mA 规格书SCT2110 8位移位LED恒流驱动IC，主要用于灯饰产品规格书SCT2512 12位移位护栏管专用IC，3路OE灰度可以单独调节规格书SCT2007 3路点光源驱动IC，可兼容MIB6010 规格书天鈺科技股份有限公司FP6742A 输入4.5-25V，输出8路小功率背光源升压驱动IC 规格书FP6742 输入4.5-25V，输出6路小功率背光源升压驱动IC 规格书FP6741 输入4.5-25V，输出10路小功率背光源升压驱动IC 规格书FP6732FP6700 高压驱动IC（类似HV9910）规格书FP6735 输入2.8-5.5升压驱动10pcs 25mA 规格书台湾飞虹积体电路有限公司台湾芯瑞科技股份有限公司SMD733 3-40V电压输入，内置MOS管降压型驱动电流1A 规格书SMD735 3-40V电压输入，降压型驱动电流700mA（可替代AMC7150）规格书SMD736 最高40V电压输入，内置MOS管降压型驱动电流3A 规格书SMD802 市电直驱1A LED驱动IC（可替代HV9910）规格书SMD911 市电直驱IC，外置MOS LED隔离方案驱动IC 规格书SMD912 市电隔离型直驱IC，外置MOS LED驱动IC 规格书台湾茂达电子公司APW7003APW7008APW7071APW7005日本部分：东芝公司TB62725 8位移位恒流驱动IC 规格书TB62726AN/AF 16位全彩LED大屏幕规格书TB62726ANG/AFG 16位全彩LED大屏幕规格书TCA62746AFG/AFNG 16位全彩LED大屏幕带断、短路侦测及温度保护规格书松下电器产业株式会社半导体社MIP551 电压输入（80～280 VAC）输出电流0.5 A 多颗LED应用规格书MIP552 电压输入（80～280 VAC）输出电流1 A 多颗LED应用规格书美国部分：IR 国际整流器公司IRS2540 200V市电直驱1W多颗LED驱动IC，500mA 规格书IRS2541 600V市电直驱1W多颗LED驱动IC，500mA 规格书ON 安森美半导体NCP5612 2通道泵式可PWM的白色LED驱动产品是LCD屏背光照明，操作模态 1 x 和 1.5 x 泵式驱动，87% 效率连同 0.2% 相配误差。

Features●High Performance, Low Power AVR ® 8-Bit Microcontroller Family ●Advanced RISC Architecture 131 Powerful Instructions – Most Single Clock Cycle Execution 32 x 8 General Purpose Working Registers Fully Static OperationUp to 20 MIPS Throughput at 20MHz On-chip 2-cycle Multiplier●High Endurance Non-volatile Memory Segments 4/8/16/32KBytes of In-System Self-Programmable Flash program memory 256/512/512/1KBytes EEPROM 512/1K/1K/2KBytes Internal SRAMWrite/Erase Cycles: 10,000 Flash/100,000 EEPROM Data retention: 20 years at 85°C/100 years at 25°C (1)Optional Boot Code Section with Independent Lock Bits●In-System Programming by On-chip Boot Program ●True Read-While-Write OperationProgramming Lock for Software Security●QTouch ® library support Capacitive touch buttons, sliders and wheels QTouch and QMatrix™ acquisition Up to 64 sense channels●Peripheral Features Two 8-bit Timer/Counters with Separate Prescaler and Compare ModeOne 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture ModemegaA VR ® Data SheetIntroductionThe ATmega48A/PA/88A/PA/168A/PA/328/P is a low power, CMOS 8-bit microcontrollers based on the AVR ® enhanced RISC architecture. By executing instructions in a single clock cycle, the devices achieve CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the sys-tem designer to optimize power consumption versus processing speed.2.OverviewThe ATmega48A/PA/88A/PA/168A/PA/328/P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, theATmega48A/PA/88A/PA/168A/PA/328/P achieves throughputs approaching 1 MIPS per MHz allowing thesystem designer to optimize power consumption versus processing speed.2.1Block DiagramFigure 2-1.Block DiagramThe AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.The ATmega48A/PA/88A/PA/168A/PA/328/P provides the following features: 4K/8Kbytes of In-SystemProgrammable Flash with Read-While-Write capabilities, 256/512/512/1Kbytes EEPROM, 512/1K/1K/2Kbytes SRAM, 23general purpose I/O lines, 32 general purpose working registers, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, a byte-oriented 2-wire Serial Interface, an SPI serial port, a 6-channel 10-bit ADC (8 channels in TQFP and VQFN packages), aprogrammable Watchdog Timer with internal Oscillator, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, USART, 2-wire Serial Interface, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low powerconsumption.Microchip offers the QTouch library for embedding capacitive touch buttons, sliders and wheels functionality into AVR® microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully debounced reporting of touch keys and includes Adjacent Key Suppression™ (AKS™) technology forunambiguous detection of key events. The easy-to-use QTouch Suite toolchain allows you to explore, develop and debug your own touch applications.The device is manufactured using Microchip’s high density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by aconventional non-volatile memory programmer, or by an On-chip Boot program running on the AVR core. The Boot program can use any interface to download the application program in the Application Flash memory.Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash ona monolithic chip, the ATmega48A/PA/88A/PA/168A/PA/328/P is a powerful microcontroller that provides ahighly flexible and cost effective solution to many embedded control applications.The ATmega48A/PA/88A/PA/168A/PA/328/P AVR is supported with a full suite of program and systemdevelopment tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-CircuitEmulators, and Evaluation kits.2.2Comparison Between ProcessorsThe ATmega48A/PA/88A/PA/168A/PA/328/P differ only in memory sizes, boot loader support, and interrupt vector sizes. Table 2-1 summarizes the different memory and interrupt vector sizes for the devices.Table 2-1.Memory Size SummaryATmega48A4KBytes256Bytes512Bytes 1 instruction word/vectorATmega48PA4KBytes256Bytes512Bytes 1 instruction word/vectorATmega88A8KBytes512Bytes1KBytes 1 instruction word/vectorATmega88PA8KBytes512Bytes1KBytes 1 instruction word/vectorATmega168A16KBytes512Bytes1KBytes 2 instruction words/vectorATmega168PA16KBytes512Bytes1KBytes 2 instruction words/vectorATmega32832KBytes1KBytes2KBytes 2 instruction words/vectorATmega328P32KBytes1KBytes2KBytes 2 instruction words/vector7.AVR CPU Core7.1OverviewThis section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts.Figure 7-1.Block Diagram of the AVR ArchitectureIn order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separatememories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory.This concept enables instructions to be executed in every clock cycle. The program memory is In-SystemReprogrammable Flash memory.The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two。

nRFxxx是一款多协议SoC（System on Chip），是挪威Nordic公司推出的一款低功耗蓝牙（Bluetooth）和2.4GHz无线通信技术的芯片。

它为物联网设备提供了一种高效的解决方案，可以广泛应用于智能家居、智能穿戴、工业控制等领域。

针对nRFxxx中文版规格书，我们需要了解以下几个方面的内容：一、nRFxxx的硬件特性1. 芯片体系结构：nRFxxx采用了ARM Cortex-M4处理器，集成了2.4GHz无线通信模块和丰富的外设接口。

该处理器能够提供稳定、高效的运算能力，为物联网设备的智能化提供了坚实基础。

2. 低功耗特性：nRFxxx采用了领先的功耗管理技术，能够在低功耗模式下保持稳定的通信连接，延长设备的使用时间，适应了物联网设备对长时间运行的需求。

3. 射频性能：nRFxxx内置了强大的射频前端，能够实现卓越的通信覆盖范围和抗干扰能力，确保设备稳定、高效地进行通信。

二、nRFxxx的软件特性1. 蓝牙4.2和5.1支持：nRFxxx支持蓝牙4.2和5.1标准，使其能够与多种蓝牙设备进行稳定、高效的连接和通信，满足了物联网设备对通信协议的多样化需求。

2. 多协议支持：nRFxxx支持同时运行蓝牙和其它2.4GHz无线通信协议，如BLE（低功耗蓝牙）、ANT和2.4GHz专有通信协议等，灵活地满足了不同物联网设备的通信需求。

3. 安全特性：nRFxxx内置了丰富的安全功能，包括加密引擎、安全协议栈和随机数生成器等，保障了物联网设备的通信安全和数据隐私。

三、nRFxxx的开发支持1. 开发工具链：nRFxxx提供了丰富的开发工具链，包括nRF Connect SDK、nRF5 SDK和Keil MDK等，简化了物联网设备的软件开发流程，提高了开发效率。

2. SDK支持：nRFxxx的SDK（Software Development Kit）提供了丰富的示例代码和API，帮助开发人员快速搭建原型，加速产品上市时间。

USB Operating ModesThe role the USB controller takes depends on the way the devices are cabled together. Each USB cable has an A and a B device end. If the A end of the cable is plugged into the device containing the USB controller, the USB control-ler takes the role of the host device. It goes into host mode (in this case, the USB_DEV_CTL.HOSTMODE bit is set to 1). If the B of the cable is plugged in, the USB controller goes instead into peripheral mode (and theUSB_DEV_CTL.HOSTMODE bit remains at 0).When both devices contain dual role controllers, signaling can be used to switch the roles of the two devices, with-out switching the cable connecting the two devices. See Host Negotiation Protocol for details on the conditions un-der which the USB controller can switch between peripheral and host mode.NOTE:The multi-point capability of the USB controller is associated with a range of registers recording the allo-cation of device functions to individual endpoints and device function characteristics. These characteris-tics include endpoint number, operating speed, and transaction type on an endpoint-by-endpoint basis.These registers are principally associated with the use of the USB controller as the host to a number ofdevices. However, set the registers when the core is used as the host for a single target device.To enable the USB:1.Configure the USB PLL multiplier settings in the USB PLL control register. Check the processor data sheet forthe requirements for input clock frequency.2.Enable the USB PHY by setting the USB_PHY_CTL.EN bit.3.Poll the bit in the USB PLL control register to ensure that the USB PLL has locked to the new frequency. Peripheral ModeUSB OTG interface operations for the peripheral mode differ from host mode in a number of ways. The following sections describe peripheral mode operations.Endpoint SetupIn peripheral mode, the USB uses a few endpoint-specific configuration bits when setting up an endpoint for trans-fer for all types of peripheral transfer. The configuration determines how the processor core interacts with the end-point FIFO.One key parameter required before a transfer can occur through an endpoint is the maximum USB packet size that the endpoint can support. The software sets this value. It depends on various system constraints. These constraints include the size of hardware FIFO available and system latencies as well as the USB transfer type and class used. The USB_EP[n]_TXMAXP or USB_EP[n]_RXMAXP registers define the maximum amount of data that can be transfer-red to the selected endpoint in a single frame. The value must match the programmed maximum individual packet size (MaxPktSize) of the standard endpoint descriptor for the endpoint.For transmit endpoints, program the maximum packet size using the USB_EP[n]_TXMAXP. For receive endpoints, the USB uses the USB_EP[n]_RXMAXP register. The maximum packet size must not exceed the actual hardware endpoint FIFO size.USB Architectural ConceptsThe USB controller, as part of its support for multiple devices, permits individual allocation of the functions of the target to the different Rx and Tx endpoints implemented. Furthermore, the USB controller can make this allocation dynamically, allowing the devices from the targeted peripheral list to be used in different combinations. The num-bers of Tx and Rx endpoints implemented in the controller limit the combinations of peripheral devices that can be used together. Devices can only be added where the required endpoints remain available.On-Chip Bus InterfacesThe USB controller uses two 32-bit wide independent bus interfaces, a master and a slave, to communicate with a processor-based subsystem. The slave interface allows the processor core to access the control and status registers (including DMA master registers) and the endpoint FIFOs. The integrated DMA uses the master interface to drive data into or out of the endpoint FIFOs with minimal processor core interaction. For more information, see USB Block Diagram.FIFO ConfigurationEach bidirectional endpoint (provided as two unidirectional endpoints) has its own endpoint number (0 for control, 1 on up for data transfer). Although two endpoints could use the same number, the endpoints can support different transfer types. Each of these bidirectional endpoints has a fixed region of the SRAM in the USB controller to which it has access. This feature dictates to some extent the types of transfers that can be used for that particular endpoint. This restriction follows from the maximum size of USB packets, which varies with each transfer type. The FIFO Sizes and Transfer Types table lists the endpoint FIFO configuration, with an indication of the transfer types possi-ble for that particular buffer size.Each endpoint FIFO can buffer one or two packets (in double-buffered mode). Double-buffering is recommended for most applications to improve efficiency by reducing the frequency of servicing for each endpoint.Double-buffering bulk transactions means that data transfers over the USB are not slowed when packets are loaded or unloaded from the FIFO in the time it takes to transfer a packet. Double-buffering isochronous transactions al-lows more time to load or unload the FIFO. It also allows the usage of the SOF interrupt to service the endpoint rather than the endpoint interrupt. This functionality has the following advantages:•Easy detection of lost packets•Regular interrupt timing (making it easier to source or sink the data)USB Functional DescriptionADSP-BF70x USB Interrupt List。

i.MX 6UltraLite Applications Processors for Industrial Products, Rev. 2.2, 05/201724NXP Semiconductors Electrical characteristicsTable 12 shows on-chip LDO regulators that can supply on-chip loads.4.1.4External clock sourcesEach i.MX 6UltraLite processor has two external input system clocks: a low frequency (RTC_XTALI) and a high frequency (XTALI).DDR I/O supply NVCC_DRAM LPDDR21.14 1.2 1.3V —DDR3L1.28 1.35 1.45V —DDR31.43 1.5 1.575V —NVCC_DRAM2P5— 2.25 2.5 2.75V —GPIO supplies NVCC_CSI— 1.65 1.8,2.8,3.3 3.6V All digital I/O supplies (NVCC_xxxx) must be powered (unless otherwise specified in this data sheet) under normal conditions whether the associated I/O pins are in use or not.NVCC_ENETNVCC_GPIONVCC_UARTNVCC_LCDNVCC_NANDNVCC_SD1A/D converter VDDA_ADC_3P3— 3.0 3.15 3.6V VDDA_ADC_3P3 must bepowered when chip is in RUNmode, IDLE mode, or SUSPENDmode.VDDA_ADC_3P3 should not bepowered when chip is in SNVSmode.Temperature Operating RangesJunctiontemperature Tj Industrial -40—105o C See the application note, i.MX 6UltraLite Product Lifetime UsageEstimates for information onproduct lifetime (power-on years)for this processor.1Applying the maximum voltage results in maximum power consumption and heat generation. NXP recommends a voltage set point = (V min + the supply tolerance). This result in an optimized power/speed ratio.2In setting VDD_HIGH_IN voltage, refer to the Errata ERR010690 (SNVS_LP Registers Reset Issue).3In setting VDD_SNVS_IN voltage with regards to Charging Currents and RTC, refer to the i.MX 6UltraLite Hardware Development Guide (IMX6ULHDG).Table 12. On-Chip LDOs 1 and their On-Chip Loads1On-chip LDOs are designed to supply i.MX6UltraLite loads and must not be used to supply external loads.Voltage SourceLoad Comment VDD_HIGH_CAPNVCC_DRAM_2P5Board-level connection to VDD_HIGH_CAP Table 11. Operating Ranges (continued)Electrical characteristicsi.MX 6UltraLite Applications Processors for Industrial Products, Rev. 2.2, 05/2017NXP Semiconductors 25The RTC_XTALI is used for low-frequency functions. It supplies the clock for wake-up circuit,power-down real time clock operation, and slow system and watch-dog counters. The clock input can be connected to either external oscillator or a crystal using internal oscillator amplifier. Additionally, there is an internal ring oscillator, which can be used instead of the RTC_XTALI if accuracy is not important.The system clock input XTALI is used to generate the main system clock. It supplies the PLLs and other peripherals. The system clock input can be connected to either external oscillator or a crystal using internal oscillator amplifier.Table 13 shows the interface frequency requirements.The typical values shown in Table 13 are required for use with NXP BSPs to ensure precise time keeping and USB operation. For RTC_XTALI operation, two clock sources are available.•On-chip 40 kHz ring oscillator—this clock source has the following characteristics:—Approximately 25 µA more Idd than crystal oscillator—Approximately ±50% tolerance—No external component required—Starts up quicker than 32 kHz crystal oscillator•External crystal oscillator with on-chip support circuit:—At power up, ring oscillator is utilized. After crystal oscillator is stable, the clock circuitswitches over to the crystal oscillator automatically.—Higher accuracy than ring oscillator—If no external crystal is present, then the ring oscillator is utilizedThe decision of choosing a clock source should be taken based on real-time clock use and precision time-out.4.1.5Maximum supply currentsThe data shown in Table 14 represent a use case designed specifically to show the maximum current consumption possible. All cores are running at the defined maximum frequency and are limited to L1 cache accesses only to ensure no pipeline stalls. Although a valid condition, it would have a very limited practical use case, if at all, and be limited to an extremely low duty cycle unless the intention was to specifically show the worst case power consumption.Table 13. External Input Clock Frequency Parameter DescriptionSymbol Min Typ Max Unit RTC_XTALI Oscillator 1,21External oscillator or a crystal with internal oscillator amplifier.2The required frequency stability of this clock source is application dependent. For recommendations, see the Hardware Development Guide for i.MX 6UltraLite Applications Processors (IMX6ULHDG).f ckil —32.7683/32.03Recommended nominal frequency 32.768kHz.—kHz XTALI Oscillator 2,44External oscillator or a fundamental frequency crystal with internal oscillator amplifier.f xtal —24—MHz。

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters andother important disclaimers. PRODUCTION DATA.1 TMS320C6678 Features and Description1.1Features•Eight TMS320C66x™ DSP Core Subsystems (C66x CorePacs), Each with– 1.0 GHz, 1.25 GHz, or 1.4 GHz C66x Fixed/Floating-Point CPU Core›44.8 GMAC/Core for Fixed Point @ 1.4 GHz›22.4 GFLOP/Core for Floating Point @ 1.4 GHz–Memory›32K Byte L1P Per Core›32K Byte L1D Per Core›512K Byte Local L2 Per Core•Multicore Shared Memory Controller (MSMC)–4096KB MSM SRAM Memory Shared by Eight DSP C66x CorePacs–Memory Protection Unit for Both MSM SRAM and DDR3_EMIF•Multicore Navigator–8192 Multipurpose Hardware Queues with Queue Manager–Packet-Based DMA for Zero-Overhead Transfers•Network Coprocessor–Packet Accelerator Enables Support for›Transport Plane IPsec, GTP-U, SCTP, PDCP›L2 User Plane PDCP (RoHC, Air Ciphering)›1-Gbps Wire-Speed Throughput at 1.5 MPackets Per Second–Security Accelerator Engine Enables Support for›IPSec, SRTP, 3GPP, WiMAX Air Interface, and SSL/TLS Security›ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC, CMAC,GMAC, AES, DES, 3DES, Kasumi, SNOW 3G, SHA-1,SHA-2 (256-bit Hash), MD5›Up to 2.8 Gbps Encryption Speed •Peripherals –Four Lanes of SRIO 2.1› 1.24/2.5/3.125/5 GBaud Operation Supported Per Lane ›Supports Direct I/O, Message Passing ›Supports Four 1×, Two 2×, One 4×, and Two 1× +One 2× Link Configurations –PCIe Gen2›Single Port Supporting 1 or 2 Lanes ›Supports Up To 5 GB aud Per Lane –HyperLink ›Supports Connections to Other KeyStone Architecture Devices Providing Resource Scalability ›Supports up to 50 Gbaud –Gigabit Ethernet (GbE) Switch Subsystem ›Two SGMII Ports ›Supports 10/100/1000 Mbps Operation –64-Bit DDR3 Interface (DDR3-1600)›8G Byte Addressable Memory Space –16-Bit EMIF –Two Telecom Serial Ports (TSIP)›Supports 1024 DS0s Per TSIP ›Supports 2/4/8 Lanes at 32.768/16.384/8.192 Mbps Per Lane –UART Interface –I 2C Interface –16 GPIO Pins –SPI Interface –Semaphore Module –Sixteen 64-Bit Timers –Three On-Chip PLLs•Commercial Temperature:–0°C to 85°C•Extended Temperature:–-40°Cto100°CTMS320C6678Multicore Fixed and Floating-Point Digital Signal ProcessorSPRS691E—March 2014 For fixed-point use, the C66x core has 4× the multiply accumulate (MAC) capability of C64x+ cores. In addition, the C66x core integrates floating point capability and the per-core raw computational performance in an industry-leading 44.8GMACS/core and 22.4GFLOPS/core (@1.4GHz operating frequency). It can execute 8 single-precision floating point MAC operations per cycle and can perform double- and mixed-precision operations, and is IEEE754 compliant. The C66x core incorporates 90 new instructions (compared to the C64x+ core) targeted for floating point and vector math oriented processing. These enhancements yield sizeable performance improvements in popular DSP kernels used in signal processing, mathematical, and image acquisition functions. The C66x core is backwards code-compatible with TI's previous generation C6000 fixed and floating point DSP cores, ensuring software portability and shortened software development cycles for applications migrating to faster hardware.The C6678 DSP integrates a large amount of on-chip memory. In addition to 32KB of L1 program and data cache, there is 512KB of dedicated memory per core that can be configured as mapped RAM or cache. The device also integrates 4096KB of Multicore Shared Memory that can be used as a shared L2 SRAM and/or shared L3 SRAM. All L2 memories incorporate error detection and error correction. For fast access to external memory, this device includes a 64-bit DDR-3 external memory interface (EMIF) running at 1600 MHz and has ECC DRAM support. This family supports a plethora of high speed standard interfaces including RapidIO ver 2, PCI Express Gen2, and Gigabit Ethernet, as well as an integrated Ethernet switch. It also includes I2C, UART, Telecom Serial Interface Port (TSIP), and a 16-bit EMIF, along with general purpose CMOS IO. For high throughput, low latency communication between devices or with an FPGA, this device also sports a 50-Gbaud full-duplex interface called HyperLink. Adding to the network awareness of this device is a network co-processor that includes both packet and optional security acceleration. The packet accelerator can process up to 1.5 M packets/s and enables a single IP address to be used for the entire multicore C6678 device. It also provides L2 to L4 classification, along with checksum and QoS capabilities. The C6678 device has a complete set of development tools, which includes: an enhanced C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.Copyright 2014 Texas Instruments Incorporated TMS320C6678 Features and Description3 Submit Documentation Feedback。

7V, 3A1 特性● 高效电源开关☆ 内部集成35m Ω导通电阻、18V 高耐A 智能识别与LED 显示充电端口电源开关高耐压MOS 开关， 2 典型应用● 智能排插 ● 便携式充电设备 PL5802 深圳芯派科技ＴＥＬ：１３５　３０４５　２６４６　（唐生）ＩＣＱ：２９４　４３４　３３６２ＩＣＱ：２９４　４３５　３３６２5 引脚定义及功能6 订单信息7.4 温度特性(注 3)注:4) 设计参数保证，批量生产不测试。

8 应用指南8.1 概述将输出电流降低到几微安。

PL58028.5 温度保护PL5802具有温度保护功能，通过内部温运行，芯片温度高于设定OTP阈值时，PL59 应用和设计9.1 输入输出电容输入输出电容提升了芯片的应用品质，或者更大的陶瓷旁路电容连接于Vin和GND 解电容吸收输入尖峰浪涌电压。

我们建议所有应用都应在输出加上至少10 PCB 布局11.1 布板指南1. PL5802 摆放。

将PL5802放置于靠近USB的输出控制器，2. 输入旁路电容在VIN的PIN附近放置10uF的陶瓷旁路电容需要另外一个470uF电解电容来吸收热插拔11.2 PCB布局实例内部温度检测电路，侦测工作时候的功率开关温度。

当设备PL5802将关闭电源开关，温度降低前，电源开关将不会被打品质，电容的选取需要根据实际应用进行优化，对于所有的应用GND之间，当输入电源存在热插拔操作时，可能需要更大的上至少4.7uF或者更大的陶瓷旁路电容,应用减少瞬态大电流对制器，最好在VBUS端增加一个10μF 的滤波电容。

路电容，使PCB中VIN的OIN脚到电容的距离尽可能短。

在存热插拔引起的输入电压尖峰。

Fig. 3 布板实例当设备在过流状态下以恒流模式会被打开，直到接触过温状态。

的应用场合，我们建议将4.7uF 更大的输入电容，例如470uF电电流对电源开关的影响。

在存在热插拔操作时，可能还序号 元件名称 元件编号1 贴片电容 C1, C2 贴片电阻 R1,3 贴片电阻 R34 贴片IC U15 黄色LED灯 LED6 红色LED灯 LED27 USB序号 元件名称 元件编号1 贴片电容 C1, C3 贴片电阻 R34 贴片IC U16 USB PL5802A BOM清单件编号 元件规格 封装 C1, C2 10uF/10V 1206 R2 1K 5% 0603 R3 2.2K 1% 0603 U1 PL5802A TSOT23-6 LED1 0603 LED2 0603单口USBPL5802B BOM清单件编号 元件规格 封装 C1, C2 10uF/10V 1206 R3 2.2K 1% 0603 U1 PL5802B TSOT23-6单口USB 数量 2 2 1 1 1 1 1数量 2 1 1 112 封装信息宝砾公司对本文件中可能出现的任何错误不公司不承担因应用或使用本协议所述的任何产品首席执行官书面批准，不得被作为生命维持设备偿。

Syntax ConventionsSyntax ConventionsThe Blackfin+ processor instruction set supports several syntactical conventions that appear throughout this docu-ment. These conventions relate to case sensitivity, free format, instruction delimiting, and comments.Case SensitivityThe instruction syntax is case insensitive. The assembler treats register names and instruction keywords in a case-insensitive manner (i.e., R3.l, R3.L, r3.l, and r3.L are all valid, equivalent input to the assembler).In explanations and descriptions throughout this manual, upper case is used to help the register names and keywords stand out among normal text.Free FormatAssembler input is free format and may appear anywhere on the line. One instruction may extend across multiple lines, or more than one instruction may appear on the same line, and white space (e.g., space, tab, or a new line) may appear anywhere between tokens. A token must not have embedded spaces. Tokens include numbers, register names, keywords, user identifiers, and also some multi-character special symbols like "+=", "/*", or "||". Instruction DelimitingA semicolon must terminate every instruction. Several instructions can be placed together on a single line at the programmer's discretion, provided each instruction ends with a semicolon.Each complete instruction must end with a semicolon. Sometimes, a complete instruction will consist of more than one operation. There are two cases where this occurs.•T wo general operations are combined to be issued across multiple computation units. In this case, a comma separates the different parts:a0 = r3.h * r2.l , a1 = r3.l * r2.h ;• A general instruction is combined with one or two memory accesses as a multi-issue instruction. The latter portions of instructions like these are separated by the parallel-issue "||" token. For example:a0 = r3.h * r2.l || r1 = [p3++] || r4 = [i2++] ;CommentsThe assembler supports various kinds of comments, including:•End of line: A double forward slash token ("//") indicates the beginning of a comment that concludes at the next new line character.•General comment: A general comment begins with the "/*" token and ends with the "*/" token. It may con-tain any characters and extend over multiple lines.Comments are not recursive; if the assembler sees a "/*" within a general comment, it issues an assembler warning at build-time.Notation ConventionsNotation ConventionsThis manual and the assembler use the following conventions:•Register names are alphabetical, followed by a number in cases where there are more than one register in a logi-cal group. Thus, examples include ASTAT, FP, M2, and R3.•Register names are reserved and may not be used as program identifiers.•Some operations (such as the Move Register instruction) require a register pair. Register pairs are always Data Registers or Accumulators and are denoted using a colon, for example, R3:2. The larger number must be writ-ten first. Note that the hardware supports only odd-even pairs, for example, R7:6, R5:4, R3:2, R1:0 and A1:0.•Some instructions (such as the --SP (Push Multiple) instruction) require a group of adjacent registers. Adjacent registers are syntactically denoted with the range enclosed in parentheses and separated by a colon. For exam-ple, the range of data registers comprised of R3, R4, R5, R6, and R7 is written in this instruction as R7:3. Again, the larger number appears first.•Portions of a particular register may be individually specified by using the dot (".") syntax following the register name, followed by a letter denoting the desired portion. For 32-bit registers, ".H" denotes the most-significant ("High") 16 bits, whereas ".L" denotes the least-significant 16 bits. Similar access control is available for the 40-bit accumulator registers, which is discussed later.This manual uses the following conventions.•When there is a choice of any one register within a register group, this manual shows the register set using a dash ("-"). For example, "R7-0" in text means that any one of the eight data registers (R7, R6, R5, R4, R3, R2, R1, or R0) can be used in the syntax for the instruction.•Immediate values are designated as "imm" with the following modifiers:•"imm" indicates a signed integer and is followed by an integer value indicating how many bits are required to represent it in binary (e.g., imm7 is a signed 7-bit value).•The "u" prefix indicates an unsigned value (e.g., uimm4 is an unsigned 4-bit value).•The "m" suffix followed by a number can be appended to provide added alignment requirements. For ex-ample, uimm16m2 is an unsigned, 16-bit integer that must be an even number, and imm7m4 is a signed,7-bit integer that must be a multiple of four.•PC-relative, signed values are designated as "pcrel" and have the following modifiers:•the decimal number indicates how many bits are required to represent the value in bianry (e.g., pcrel5 is a 5-bit value).•any alignment requirements are designated by an optional "m" suffix followed by a number (e.g., pcrel13m2 is a 13-bit integer that must be an even number).•Loop PC-relative, signed values are designated as "lppcrel" with the following modifiers:Glossary•the decimal number indicates how many bits are required to represent the value in binary (e.g., lppcrel5 is a 5-bit value).•any alignment requirements are designated by an optional "m" suffix followed by a number (e.g., lppcrel11m2 is an 11-bit integer that must be an even number).GlossaryThe following terms appear throughout this document. Without trying to explain the Blackfin+ processor, here are the terms used along with their definitions.Register NamesThe architecture includes the registers shown in the Registers table.。