下载文档原格式
VLSI复习题型：缩写5题10分简答12题60分计算3题30分Chapter 011.How to evaluate performance•Cost•Reliability•Speed (delay, operating frequency)•Power dissipation2.Regenerative property3.Delay :Chapter 021.Inverter layout2.Photolithography process1)Oxidation layering(氧化层)2)Pthotoresist coating（涂光刻胶）3)Stepper exposure（光刻机曝光）4)Photoresist development and bake(光刻胶的显影和烘干)5)Acid etching（酸刻蚀）6)Spin, rinse, and dry（旋转，清洗和干燥）7)Various process steps：Ion implantation（离子注入）Plasma etching（等离子刻蚀）Metal deposition（金属沉淀）8)Photoresist removal( or ashing) 去除光刻胶（即“沙洗”）Chapter 031.Linear/ Saturation mode2.Long channel vs short channel3.Capacitances= structure capacitances+channel capacitances+MOS diffusion capacitances4.Resistance=MOS sructure resistance+source and drain resistance+cantact resistance+wiringresistanceWith silicidation R方块ˆ is reduced to the range 1 to 4 Ω/方块（source and drain resistance）Chapter 041.C wire = C pp + C fringe + C interwire2.Dealing with resistance:1)Use better interconnect materials2)More interconnect layers3.RC Mode•Lumped RC model–total wire resistance is lumped into a single R and total capacitance into a single C–good for short wires; pessimistic and inaccurate for long wires•Distributed RC model–circuit parasitics are distributed along the length, L, of the wire4.DelayDelay of a wire is a quadratic function of its length, LThe delay is 1/2 of that predicted (by the lumped model)5.Reflection coefficient【画传输图（or 波形），计算题】Chapter 051.V M∝(W/L)p/(W/L)nIncreasing the width of the PMOS moves V M towards V DD,‰Increasing the width of theNMOS moves V M towards GND.2.Delay3.Power in CMOS1.Dynamic power consumption: charging and discharging capacitors;Not a function of transistor sizes;Need to reduce C L,Vdd,and f to reduce power.2.Short circuit currents: short circuit path supply rails during switching;Keep the input and output rise/fall times the same;If Vdd<Vtn+|Vtp|,then short-circuit power can be eliminated.3.Leakage: leaking diodes and transistors4.Technology scaling modelsFull scalingFixed voltage scalingGeneral scalingChapter 061.Static CMOS- output connected to either Vdd or GND via a low-resistance path⏹High noise margins⏹Low output impedance, high input impedance⏹No steady state path between Vdd and GND⏹Delay is a function of load capacitance and transistor resistanceDynamic CMOS--relies on temporary storage of signal values on capacitance of high-impedance circuit nodes.⏹Simpler, faster gates⏹Increased sensitivity to noise2.Static vs dynamic circuit⏹In static circuit at every point in time (except when switching) the output is connectedto either GND or V DD via a low resistance path.--fan-in of N requires 2N devices⏹Dynamic circuits rely on the temporary storage of signal values on the capacitance ofhigh impedance nodes--requires only N+2 transistors--takes a sequence of precharge and conditional evaluation phases to realize logicfunctions.●conditions on output1) once the optput of a dynamic gate is discharged, it cannot be charged again until thenext precharge opreation.2) Inputs to the gate can make at most one transition during evaluation.3) Output can be in the high impedance state during and after evaluation(PDN off), stateis stored in C L.●Properties of Dynamic Gates1)Logic function is implemented by the PDN only–number of transistors is N + 2 (versus 2N for static complementary CMOS)–should be smaller in area than static complementary CMOS2)Full swing outputs (VOL = GND and VOH = VDD)3)Nonratioed--sizing of the devices is not important for proper functioning (only for performance)4) Faster switching speeds5) Power dissipation should be better- consumes only dynamic power –no short circuit power consumption since the pull- up path is not on when evaluating-lower C L--both C int(since there are fewer transistors connected to the drain outpu t) and C ext(since there the output load is one per connectedgate, not two) -by construction can have at most one transition per cycle – no glitching6) Needs a percharge clockbinational vs Sequential logic4.Why PMOS in PUN and NMOS in PDN?Threshold drops5.Ratioed logic: Pseudo-NMOS→Small area and load, but static power dissipationChapter 07tch vs Register⏹Latch: level sensitive----As for positive: passes inputs to Q when the clock is high----transparent mode;When clock is low----hold mode⏹Flip-flop: edge sensitive2.Bistable circuit:The cross coupling of two inverters results in a bistablecircuit (a circuit with two stable states)⏹Have to be able to change the stored value by making A (or B) temporarily unstable byincreasing the loop gain to a value larger than 1Done by applying a trigger pulse at Vi1 or Vi2the width of the trigger pulse need be only a little larger than the total propagation delayaround the loop circuit (twice the delay of an inverter)⏹Two approaches used1.cutting the feedback loop (mux based latch)2.overpowering the feedback loop (as used in SRAMs)3.MS ET timing properties⏹Set-up time: time before rising edge of clk that D must be valid⏹Propagation delay: time for QM to reach Q⏹Hold time: time D must be stable after rising edge of clk4.Pipelining5.Schmitt Trigger(rise—P; fall—N)Chapter 091.Cross Talk: An unwanted coupling from a neighboring signal wire to a network nodeintroduces an interference that is generally called cross talk.2.Dealing with Capacitive Cross Talk•Avoid floating nodes•Protect sensitive nodes•Make rise and fall times as large as possible•Differential signaling•Do not run wires together for a long distance•Use shielding wires•Use shielding layers3.Cross Talk and Performance: when neighboring lines switch in opposite direction of victimline, delay increases.4.Impact of resistance is commonly seen in power supply distribution:–IR drop–Voltage variationsChapter 101.Clock Nonidealities:⏹Clock skew: Spatial variation in temporally equivalent clock edges;⏹Clock jitter: Temporal variations in consecutive edges of the clock signal⏹Variation of the pulse width2.Clock Uncertainties----Source of clock uncertainty（图形填空）（重点）简答题：•Clock‐Signal Generation (1)•Manufacturing Device Variations (2)•Interconnect Variations (3)•Environmental Variations (4 and 5)•Capacitive Coupling (6 and 7)3.Impact of Positive/Negative Clock Skew and Clock jitter (重点)1.Positive clock skew:Clock and data flow in the same direction2.Negative clock skew: Clock and data flow in opposite directions3.Jitter cause T to vary on a cycle-by-cycle basisCombined impact of skew and jitter:Constraints on the minimum clock period (positive)4.To reduce dynamic power, the clock network must support clock gating (shutting down(disabling the clock ) units)5. Clock distribution techniques--Balanced paths(H-tree network, matched RC trees)--Clock grids: minimize absolute delay6.Matched RC trees, represents a floor plan that distributes the clock signal so that the interconnections carrying the clock signals to the functional subblocks are of equal length.7. 彩图9：The unbalanced load creates a large skew, by careful tuning of the wire width, the load is balanced, minimizing the skew.8. Dealing with Clock Skew and Jitter•To minimize skew, balance clock paths using H-treeor matched-tree clock distribution structures. •If possible, route data and clock in opposite directions;eliminates races at the cost of performance.•The use of gated clocks to help with dynamic power consumption make jitter worse.•Shield clock wires (route power lines –VDD or GND –next to clock lines) to minimize/eliminate coupling with neighboring signal nets.•Use dummy fills to reduce skew by reducing variations in interconnect capacitances dueto interlayer dielectric thickness variations.•Beware of temperature and supply rail variations and their effects on skew and jitter. •Power supply noise fundamentally limits the performance of clock networks.Chapter 111.Full adder(P=A+B)2.Static vs dynamic Manchester Carry ChainStatic dynamic3.Square Root Carry Select Adder (PPT 24)4.Wallace‐Tree Multiplier(PPT 32)5.Logarithmic ShifterChapter 121.Semiconductor Memory Classification2.Bit line & word line3.Memory Timing(DRAM vs SRAM)DRAM: Multiplexde AddressingSRAM: Self-timed Address Switching/Changing 4.MOS OR ROM5. SRAM vs DRAM6. DRAM Timing7. SRAM ATD(Address Transition Detection)Chapter 131.Two Important Test Properties•Controllability ‐measures the ease of bringing anode to a given condition using only the input pins•Observability ‐measures the ease of observing thevalue of a node at the output pins2.Test Approaches•Ad‐hoc testing•Scan based test•Self test3.Scan Register11。
1．集成电路的发展过程经历了哪些发展阶段？划分集成电路的标准是什么？集成电路的发展过程:•小规模集成电路(Small Scale IC，SSI)•中规模集成电路(Medium Scale IC，MSI)•大规模集成电路(Large Scale IC，LSI)•超大规模集成电路(Very Large Scale IC，VLSI)•特大规模集成电路(Ultra Large Scale IC，ULSI)•巨大规模集成电路(Gigantic Scale IC，GSI）划分集成电路规模的标准2．超大规模集成电路有哪些优点？1. 降低生产成本VLSI减少了体积和重量等,可靠性成万倍提高,功耗成万倍减少.2.提高工作速度VLSI内部连线很短,缩短了延迟时间.加工的技术越来越精细.电路工作速度的提高,主要是依靠减少尺寸获得.3. 降低功耗芯片内部电路尺寸小,连线短,分布电容小,驱动电路所需的功率下降.4. 简化逻辑电路芯片内部电路受干扰小,电路可简化.5.优越的可靠性采用VLSI后，元件数目和外部的接触点都大为减少，可靠性得到很大提高。
6.体积小重量轻7.缩短电子产品的设计和组装周期一片VLSI组件可以代替大量的元器件,组装工作极大的节省,生产线被压缩,加快了生产速度.3．简述双阱CMOS工艺制作CMOS反相器的工艺流程过程。
1、形成N阱2、形成P阱3、推阱4、形成场隔离区5、形成多晶硅栅6、形成硅化物7、形成N管源漏区8、形成P管源漏区9、形成接触孔10、形成第一层金属11、形成第一层金属12、形成穿通接触孔13、形成第二层金属14、合金15、形成钝化层16、测试、封装，完成集成电路的制造工艺4．在VLSI设计中，对互连线的要求和可能的互连线材料是什么？互连线的要求低电阻值：产生的电压降最小；信号传输延时最小（RC时间常数最小化）与器件之间的接触电阻低长期可靠工作可能的互连线材料金属（低电阻率），多晶硅（中等电阻率），高掺杂区的硅(注入或扩散)（中等电阻率）5．在进行版图设计时为什么要制定版图设计规则？—片集成电路上有成千上万个晶体管和电阻等元件以及大量的连线。
《超大规模集成电路物理设计：从图分割到时序收敛》读书笔记目录一、内容概览 (1)二、关于本书的背景知识介绍 (2)三、内容概览 (3)3.1 主要章节概述 (4)3.2 重点概念解析 (6)四、详细读书笔记 (7)五、本书中的关键观点和论点分析 (8)5.1 关于超大规模集成电路物理设计的关键观点 (10)5.2 书中论点的深度分析 (11)六、比较与评价 (13)6.1 本书与其他相关书籍的比较 (14)6.2 本书的优点与不足评价 (15)七、实践应用与案例分析 (16)7.1 书中理论在实际设计中的应用 (18)7.2 案例分析 (19)八、总结与心得体会 (21)8.1 本书的主要收获和启示 (22)8.2 个人对超大规模集成电路物理设计的未来展望 (23)一、内容概览《超大规模集成电路物理设计：从图分割到时序收敛》是一本深入探讨超大规模集成电路（VLSI）物理设计过程的著作。
本书从图分割的基本原理出发，详细阐述了集成电路设计的各个阶段，包括布局、布线、时序分析和验证等。
在图分割部分，本书介绍了如何将复杂的集成电路设计问题简化为更易于处理的子问题。
通过图论和计算机辅助设计（CAD）技术，作者提出了一系列高效的图分割算法，从而为后续的物理设计过程奠定了坚实的基础。
在布局阶段，本书重点讨论了如何根据电路结构和约束条件选择合适的布局算法。
作者详细分析了不同布局策略的优缺点，并提出了针对复杂电路的优化方法。
布线是集成电路设计中的关键步骤之一，本书介绍了多种布线算法，包括基于启发式的布线方法、基于物理约束的布线方法和基于人工智能技术的布线方法等。
作者还探讨了布线过程中的优化问题和挑战。
时序分析是确保集成电路正常工作的关键环节，本书详细阐述了时序分析的基本原理和方法，包括静态时序分析、动态时序分析和时序收敛等。
作者通过理论分析和实例验证，介绍了如何有效地进行时序分析和优化，以确保设计的集成电路具有良好的时序性能。
目录摘要 (1)关键词 (1)Abstract (1)Key words (1)1 引言 (1)2 超大规模集成电路的设计要求 (1)3 超大规模集成电路的设计策略 (2)3.1层次性 (2)3.2模块化 (2)3.3规则化 (2)3.4局部化 (2)4 超大规模集成电路的设计方法 (3)4.1 全定制设计方法 (3)4.2 半定制设计方法 (4)4.3 不同设计方法的比较 (5)5 超大规模集成电路的设计步骤 (6)5.1 系统设计 (7)5.2 功能设计 (7)5.3 逻辑设计 (7)5.4 电路设计 (7)5.5 版图设计 (7)5.6 设计验证 (8)5.7 制造 (8)5.8 封装和测试 (8)6 超大规模集成电路的设计流程 (8)6.1 总体的设计流程 (8)6.1.1高层次综合 (8)6.1.2逻辑综合 (8)6.1.3 物理综合 (9)6.2 详细的设计流程 (9)7 超大规模集成电路的验证方法 (9)7.1 动态验证 (9)7.2 静态验证 (9)7.3 物理验证 (9)8 总结 (9)致谢 (10)参考文献 (10)超大规模集成电路网络工程专业学生孙守勇指导教师吴俊华摘要：随着集成电路的高速发展，集成电路的设计显得越来越重要，目前设计能力滞后于制造工艺已成为世界集成电路产业的发展现状之一。
为了明确超大规模集成电路设计的理想方法，首先对超大规模集成电路的设计要求进行了调查，然后对超大规模集成电路的设计策略进行了研究，探讨了超大规模集成电路的不同设计方法，并对不同的设计方法做出了比较，明确了超大规模集成电路的设计步骤及设计流程，最后探讨了超大规模集成电路的验证方法。
关键词：集成电路设计方法步骤Very Large Scale IntegrationStudent Majoring in Network Engineering Sun ShouyongTutor Wu JunhuaAbstract:With the high speed development of integrated circuit, the design of integrated circuit is becoming more and more important. At present, the design capacity behind manufacture technology has become one of the world's integrated circuit industry development current situation. In order to specify the ideal method of VLSI design, first of all, the requirements of VLSI was investigated, then, the design strategy of VLSI is studied. Discuss different methods of VLSI, and made a comparison of different methods. Clear and definite the design steps of very large scale integrated circuit and the design process, finally, discuss the validation method of very large scale integrated circuit.Key words：integrated circuit; design; method; step1引言自从1959年集成电路诞生以来，经历了小规模（SSI）、中规模（MSI）、大规模（LSI）的发展历程，目前已进入超大个规模(VLSI)和甚大规模集成电路(ULSI)阶段，集成电路技术的发展已日臻完善，集成电路芯片的应用也渗透到国民经济的各个部门和科学技术的各个领域之中，对当代经济发展和科技进步起到了不可估计的推动作用。
超大规模集成电路设计导论课程设计介绍超大规模集成电路（Very Large-Scale Integration，简称VLSI）是指将许多电子器件、电子元件和电路系统高度集成在一起，形成一个功能强大的芯片。
VLSI 技术是电子信息科学与技术的重要分支之一，应用范围广泛，从计算机芯片到计算机网络、通信系统、控制系统等领域都有广泛的应用。
本文将介绍超大规模集成电路设计导论课程设计的相关内容。
课程设计任务超大规模集成电路设计导论课程设计的任务是设计一个最小的超大规模集成电路芯片，实现指定的功能。
学生需完成以下任务：1.设计一个基于MOSFET电路的逻辑电路。
学生需要掌握MOS场效应管的基本工作原理，了解CMOS电路的基本操作和管路的结构。
2.进行电路级仿真。
学生需要使用常用的电路设计软件进行电路仿真，如HSpice、Cadence等。
3.进行物理级设计。
学生需要熟悉并掌握芯片物理设计的相关知识，包括版图设计、布线、电源分配等。
4.进行芯片测试。
学生需要设计并实现相应的测试电路，并进行芯片测试，以验证芯片的正确性和稳定性。
设计流程超大规模集成电路设计导论课程设计的设计流程可以分为以下几个步骤：步骤一：确定电路功能在超大规模集成电路设计导论课程设计中，首先需要确定电路的功能。
学生需要根据课程要求，确定芯片的功能模块，例如逻辑门、存储器等。
步骤二：电路设计在确定电路功能之后，学生需要进行电路设计。
主要的工作包括选择电路拓扑结构，确定器件大小和参数等。
步骤三：电路仿真完成电路设计后，学生需要进行电路仿真。
通过仿真可以预测电路的性能和工作过程，根据仿真结果进行电路调整和参数优化。
步骤四：物理级设计完成电路仿真之后，需要进行物理级设计。
主要的工作包括版图设计、布线和电源分配等。
学生需要熟练运用芯片设计软件，如Cadence等。
步骤五：芯片制造完成物理级设计后，学生需要将设计好的芯片提交到芯片制造厂家进行生产加工。
学生需要了解芯片制造的相关知识和技术，如光刻工艺、腐蚀工艺等。
