设计考试题目：用VHDL语言描述和实现乘法累加器设计

VHDL数学运算VHDL是一种硬件描述语言，可以用于实现数字电路和系统级集成电路设计。

在数字电路和系统级集成电路中，数学运算是一个非常重要的部分。

VHDL可以支持各种数学运算，包括加、减、乘和除等基本运算，以及三角函数、指数函数和对数函数等高级运算。

在VHDL中，基本的加、减、乘和除运算可以使用算术运算符实现。

例如，加法可以使用“+”运算符实现，如下所示：signal a, b, c : std_logic_vector(3 downto 0);c <= a + b;这个代码片段将a和b两个信号相加，并将结果存储在c信号中。

类似地，减法可以使用“-”运算符实现，乘法可以使用“*”运算符实现，除法可以使用“/”或“mod”运算符实现。

除此之外，VHDL还支持各种高级数学函数，例如三角函数、指数函数和对数函数等。

这些函数可以通过VHDL中提供的库函数来实现。

例如，可以使用“sin”函数来计算正弦值，如下所示：signal angle : real;signal sine : real;sine <= sin(angle);此外，VHDL还支持各种数学库函数，例如幂函数、平方根函数和绝对值函数等。

这些函数可以帮助设计人员轻松地实现各种复杂的数学运算和算法。

例如，可以使用“pow”函数来计算任意数的幂，如下所示：signal base : real;signal exponent : integer;signal result : real;result <= pow(base, exponent);总之，VHDL的数学运算功能非常强大，可以帮助设计人员轻松地实现各种数字电路和系统级集成电路的数学运算和算法。

设计人员应该熟练掌握VHDL的数学运算功能，以便能够高效地进行设计和开发工作。

控制模块：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity cont_modu isport(Clk : in std_logic ;Start : in std_logic; //数据输入开始信号en_sig : out std_logic; //控制运算信号，为‘1’运算数据out_sig : out std_logic // 运算完成信号);end entity;architecture rlt_cont_modu of cont_modu issignal cnt :integer range 0 to 15 :=0;//定义从0到15type state is(S_idle,S_work,S_1d,S_2d);//运算状态信号，状态机signal st_ty : state :=S_idle;beginprocess(Clk)beginif rising_edge(Clk) thencase st_ty is 选择语句；S_idle为空闲状态，当输入数据后Start信号为1就开始工作when S_idle => if Start ='1' then 如果为1就跳转到S_work状态，并且使能信号置1st_ty <= S_work;en_sig <='1';else 不然继续在S_idle状态st_ty <= S_idle;en_sig <='0';end if;out_sig <='0';when S_work => if cnt =15 then 在S_work状态下，cnt信号一直加1，加满16个数就跳转到S_1d，然后使能信号en_sig 就为0。

课程名称：EDA技术实验实验名称：移位相加8位硬件乘法器电路设计一、实验目的：1、学习移位相加8位硬件乘法器电路设计；2、进一步提高学生应用EDA技术进行项目设计的能力。

二、实验原理纯组合逻辑结构构成的乘法器虽然工作速度比较快，但过于占用硬件资源，难以实现宽位乘法器；基于PLD器件外接ROM九九表的乘法器则无法构成单片系统，也不实用。

本实验由8位加法器构成的以时序逻辑方式设计锝位乘法器，具有一定的实用价值。

其原理是：乘法通过逐位相加原理来实现，从被乘数的最低位开始，若为1，则乘数左移后与上一次的和相加；若为0，左移后以全0相加，直至被乘数的最高位。

三、实验内容1、打开Q 软件，新建VHDL程序输入文件，用VHDL语言设计乘法器的各个模块：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY SREG8B ISPORT ( CLK : IN STD_LOGIC;LOAD : IN STD_LOGIC;DIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);QB : OUT STD_LOGIC );END SREG8B;ARCHITECTURE behav OF SREG8B ISSIGNAL REG8 : STD_LOGIC_VECTOR(7 DOWNTO 0);BEGINPROCESS (CLK,LOAD)BEGINIF LOAD = '1' THEN REG8 <= DIN;ELSIF CLK'EVENT AND CLK = '1' THENREG8(6 DOWNTO 0) <= REG8(7 DOWNTO 1);END IF;END PROCESS;QB <= REG8(0);END behav;图1.1 8位右移寄存器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD-LOGIC_UNSIGNED.ALL;ENTITY ADDER8 ISPORT(B,A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);S : OUT STD_LOGIC_VECTOR(8 DOWNTO 0));END ADDER8;ARCHITECTURE behav OF ADDER8 ISBEGINS <= '0'&A+B;END behav;图1.2 8位加法器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY ANDARITH ISPORT ( ABIN : IN STD_LOGIC;DIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END ANDRITH;ARCHITECTURE behav OF ANDARITH ISBEGINPROCESS(ABIN,DIN)BEGINFOR I IN 0 TO 7 LOOPDOUT(I) <= DIN(I) AND ABIN;END LOOP;END PROCESS;END behav;图1.3 选通与门模块LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY REG16B ISPORT ( CLK,CLR : IN STD_LOGIC;D : IN STD_LOGIC_VECTOR(8 DOWNTO 0);Q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); END REG16B;ARCHITECTURE behav OF REG16B ISSIGNAL R16S :STD_LOGIC_VECTOR(15 DOWNTO 0); BEGINPROCESS(CLK,CLR)BEGINIF CLR = '1' THEN R16S <= (OTHERS =>'0');ELSIF CLK'EVENT AND CLK = '1' THENR16S(6 DOWNTO 0) <= R16S(7 DOWNTO 1);R16S(15 DOWNTO 7) <= D;END IF;END PROCESS;Q <= R16S;END behav;图1.4 16位锁存器2、对各个模块进行编译并打包成电路元件，如上图1所示。

利用VHDL設計乘法器Implement of Multiplier by Using VHDL許地申Dih-Shen Hsu中華技術學院電機系副教授Associate ProfessorDepartment of Electrical EngineeringChina Institute of Technology摘 要在計算機結構裡加，減，乘，除是常被用到的運算，本文提出以非常高速積體電路硬體描述語言(VHDL)來描述硬體，說明如何將兩個運算元作相乘的運算。

我們首先以無號數整數做乘法運算來說明其原理，設計其電路結構。

其實在VHDL 程式中，我們更可以載入STD_LOGIC_ARITH與STD_LOGIC_UNSIGNED元件盒之後，直接進行乘法運算，既簡單又容易擴充。

最後，我們將以4-bit X 4-bit 的例子來做電路描述、電路合成、電路模擬並以七段顯示器將其結果顯示出來。

關鍵字：非常高速積體電路硬體描述語言、電路描述、電路合成、電路模擬AbstractWe have known operation that perform addition, subtraction, multiplication, and division. In this paper we are presented primarily to describe hardware using by VHDL. We can explain how multiplication may be performed for two operand. Multiplication of unsigned numbers illustrates the main issues involved in the design of multiplier circuit. In fact, after the STD_LOGIC_ARITH and STD_LOGIC_UNSIGNED packages were added to the VHDL program, it became not only simple but also easy to extended. Next, consider a 4 x 4 example to circuit description, circuit synthesis, and circuit simulation by using VHDL. Finally, this approach can also be displayed by 7-segment.Keyword : VHDL , circuit description , circuit synthesis, circuit simulation壹.簡介VHDL是Very High Speed Integrated Circuit Hardware Description Language 的英文縮寫。

9*9乘法器的VHDL的设计1 设计任务制作一个9*9乘法器2 设计说明输入两个四位二进制信号a，b分别作为被乘数和乘数，以8421bcd码编号，输入一个一位信号oc作为控制信号；输出两个四位二进制信号c，d分别作为结果的十位和个位，以8421bcd码编号。

3 设计结果3.1 原理图图1 原理图3.2 信号表a：被乘数，用4位二进制8421bcd码表示；b：乘数，用4位二进制8421bcd码表示；oc：控制信号；c：结果的十位，用4位二进制8421bcd码表示；d：结果的个位，用4位二进制8421bcd码表示；图2 信号表3.3仿真结果图3 oc、a、b分别为0、2、8和0、4、3时结果图4 oc、a、b分别为1、2、8和1、4、3时结果图5 oc、a、b分别为0、10、8和0、4、11时结果3.4 电路图图6 原理图3.5 程序清单LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY mul9 ISPORT (oc: IN std_logic;a,b: IN std_logic_vector (3 downto 0);c,d: OUT std_logic_vector(3 downto 0));END;ARCHITECTURE one OF mul9 ISBEGINPROCESS(a,b)BEGINIF(oc = '1') THENIF(a = "0001") THENCASE b ISWHEN "0001" =>c <= "0000"; d <= "0001"; WHEN "0010" =>c <= "0000"; d <= "0010";WHEN "0011" =>c <= "0000"; d <= "0011"; WHEN "0100" =>c <= "0000"; d <= "0100";WHEN "0101" =>c <= "0000"; d <= "0101"; WHEN "0110" =>c <= "0000"; d <= "0110";WHEN "0111" =>c <= "0000"; d <= "0111"; WHEN "1000" =>c <= "0000"; d <= "1000";WHEN "1001" =>c <= "0000"; d <= "1001"; WHEN OTHERS =>c <= "0000"; d <= "0000";END CASE;CASE b ISWHEN "0001" =>c <= "0000"; d <= "0010"; WHEN "0010" =>c <= "0000"; d <= "0100";WHEN "0011" =>c <= "0000"; d <= "0101"; WHEN "0100" =>c <= "0000"; d <= "1000";WHEN "0101" =>c <= "0001"; d <= "0000"; WHEN "0110" =>c <= "0001"; d <= "0010";WHEN "0111" =>c <= "0001"; d <= "0100"; WHEN "1000" =>c <= "0001"; d <= "0110";WHEN "1001" =>c <= "0001"; d <= "1000"; WHEN OTHERS =>c <= "0000"; d <= "0000";END CASE;ELSIF(a = "0011") THENCASE b ISWHEN "0001" =>c <= "0000"; d <= "0101"; WHEN "0010" =>c <= "0000"; d <= "0110";WHEN "0011" =>c <= "0000"; d <= "1001"; WHEN "0100" =>c <= "0001"; d <= "0010";WHEN "0101" =>c <= "0001"; d <= "0101"; WHEN "0110" =>c <= "0001"; d <= "1000";WHEN "0111" =>c <= "0010"; d <= "0001"; WHEN "1000" =>c <= "0010"; d <= "0100";WHEN "1001" =>c <= "0010"; d <= "0111"; WHEN OTHERS =>c <= "0000"; d <= "0000";END CASE;CASE b ISWHEN "0001" =>c <= "0000"; d <= "0100"; WHEN "0010" =>c <= "0000"; d <= "1000";WHEN "0011" =>c <= "0001"; d <= "0010"; WHEN "0100" =>c <= "0001"; d <= "0110";WHEN "0101" =>c <= "0010"; d <= "0000"; WHEN "0110" =>c <= "0010"; d <= "0100";WHEN "0111" =>c <= "0010"; d <= "1000"; WHEN "1000" =>c <= "0011"; d <= "0010";WHEN "1001" =>c <= "0011"; d <= "0101"; WHEN OTHERS =>c <= "0000"; d <= "0000";END CASE;ELSIF(a = "0101") THENCASE b ISWHEN "0001" =>c <= "0000"; d <= "0101"; WHEN "0010" =>c <= "0001"; d <= "0000";WHEN "0011" =>c <= "0001"; d <= "0101"; WHEN "0100" =>c <= "0010"; d <= "0000";WHEN "0101" =>c <= "0010"; d <= "0101"; WHEN "0110" =>c <= "0011"; d <= "0000";WHEN "0111" =>c <= "0011"; d <= "0101"; WHEN "1000" =>c <= "0100"; d <= "0000";WHEN "1001" =>c <= "0100"; d <= "0101"; WHEN OTHERS =>c <= "0000"; d <= "0000";END CASE;CASE b ISWHEN "0001" =>c <= "0000"; d <= "0110"; WHEN "0010" =>c <= "0001"; d <= "0010";WHEN "0011" =>c <= "0001"; d <= "1000"; WHEN "0100" =>c <= "0010"; d <= "0100";WHEN "0101" =>c <= "0011"; d <= "0000"; WHEN "0110" =>c <= "0011"; d <= "0110";WHEN "0111" =>c <= "0100"; d <= "0010"; WHEN "1000" =>c <= "0100"; d <= "1000";WHEN "1001" =>c <= "0101"; d <= "0100"; WHEN OTHERS =>c <= "0000"; d <= "0000";END CASE;ELSIF(a = "0111") THENCASE b ISWHEN "0001" =>c <= "0000"; d <= "0111"; WHEN "0010" =>c <= "0001"; d <= "0100";WHEN "0011" =>c <= "0010"; d <= "0001"; WHEN "0100" =>c <= "0010"; d <= "1000";WHEN "0101" =>c <= "0011"; d <= "0101"; WHEN "0110" =>c <= "0100"; d <= "0010";WHEN "0111" =>c <= "0100"; d <= "1001"; WHEN "1000" =>c <= "0101"; d <= "0110";WHEN "1001" =>c <= "0110"; d <= "0011"; WHEN OTHERS =>c <= "0000"; d <= "0000";END CASE;CASE b ISWHEN "0001" =>c <= "0000"; d <= "1000"; WHEN "0010" =>c <= "0001"; d <= "0110";WHEN "0011" =>c <= "0010"; d <= "0110"; WHEN "0100" =>c <= "0011"; d <= "0010";WHEN "0101" =>c <= "0100"; d <= "0000"; WHEN "0110" =>c <= "0100"; d <= "1000";WHEN "0111" =>c <= "0101"; d <= "0110"; WHEN "1000" =>c <= "0110"; d <= "0100";WHEN "1001" =>c <= "0111"; d <= "0010"; WHEN OTHERS =>c <= "0000"; d <= "0000";END CASE;ELSIF(a = "1001") THENCASE b ISWHEN "0001" =>c <= "0000"; d <= "1001"; WHEN "0010" =>c <= "0001"; d <= "1000";WHEN "0011" =>c <= "0010"; d <= "0111"; WHEN "0100" =>c <= "0010"; d <= "0110";WHEN "0101" =>c <= "0100"; d <= "0101"; WHEN "0110" =>c <= "0101"; d <= "0100";WHEN "0111" =>c <= "0101"; d <= "0110"; WHEN "1000" =>c <= "0111"; d <= "0010";WHEN "1001" =>c <= "1000"; d <= "0001"; WHEN OTHERS =>c <= "0000"; d <= "0000";END CASE;ELSEc <= "0000";d <= "0000";END IF;ELSE c <= "0000"; d <= "0000";END IF;END PROCESS;END one;4 实验总结通过这次课程设计，我进一步加深了对电子设计自动化的了解。

VHDL 加法器设计设计要求：采用QuartusII 集成开发环境利用VHDL 硬件描述语言设计传播进位加法器，直接进位加法器，线形进位加法器，平方根进位加法器，并比较这四种加法器的性能。

为了便于比较性能，将四种加法器都设定为28位。

一、全加器设计全加器是上述四种加法器的基础部件，首先应当设计一位全加器。

设计原理：i i i iS ABC ABC ABC ABC A B C=+++=⊕⊕0i i C AB BC AC =++VHDL 程序：仿真结果：--一位全加器设计library ieee;use ieee.std_logic_1164.all; entity fulladd isport ( A: in std_logic;B: in std_logic; cin:in std_logic; sumbit:out std_logic; cout:out std_logic );end fulladd;architecture behav of fulladd is beginsumbit<=(A xor B) xor cin;cout<=(a and b) or (cin and a) or (cin and b); end behav;二、传播进位加法器设计实际上加法器就是是全加器的级联，其中的每个FA网络为一个全加器（采用上文所述的全加器）VHDL代码：--传播进位加法器library ieee;use ieee.std_logic_1164.all;use work.all;entity carry_propogate_adder isport (A: in std_logic_vector(27 downto 0);B: in std_logic_vector(27 downto 0);cin:in std_logic;sum:out std_logic_vector(27 downto 0);cout:out std_logic);end carry_propogate_adder;architecture behav of carry_propogate_adder issignal ct:std_logic_vector(28 downto 0);component fulladd isport (A: in std_logic;B: in std_logic;cin:in std_logic;sumbit:out std_logic;cout:out std_logic);end component;beginct(0)<=cin;cout<=ct(28);G1: for i in 0 to 27 generatel1:fulladd port map (A(i),B(i),ct(i),sum(i),ct(i+1));end generate G1;end behav;功能仿真:延时测定：由图中的两个时间bar 的差值可看出，sum 值和cout 值几乎同时计算出，其Tdelay=28.332ns （cin 无关）三、直接进位加法器设计 设计原理：首先将AB 输入转换为PG 输入，若每级的P 输入都是‘1’则直接将Ci 传给Co ，否则像传播进位加法器一样计算其AB-PG 转换网络原理：Fa 全加器原理：P A B G AB=⊕=o i iC G PC S P C =+=⊕VHDL 代码：-- FA 子单元 library ieee;use ieee.std_logic_1164.all;entity Fa isport (Pi,Gi,Ci:in std_logic; Coi,Si:out std_logic); end Fa;architecture Fabehav of Fa is beginCoi<=Gi or (Pi and Ci);Si<=Pi xor Ci; end Fabehav; --ABtoPG 转换网络 library ieee;use ieee.std_logic_1164.all;entity PGNet isport(Ai,Bi:in std_logic; Pi,Gi:out std_logic); end PGNet;architecture PGbehav of PGNet is beginPi<=Ai xor Bi;Gi<=Ai and Bi; end PGbehav; --传播进位加法器 library ieee;use ieee.std_logic_1164.all; entity bypass_adder is port(A,B:in std_logic_vector(27 downto 0); Ci:in std_logic; Sum:out std_logic_vector(27 downto 0); Co:out std_logic );end bypass_adder;architecture adderbehav of bypass_adder is component Fa is port (Pi,Gi,Ci:in std_logic; Coi,Si:out std_logic ); end component; component PGNet is port(Ai,Bi:in std_logic; Pi,Gi:out std_logic ); end component;signal P,G:std_logic_vector(27 downto 0); signal C:std_logic_vector(28 downto 0); signal BP:std_logic; begin C(0)<=Ci; G1: for i in 0 to 27 generate l1: PGNet port map(A(i),B(i),P(i),G(i)); end generate G1; G2: for i in 0 to 27 generate l2:Fa port map (P(i),G(i),C(i),C(i+1),Sum(i)); end generate G2; BP<='1' when P="11111111111111111111111111111111" else '0'; Co<=Ci when BP='1' else C(8); end adderbehav;功能仿真：延时仿真：当通过直接进位网络（图中testp值全部为1时），进位信号有一定提前，但由于计算所有的P值本身也需要一定时间，所以改善并不明显。

实验二四位流水线乘法器一、实验目的1．了解四位并行乘法器的原理。

2．了解四位并行乘法器的设计思想和流水线的实现方法。

3．掌握用VHDL 语言实现基本二进制运算的方法。

二、实验内容与要求通过开关和键盘输入两组4BIT的二进制数据，按照二进制加法器原理进行加和，求出和及进位，并通过LED显示灯输出显示，完成编译、综合、适配、仿真、实验箱上的硬件测试。

三、实验原理流水线结构的并行乘法器的最大有点就是速度快，尤其实在连续输入的乘法器中，可以达到近乎单周期的运算速度。

流水线乘法器是组合逻辑电路实现无符号数乘法的方法上发展而来的。

其关键是在组合逻辑电路的基础上插入寄存器。

假如有被乘数A 和乘数B，首先用A 与B 的最低位相乘得到S1，然后再把A 左移1 位与B 的第2 位相乘得到S2，再将A 左移3 位与B 的第三位相乘得到S3，依此类推，直到把B 的所有位都乘完为止，然后再把乘得的结果S1、S2、S3……相加即得到相乘的结果。

需要注意的是，具体实现乘法器是，并不是真正的去乘，而是利用简单的判断去实现，举个简单的例子。

假如A 左移n 位后与B 的第n 位相乘，如果B 的这位为‘1’，那么相乘的中间结果就是A 左移n 位后的结果，否则如果B 的这位为‘0’，那么就直接让相乘的中间结果为0 即可。

带B 的所有位相乘结束后，把所有的中间结果相加即得到A 与B 相乘的结果。

在此基础上插入寄存器即可实现流水线乘法器。

四、实验平台（1）硬件：计算机、GX-SOC/SOPC-DEV-LABCycloneII EP2C35F672C8核心板（2）软件：Quartus II软件PIN_AF8 DATAOUT[4] LED4PIN_AE7 DATAOUT[5] LED5PIN_AF7 DATAOUT[6] LED6PIN_AA11 DATAOUT[7] LED7PIN_AE21 BCD[0] 数码管DP4BPIN_AB20 BCD[1]PIN_AC20 BCD[2]PIN_AF20 BCD[3]PIN_AE20 BCD[4] 数码管DP5BPIN_AD19 BCD[5]PIN_AC19 BCD[6]PIN_AA17 BCD[7]PIN_AA18 BCD[8] 数码管DP6BPIN_W17 BCD[9]PIN_V17 BCD[10]PIN_AB18 BCD[11]六、仿真截图七、硬件实现八、程序代码1---clkgen.vhdlibrary IEEE;-- 1HZuse IEEE.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity clkgen isport (CLK : in std_logic;CLK1HZ: out std_logic);end entity;architecture clk_arch of clkgen issignal COUNT : integer range 0 to 50000000; --50MHZ -->1hz begin -- 50M/1=50000000 PROCESS(CLK)BEGINif clk'event and clk='1' thenIF COUNT= 50000000 thenCOUNT<=0;ELSE COUNT<=COUNT+1;END IF;END IF;END PROCESS;PROCESS(COUNT)BEGINIF COUNT= 5000000 THEN -- 1HZCLK1HZ<='1';ELSE CLK1HZ<='0';END IF;END PROCESS;end architecture;2—BCD-- 输出控制模块，把乘法器的输出转换成BCD码在数码管上显示、-- SCKZ.VHDlibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity BIN2BCD isport ( DIN: in std_logic_vector(7 downto 0); ---The input 8bit binaryBCDOUT: out std_logic_vector(11 downto 0)--输出显示, 已转换成BCD码);end entity;architecture arch of BIN2BCD issignal data2,data3,data4 :std_logic_vector(9 downto 0);-- 输出数据缓存signal hundred,ten,unit:std_logic_vector(3 downto 0);--signal bcdbuffer:std_logic_vector(11 downto 0);---2'1111_1001_11=999beginBCDOUT<= bcdbuffer;bcdbuffer(11 downto 8)<=hundred;bcdbuffer(7 downto 4)<=ten;bcdbuffer(3 downto 0)<=unit;get_hundred_value:process(data2)beginDA TA2<="00"&DIN;---get hundred valueif data2>=900 thenhundred<="1001";--9data3<=data2-900;elsif data2>=800 thenhundred<="1000";--8data3<=data2-500;elsif data2>=700 thenhundred<="0111";--7data3<=data2-700;elsif data2>=600 thenhundred<="0110";--6data3<=data2-600;elsif data2>=500 thenhundred<="0101";--5data3<=data2-500;elsif data2>=400 thenhundred<="0100";--4data3<=data2-400;elsif data2>=300 thenhundred<="0011";--3data3<=data2-300;elsif data2>=200 thenhundred<="0010";--2data3<=data2-200;elsif data2>=100 thenhundred<="0001";--1data3<=data2-100;else data3<=data2;hundred<="0000";end if;end process; ---get_thousand_valueget_tens_value:process(data3) begin---get tens placeif data3>=90 thenten<="1001";--9data4<=data3-90;elsif data3>=80 thenten<="1000";--8data4<=data3-50;elsif data3>=70 thenten<="0111";--7data4<=data3-70;elsif data3>=60 thenten<="0110";--6data4<=data3-60;elsif data3>=50 thenten<="0101";--5data4<=data3-50;elsif data3>=40 thenten<="0100";--4data4<=data3-40;elsif data3>=30 thenten<="0011";--3data4<=data3-30;elsif data3>=20 thenten<="0010";--2data4<=data3-20;elsif data3>=10 thenten<="0001";--1data4<=data3-10;else data4<=data3;ten<="0000";end if;end process; ---get_ten_valueget_unit_value:process(data4)begin--unit's orderif (data4>0) thenunit<=data4(3 downto 0);else unit<="0000";end if;end process;end arch;3 multi4b --------------------------------------------------------------------------------/ -- DESCRIPTION : Signed mulitplier:-- AIN (A) input width : 4-- BIN (B) input width : 4-- Q (data_out) output width : 8-- 并行流水乘法器--------------------------------------------------------------------------------/--10 × 9 = 90-- 1 0 1 0-- 1 0 0 1 =-- --------------- 1 0 1 0-- 0 0 0 0 --partial products-- 0 0 0 0-- 1 0 1 0-- -------------------- 1 0 1 1 0 1 0--parallel : process all the inputs at the same time--pipeline : use several stages with registers to implement it----关键思想，插入寄存器library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity multi4b isport ( CLK: in STD_LOGIC; ---system clockAIN: in STD_LOGIC_VECTOR (3 downto 0); ---one inputBIN: in STD_LOGIC_VECTOR (3 downto 0);-- the other inputdata_out: out STD_LOGIC_VECTOR (7 downto 0)---the result ---make sure the biggest value ,i,e. 1111x1111=1110_0001 can be held in the register );end multi4b;architecture multi_arch of multi4b issignal A,B :std_logic_vector(3 downto 0); --input register---registers to hold the result of the first processing---registers added to make use of pipeline, the 1st stagesignal A_MULT_B0: STD_LOGIC_VECTOR (3 downto 0);signal A_MULT_B1: STD_LOGIC_VECTOR (3 downto 0);signal A_MULT_B2: STD_LOGIC_VECTOR (3 downto 0);signal A_MULT_B3: STD_LOGIC_VECTOR (3 downto 0);---register to hold the result of the multipliersignal C_TEMP : STD_LOGIC_VECTOR (7 downto 0);beginPROCESS(CLK,AIN,BIN)beginif CLK'EVENT AND CLK='1' THEN-- multiplier operand inputs are registeredA<= AIN;B<= BIN;-----------------Fist stage of the multiplier------------------here we get the axb(0),axb(1),axb(2)，axb(3),i.e.partial products---put them into the responding registersA_MULT_B0(0) <= A (0) and B (0);----- multi 1 , get the a(0) and b(0), & put it into the register A_MULT_B0(0)A_MULT_B0(1) <= A (1) and B (0);A_MULT_B0(2) <= A (2) and B (0);A_MULT_B0(3) <= A (3) and B (0);--10 × 9 = 90-- 1 0 1 0-- 1 0 0 1 =-- --------------- 0 0 0 0 1 0 1 0-- 0 0 0 0 0 0 0 0 --partial products-- 0 0 0 0-- 1 0 1 0-- -------------------- 1 0 1 1 0 1 0A_MULT_B1(0) <= A (0) and B (1);A_MULT_B1(1) <= A (1) and B (1);A_MULT_B1(2) <= A (2) and B (1);A_MULT_B1(3) <= A (3) and B (1);A_MULT_B2(0) <= A (0) and B (2);A_MULT_B2(1) <= A (1) and B (2);A_MULT_B2(2) <= A (2) and B (2);A_MULT_B2(3) <= A (3) and B (2);A_MULT_B3(0) <= A (0) and B (3);A_MULT_B3(1) <= A (1) and B (3);A_MULT_B3(2) <= A (2) and B (3);A_MULT_B3(3) <= A (3) and B (3);end if;end process;--------------------Second stage of the multiplier---------------add the all the partial products ,then get the result of the multiplier C_TEMP<=( "0000" & A_MULT_B0 )+( "000"& A_MULT_B1 &'0' )+( "00" & A_MULT_B2 & "00" )+( '0'&A_MULT_B3 & "000" );--build a signal register output---输出寄存，利于实现流水data_out <= C_TEMP; --output registerend multi_arch;九、实验总结。