A single chip high data rate QPSK demodulator

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Table of Contents Revision History....................................................................................................... 1 1. Introduction........................................................................................................................... 1
3.1 General Specifications................................................................................................... 2 3.2 DC Power Consumption................................................................................................ 3 3.3 RF Specifications............................................................................................................4
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V1.0 2017-4-15 BL-M8821CU1 IEEE 802.11b/g/n/ac(1T1R) USB WLANAnd BT Module Bilian Approve Field

CS42438中文资料

Preliminary Product InformationThis document contains information for a new product.Cirrus Logic reserves the right to modify this product without notice.Copyright © Cirrus Logic, Inc. 2005Cirrus Logic, Inc.z Six 24-bit A/D, Eight 24-bit D/A Converters zADC Dynamic Range–105 dB Differential –102 dB Single-ended zDAC Dynamic Range –108 dB Differential–105 dB Single-ended zADC/DAC THD+N –-98 dB Differential–-95 dB Single-endedz Compatible with Industry-standard TimeDivision Multiplexed (TDM) Serial Interface z DAC Sampling Rates up to 192 kHzz ADC Sampling Rates up to 96 kHzz Programmable ADC High-pass Filter for DC Offset Calibration z Logarithmic Digital Volume Controlz Hardware Mode or Software I²C & SPI ™zSupports Logic Levels Between 5V and1.8VThe CS42438 CODEC provides six multi-bit analog-to-digi-tal and eight multi-bit digital-to-analog Delta-sigma converters. The CODEC is capable of operation with eitherdifferential or single-ended inputs and outputs, in a 52-pin M QFP package.Six fully differential, or single-ended, inputs are available onstereo ADC1, ADC2, and ADC3. When operating in Single-ended Mode, an internal MUX before ADC3 allows selec-tion from up to four single-ended inputs. Digital volume control is provided for each ADC channel, with selectableoverflow detection.All eight DAC channels provide digital volume control and can operate with differential or single-ended outputs.An auxiliary serial input is available for an additional twochannels of PCM data. The CS42438 is ideal for audio systems requiring wide dy-namic range, negligible distortion and low noise, such asA/V receivers, DVD receivers, and automotive audiosystems.ORDERING INFORMATIONSee page 62.CS42438FEB ‘05108 dB, 192 kHz 6-in, 8-out TDM CODECTABLE OF CONTENTS1 PIN DESCRIPTION - SOFTWARE MODE (6)1.1 Digital I/O Pin Characteristics (7)2 PIN DESCRIPTIONS - HARDWARE MODE (8)3 TYPICAL CONNECTION DIAGRAMS (10)4 CHARACTERISTICS AND SPECIFICATIONS (12)SPECIFIED OPERATING CONDITIONS (12)ABSOLUTE MAXIMUM RATINGS (12)ANALOG INPUT CHARACTERISTICS (CS42438-CMZ) (13)ANALOG INPUT CHARACTERISTICS (CS42438-DMZ) (14)ADC DIGITAL FILTER CHARACTERISTICS (15)ANALOG OUTPUT CHARACTERISTICS (CS42438-CMZ) (16)ANALOG OUTPUT CHARACTERISTICS (CS42438-DMZ) (18)COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (20)SWITCHING SPECIFICATIONS - ADC/DAC PORT (21)SWITCHING CHARACTERISTICS - AUX PORT (22)SWITCHING SPECIFICATIONS - CONTROL PORT - I²C MODE (23)SWITCHING SPECIFICATIONS - CONTROL PORT - SPI FORMAT (24)DC ELECTRICAL CHARACTERISTICS (25)DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS (25)5 APPLICATIONS (26)5.1 Overview (26)5.2 Analog Inputs (27)5.2.1 Line Level Inputs (27)5.2.2 ADC3 Analog Input (28)5.2.3 High Pass Filter and DC Offset Calibration (29)5.3 Analog Outputs (30)5.3.1 Initialization (30)5.3.2 Line-level Outputs and Filtering (30)5.3.3 Digital Volume Control (32)5.3.4 De-Emphasis Filter (32)5.4 System Clocking (33)5.5 CODEC Digital Interface (33)5.5.1 TDM (33)5.5.2 I/O Channel Allocation (34)5.6 AUX Port Digital Interface Formats (35)5.6.1 I²S (35)5.6.2 Left Justified (35)5.7 Control Port Description and Timing (36)5.7.1 SPI Mode (36)5.7.2 I2C Mode (37)5.8 Recommended Power-up Sequence (38)5.8.1 Hardware Mode (38)5.8.2 Software Mode (38)5.9 Reset and Power-up (38)5.10 Power Supply, Grounding, and PCB layout (39)6 REGISTER QUICK REFERENCE (40)7 REGISTER DESCRIPTION (42)7.1 Memory Address Pointer (MAP) (42)7.2 Chip I.D. and Revision Register (address 01h) (Read Only) (42)7.3 Power Control (address 02h) (43)7.4 Functional Mode (address 03h) (44)7.5 Miscellaneous Control (address 04h) (44)7.6 ADC Control & DAC De-emphasis (address 05h) (45)7.7 Transition Control (address 06h) (46)7.8 DAC Channel Mute (address 07h) (48)7.9 AOUTX Volume Control (addresses 08h- 0Fh) (48)7.10 DAC Channel Invert (address 10h) (49)7.11 AINX Volume Control (address 11h-16h) (49)7.12 ADC Channel Invert (address 17h) (49)7.13 Status (address 19h) (Read Only) (50)7.14 Status Mask (address 1Ah) (50)8 APPENDIX A: EXTERNAL FILTERS (51)8.1 ADC Input Filter (51)8.1.1 Passive Input Filter (52)8.1.2 Passive Input Filter w/Attenuation (52)8.2 DAC Output Filter (54)9 APPENDIX B: ADC FILTER PLOTS (55)10 APPENDIX C: DAC FILTER PLOTS (57)11 PARAMETER DEFINITIONS (59)12 REFERENCES (60)13 PACKAGE INFORMATION (61)13.1 Thermal Characteristics (61)14 ORDERING INFORMATION (62)15 REVISION HISTORY (63)LIST OF FIGURESFigure 1. Typical Connection Diagram (Software Mode) (10)Figure 2. Typical Connection Diagram (Hardware Mode) (11)Figure 3. Output Test Load (19)Figure 4. Maximum Loading (19)Figure 5. TDM Serial Audio Interface Timing (21)Figure 6. Serial Audio Interface Slave Mode Timing (22)Figure 7. Control Port Timing - I²C Format (23)Figure 8. Control Port Timing - SPI Format (24)Figure 9. Full-Scale Input (28)Figure 10. ADC3 Input Topology (28)Figure 11. Audio Output Initialization Flow Chart (31)Figure 12. Full-Scale Output (32)Figure 13. De-Emphasis Curve (33)Figure 14. TDM Serial Audio Format (34)Figure 15. AUX I²S Format (35)Figure 16. AUX Left Justified Format (35)Figure 17. Control Port Timing in SPI Mode (36)Figure 18. Control Port Timing, I²C Write (37)Figure 19. Control Port Timing, I²C Read (37)Figure 20. Single to Differential Active Input Filter (51)Figure 21. Single-Ended Active Input Filter (51)Figure 22. Passive Input Filter (52)Figure 23. Passive Input Filter w/Attenuation (53)Figure 24. Active Analog Output Filter (54)Figure 25. Passive Analog Output Filter (54)Figure 26. SSM Stopband Rejection (55)Figure 27. SSM Transition Band (55)Figure 28. SSM Transition Band (Detail) (55)Figure 29. SSM Passband Ripple (55)Figure 30. DSM Stopband Rejection (55)Figure 31. DSM Transition Band (55)Figure 32. DSM Transition Band (Detail) (56)Figure 33. DSM Passband Ripple (56)Figure 34. SSM Stopband Rejection (57)Figure 35. SSM Transition Band (57)Figure 36. SSM Transition Band (detail) (57)Figure 37. SSM Passband Ripple (57)Figure 38. DSM Stopband Rejection (57)Figure 39. DSM Transition Band (57)Figure 40. DSM Transition Band (detail) (58)Figure 41. DSM Passband Ripple (58)Figure 42. QSM Stopband Rejection (58)Figure 43. QSM Transition Band (58)Figure 44. QSM Transition Band (detail) (58)Figure 45. QSM Passband Ripple (58)LIST OF TABLESTable 1. I/O Power Rails (7)Table 2. Hardware Configurable Settings (26)Table 3. AIN5 Analog Input Selection (29)Table 4. AIN6 Analog Input Selection (29)Table 5. MCLK Frequency Settings (33)Table 6. Serial Audio Interface Channel Allocations (34)Table 7. MCLK Frequency Settings (44)Table 8. Example AOUT Volume Settings (48)Table 9. Example AIN Volume Settings (49)Table 10. Revision History (63)1PIN DESCRIPTION - SOFTWARE MODEPin Name#Pin DescriptionSCL/CCLK1Serial Control Port Clock (Input) - Serial clock for the control port interface.SDA/CDOUT2Serial Control Data I/O (Input/Output) - Input/Output for I2C data. Output for SPI data.AD0/CS3Address Bit [0]/ Chip Select (Input) - Chip address bit in I2C Mode. Control signal used to select the chip in SPI mode.AD1/CDIN4Address Bit [1]/ SPI Data Input (Input) - Chip address bit in I2C Mode. Input for SPI data.RST5Reset (Input) - The device enters a low power mode and all internal registers are reset to theirdefault settings when low.VLC6Control Port Power (Input) - Determines the required signal level for the control port interface.See “Digital I/O Pin Characteristics” on page7.FS7Frame Sync (Input) - Signals the start of a new TDM frame in the TDM digital interface format. VD8Digital Power (Input) - Positive power supply for the digital section.DGND9,18Digital Ground (Input) -VLS10Serial Port Interface Power (Input) - Determines the required signal level for the serial port inter-faces. See “Digital I/O Pin Characteristics” on page7.SCLK11Serial Clock(Input) - Serial clock for the serial audio interface. Input frequency must be 256xFs. MCLK12Master Clock (Input) - Clock source for the delta-sigma modulators and digital filters.ADC_SDOUT13Serial Audio Data Output (Output) - TDM output for two’s complement serial audio data.DAC_SDIN14DAC Serial Audio Data Input (Input) - TDM Input for two’s complement serial audio data.AUX_LRCK15Auxiliary Left/Right Clock (Output) - Determines which channel, Left or Right, is currently activeon the Auxiliary serial audio data line.1.1Digital I/O Pin CharacteristicsVarious pins on the CS42438 are powered from separate power supply rails. The logic level for each input should adhere to the corresponding power rail and should not exceed the maximum ratings.AUX_SCLK 16Auxiliary Serial Clock (Output) - Serial clock for the Auxiliary serial audio interface.AUX_SDIN 17Auxiliary Serial Input (Input ) - The CS42438 provides an additional serial input for two’s comple-ment serial audio data.AOUT1 +,-AOUT2 +,-AOUT3 +,-AOUT4 +,-AOUT5 +,-AOUT6 +,-20,1921,2224,23 25,2628,2729,30Differential Analog Output (Output ) - The full-scale differential analog output level is specified in the Analog Characteristics specification table. Each positive leg of the differential outputs may also be used single-ended.AGND 35,48Analog Ground (Input ) - VQ 36Quiescent Voltage (Output ) - Filter connection for internal quiescent reference voltage.VA 37,46Analog Power (Input ) - Positive power supply for the analog section.AIN1 +,-AIN2 +,-AIN3 +,-AIN4 +,-AIN5 +,-AIN6 +,-39,3841,4043,4245,4450,4952,51Differential Analog Input (Input ) - Signals are presented differentially to the delta-sigma modula-tors. The full-scale input level is specified in the Analog Characteristics specification table. Single-ended inputs may be applied to the positive terminals when the ADCx SINGLE bit is enabled. Once in Single-Ended Mode, the negative terminal of AIN1-AIN4 must be externally driven to com-mon mode. See below for a description of AIN5-AIN6 in Single-Ended Mode.AIN5 A,B AIN6 A,B50,4952,51Single-Ended Analog Input (Input ) - In Single-Ended Mode, an internal analog mux allows selec-tion between 2 channels for both analog inputs AIN5 and AIN6 (see section 7.6.6-7.6.8 for details).The unused leg of each input is internally connected to common mode. The full-scale input level is specified in the Analog Characteristics specification table.FILT+47Positive Voltage Reference (Output ) - Positive reference voltage for the internal sampling cir-cuits.Power RailPin Name SW/(HW)I/ODriver ReceiverVLCRST Input - 1.8 V - 5.0 V, CMOSSCL/CCLK (AIN5_MUX)Input - 1.8 V - 5.0 V, CMOS, with Hysteresis SDA/CDOUT (AIN6_MUX)Input/Output 1.8 V - 5.0 V, CMOS/Open Drain1.8 V - 5.0 V, CMOS, with HysteresisAD0/CS (MFREQ)Input - 1.8 V - 5.0 V, CMOS AD1/CDIN (ADC3_HPF)Input- 1.8 V - 5.0 V, CMOS VLSMCLK Input - 1.8 V - 5.0 V, CMOS LRCK Input - 1.8 V - 5.0 V, CMOS SCLK Input - 1.8 V - 5.0 V, CMOSADC_SDOUT (ADC3_SINGLE)Input/Output 1.8 V - 5.0 V, CMOS -DAC_SDIN Input - 1.8 V - 5.0 V, CMOSAUX_LRCK Output 1.8 V - 5.0 V, CMOS -AUX_SCLK Output 1.8 V - 5.0 V, CMOS-AUX_SDINInput- 1.8 V - 5.0 V, CMOSTable 1. I/O Power Rails2Pin Name#Pin DescriptionAIN5_MUX AIN6_MUX 12Analog Input Multiplexer (Input) - Allows selection between the A and B single-ended inputs of ADC3. See sections 7.6.7 and 7.6.8 for details.MFREQ3MCLK Frequency (Input) - Sets the required frequency range of the input Master Clock. See sec-tion 5.4 for the appropriate settings.ADC3_HPF4ADC3 High-Pass Filter Freeze (Input) - When this pin is driven high, the internal high-pass filter will be disabled for ADC3.The current DC offset value will be frozen and continue to be subtractedfrom the conversion result. See “ADC Digital Filter Characteristics” on page15.RST5Reset (Input) - The device enters a low power mode and all internal registers are reset to theirdefault settings when low.VLC6Control Port Power (Input) - Determines the required signal level for the control port interface.See “Digital I/O Pin Characteristics” on page7.FS7Frame Sync (Input) - Signals the start of a new TDM frame in the TDM digital interface format. VD8Digital Power (Input) - Positive power supply for the digital section.VLS10Serial Port Interface Power (Input) - Determines the required signal level for the serial port inter-faces.SCLK11Serial Clock(Input) - Serial clock for the serial audio interface. Input frequency must be 256xFs.ADC_SDOUT/ ADC3_SINGLE 13Serial Audio Data Output (Output) - TDM output for two’s complement serial audio data. Start-up Option for Hardware Mode: Pull-up to VLS enables Single-Ended Mode for AIN5-AIN6.DAC_SDIN14DAC Serial Audio Data Input (Input) - Input for two’s complement serial audio data.AUX_LRCK15Auxiliary Left/Right Clock (Output) - Determines which channel, Left or Right, is currently active on the Auxiliary serial audio data line.AUX_SCLK16Auxiliary Serial Clock(Output) - Serial clock for the Auxiliary serial audio interface.AUX_SDIN17Auxiliary Serial Input (Input) - The CS42438 provides an additional serial input for two’s comple-ment serial audio data.AOUT1 +,-AOUT2 +,-AOUT3 +,-AOUT4 +,-AOUT5 +,-AOUT6 +,-20,1921,2224,2325,2628,2729,30Differential Analog Output (Output) - The full-scale differential analog output level is specified in the Analog Characteristics specification table. Each positive leg of the differential outputs may also be used single-ended.AGND35,48Analog Ground (Input) -VQ36Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage. VA37,46Analog Power (Input) - Positive power supply for the analog section.AIN1 +,-AIN2 +,-AIN3 +,-AIN4 +,-AIN5 +,-AIN6 +,-39,3841,4043,4245,4450,4952,51Differential Analog Input (Input) - Signals are presented differentially to the delta-sigma modula-tors. The full-scale input level is specified in the Analog Characteristics specification table. Single-ended inputs may be applied to the positive terminals when the ADCx SINGLE pin is enabled.Once in Single-Ended Mode, the negative terminal of AIN1-AIN4 must be externally driven to com-mon mode. See below for a description of AIN5-AIN6 in Single-Ended Mode.AIN5 A,B AIN6 A,B 50,4952,51Single-Ended Analog Input (Input) - In Single-Ended Mode, an internal analog mux allows selec-tion between 2 channels for both analog inputs AIN5 and AIN6 (see section 7.6.6-7.6.8 for details).The unused leg of each input is internally connected to common mode. The full-scale input level is specified in the Analog Characteristics specification table.FILT+47Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling cir-cuits.3TYPICAL CONNECTION DIAGRAMSFigure 1. Typical Connection Diagram (Software Mode)Figure 2. Typical Connection Diagram (Hardware Mode)4CHARACTERISTICS AND SPECIFICATIONS(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical per-formance characteristics and specifications are derived from measurements taken at nominal supply voltages and T A = 25° C.)SPECIFIED OPERATING CONDITIONS(AGND=DGND=0 V, all voltages with respect to ground.)ABSOLUTE MAXIMUM RATINGS(AGND = DGND = 0 V; all voltages with respect to ground.)WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation isnot guaranteed at these extremes.Notes: 1.Analog input/output performance will slightly degrade at VA = 3.3 V.2.The ADC_SDOUT may not meet timing requirements in Double-Speed Mode.3.Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCRlatch-up.4.The maximum over/under voltage is limited by the input current.ParametersSymbol Min TypMaxUnitsDC Power Supply Analog 3.3 V (Note 1) 5.0 V VA 3.144.75 3.35 3.475.25V V Digital 3.3 V VD 3.14 3.3 3.47VSerial Audio Interface 1.8 V (Note 2)2.5 V 3.3 V 5.0 V VLS 1.712.373.144.751.82.53.35 1.892.633.475.25V V V V Control Port Interface 1.8 V2.5 V3.3 V5.0 VVLC 1.712.373.144.75 1.82.53.35 1.892.633.475.25V V V V Ambient TemperatureCommercial -CMZ Automotive -DMZ T A -10-40--+70+85°C °CParametersSymbol Min Max Units DC Power SupplyAnalogDigitalSerial Port Interface Control Port InterfaceVA VD VLS VLC -0.3-0.3-0.3-0.3 6.06.06.06.0V V V V Input Current(Note 3)I in -±10mA Analog Input Voltage (Note 4)V IN AGND-0.7VA+0.7V Digital Input VoltageSerial Port Interface (Note 4)Control Port InterfaceV IND-S V IND-C -0.3-0.3VLS+ 0.4VLC+ 0.4V V Ambient Operating Temperature CS42438-CMZ (power applied)CS42438-DMZT A -20-50+85+95°C °C Storage TemperatureT stg-65+150°CANALOG INPUT CHARACTERISTICS (CS42438-CMZ)(Test Conditions (unless otherwise specified): VLS = VLC = VD = 3.3 V, VA = 5V; Full scale input sine wave: 1 kHz through the active input filter on page51; Measurement Bandwidth is 10Hz to 20kHz unless otherwise specified.)Differential Single-EndedParameter Min Typ Max Min Typ Max Unit Single Speed Mode Fs=48 kHzDynamic Range A-weightedunweighted 9996105102--969310299--dBdBTotal Harmonic Distortion + Noise -1dB (Note 5) -20dB-60dB ----98-82-42-92------95-79-39-89--dBdBdBDouble Speed Mode Fs=96 kHzDynamic Range A-weightedunweighted40 kHz bandwidth unweighted 9996-10510299---96931029996---dBdBdBTotal Harmonic Distortion + Noise -1dB (Note 5) -20dB-60dB40 kHz bandwidth -1 dB -----98-82-42-90-92--------95-79-39-90-89---dBdBdBdBAll Speed ModesADC1-3 Interchannel Isolation-90--90-dB ADC3 MUX Interchannel Isolation-90--90-dB DC AccuracyInterchannel Gain Mismatch-0.1--0.1-dB Gain Drift-±100--±100-ppm/°C Analog InputFull-scale Input Voltage 1.06*VA 1.12*VA 1.18*VA0.53*VA0.56*VA0.59*VA Vpp Differential Input Impedance (Note 6)18-----kΩSingle-Ended Input Impedance (Note 7)---18--kΩCommon Mode Rejection Ratio (CMRR)-82----dBANALOG INPUT CHARACTERISTICS (CS42438-DMZ)(Test Conditions (unless otherwise specified):VLS = VLC = VD = 3.3 V, VA = 5V; Full scale input sine wave: 1 kHz through the active input filter on page51; Measurement Bandwidth is 10Hz to 20kHz unless otherwise specified.)Notes: 5.Referred to the typical full-scale voltage.6.Measured between AINx+ and AINx-.7.Measured between AINxx and AGND.Differential Single-EndedParameter Min Typ Max Min Typ Max Unit Single Speed Mode Fs=48 kHzDynamic Range A-weightedunweighted 9794105102--949110299--dBdBTotal Harmonic Distortion + Noise -1dB (Note 5) -20dB-60dB ----98-82-42-90------95-79-39-87--dBdBdBDouble Speed Mode Fs=96 kHzDynamic Range A-weightedunweighted40 kHz bandwidth unweighted 9794-10510299---9491-1029996---dBdBdBTotal Harmonic Distortion + Noise -1dB (Note 5) -20dB-60dB40 kHz bandwidth -1 dB -----98-82-42-87-90--------95-79-39-87-87---dBdBdBdBAll Speed ModesADC1-3 Interchannel Isolation-90--90-dB ADC3 MUX Interchannel Isolation-85--85-dB DC AccuracyInterchannel Gain Mismatch-0.1--0.1-dB Gain Drift-±100--±100-ppm/°C Analog InputFull-scale Input Voltage 1.04*VA 1.12*VA 1.20*VA0.52*VA0.56*VA0.60*VA Vpp Differential Input Impedance (Note 6)18-----kΩSingle-Ended Input Impedance (Note 7)---18--kΩCommon Mode Rejection Ratio (CMRR)-82----dBADC DIGITAL FILTER CHARACTERISTICSNotes:8.Filter response is guaranteed by design.9.Response is clock dependent and will scale with Fs. Note that the response plots (Figures 26to 33) havebeen normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.Parameter (Note 8, 9)MinTypMaxUnitSingle Speed Mode (Note 9)Passband (Frequency Response) to -0.1 dB corner0-0.4896Fs Passband Ripple --0.08dB Stopband0.5688--Fs Stopband Attenuation 70--dB Total Group Delay-12/Fs-sDouble Speed Mode (Note 9)Passband (Frequency Response) to -0.1 dB corner0-0.4896Fs Passband Ripple --0.16dB Stopband0.5604--Fs Stopband Attenuation 69--dB Total Group Delay-9/Fs-sHigh Pass Filter Characteristics Frequency Response -3.0 dB -0.13 dB -120--Hz Hz Phase Deviation @ 20Hz-10-Deg Passband Ripple --0dB Filter Settling Time-105/FssANALOG OUTPUT CHARACTERISTICS (CS42438-CMZ)(Test Conditions (unless otherwise specified):VLS = VLC = VD = 3.3 V, VA = 5V; Measurement Bandwidth is10Hz to 20kHz unless otherwise specified; Full scale 997 Hz output sine wave (see Note 11); Single-ended test load: R L = 3kΩ, C L = 10 pF.)ParameterDifferentialMin Typ MaxSingle-EndedMin Typ Max UnitSingle-Speed Mode Fs = 48 kHz Dynamic Range18 to 24-Bit A-weightedunweighted 16-Bit A-weightedunweighted 10299--1081059996----9996--1051029693----dBdBdBdBTotal Harmonic Distortion + Noise18 to 24-Bit0 dB-20 dB-60 dB 16-Bit0 dB-20 dB-60 dB -------98-85-45-93-76-36-92-----------95-82-42-90-73-33-89-----dBdBdBdBdBdBDouble-Speed Mode Fs = 96 kHz Dynamic Range18 to 24-Bit A-weightedunweighted 16-Bit A-weightedunweighted 10299--1081059996----9996--1051029693----dBdBdBdBTotal Harmonic Distortion + Noise18 to 24-Bit0 dB-20 dB-60 dB 16-Bit0 dB-20 dB-60 dB -------98-85-45-93-76-36-92-----------95-82-42-90-73-33-89-----dBdBdBdBdBdBQuad-Speed Mode Fs = 192 kHz Dynamic Range18 to 24-Bit A-weightedunweighted 16-Bit A-weightedunweighted 10299--1081059996----9996--1051029693----dBdBdBdBTotal Harmonic Distortion + Noise18 to 24-Bit0 dB-20 dB-60 dB 16-Bit0 dB-20 dB-60 dB -------98-85-45-93-76-36-92-----------95-82-42-90-73-33-89-----dBdBdBdBdBdBAll Speed ModesInterchannel Isolation (1 kHz)-100--100-dB Analog OutputFull Scale Output 1.235•VA 1.300•VA 1.365•VA0.618•VA0.650•VA0.683•VA Vpp Interchannel Gain Mismatch-0.10.25-0.10.25dB Gain Drift-±100--±100-ppm/°C Output Impedance-100--100-ΩDC Current draw from an AOUT pin--10--10µA(Note 10)AC-Load Resistance (R L)(Note 12)3--3--kΩLoad Capacitance (C L)(Note 12)--100--100pFANALOG OUTPUT CHARACTERISTICS (CS42438-DMZ)(Test Conditions (unless otherwise specified): VLS = VLC = VD = 3.3 V,VA = 5V; Measurement Bandwidth is10Hz to 20kHz unless otherwise specified; Full scale 997 Hz output sine wave (see Note 11); Single-ended test load: R L = 3kΩ, C L = 10 pF.)ParameterDifferentialMin Typ MaxSingle-EndedMin Typ Max UnitSingle-Speed Mode Fs = 48 kHz Dynamic Range18 to 24-Bit A-weightedunweighted 16-Bit A-weightedunweighted 10097--1081059996----9794--1051029693----dBdBdBdBTotal Harmonic Distortion + Noise18 to 24-Bit0 dB-20 dB-60 dB 16-Bit0 dB-20 dB-60 dB -------98-85-45-93-76-36-90------------95-82-42-90-73-33-87-----dBdBdBdBdBdBDouble-Speed Mode Fs = 96 kHz Dynamic Range18 to 24-Bit A-weightedunweighted 16-Bit A-weightedunweighted 10097--1081059996----9794--1051029693----dBdBdBdBTotal Harmonic Distortion + Noise18 to 24-Bit0 dB-20 dB-60 dB 16-Bit0 dB-20 dB-60 dB -------98-85-45-93-76-36-90------------95-82-42-90-73-33-87-----dBdBdBdBdBdBQuad-Speed Mode Fs = 192 kHz Dynamic Range18 to 24-Bit A-weightedunweighted 16-Bit A-weightedunweighted 10097--1081059996----9794--1051029693----dBdBdBdBTotal Harmonic Distortion + Noise18 to 24-Bit0 dB-20 dB-60 dB 16-Bit0 dB-20 dB-60 dB -------98-85-45-93-76-36-90------------95-82-42-90-73-33-87-----dBdBdBdBdBdBNotes:10.Guaranteed by design. The DC current draw represents the allowed current draw from the AOUT pindue to typical leakage through the electrolytic DC blocking capacitors.11.One-half LSB of triangular PDF dither is added to data.12.Guaranteed by design. See Figure 3. R L and C L reflect the recommended minimum resistance andmaximum capacitance required for the internal op-amp's stability and signal integrity. In this circuit topology, C L will effectively move the dominant pole of the two-pole amp in the output stage. Increasing this value beyond the recommended 100 pF can cause the internal op-amp to become unstable. See Appendix A for a recommended output filter.All Speed ModesInterchannel Isolation (1 kHz)-100--100-dBAnalog Output Full Scale Output 1.210•VA 1.300•VA 1.392•VA 0.605•VA 0.650•VA 0.696•VA VppInterchannel Gain Mismatch -0.10.25-0.10.25dB Gain Drift -±100--±100-ppm/°C Output Impedance -100--100-ΩDC Current draw from an AOUT pin (Note 10)--10--10µAAC-Load Resistance (R L )(Note 12)3--3--k ΩLoad Capacitance (C L )(Note 12)--100--100pFFigure 3. Output Test Load Figure 4. Maximum Loading。

QPSK

WIRELESS, RF, AND CABLE Application Note 686: Oct 13, 2000QPSK Modulation DemystifiedReaders are presented with step by step derivations showing the operation of QPSK modulation and demodulation. The move from analog communication to digital has advanced the use of QPSK. Euler's relation is used to assist analysis of multiplication of sine and cosine signals. A SPICE simulation is used to illustrate QPSK modulationof a 1MHz sine wave. A phasor diagram shows the impact of poor synchronizationwith the local oscillator. Digital processing is used to remove phase and frequency errors.Since the early days of electronics, as advances in technology were taking place, the boundaries of both local and global communication began eroding, resulting in a world that is smaller and hence more easily accessible for the sharing of knowledge and information. The pioneeringwork by Bell and Marconi formed the cornerstone of the information age that exists today and paved the way for the future of telecommunications.Traditionally, local communication was done over wires, as this presented a cost-effective wayof ensuring a reliable transfer of information. For long-distance communications, transmissionof information over radio waves was needed. Although this was convenient from a hardware standpoint, radio-waves transmission raised doubts over the corruption of the information and was often dependent on high-power transmitters to overcome weather conditions, large buildings, and interference from other sources of electromagnetics.The various modulation techniques offered different solutions in terms of cost-effectivenessand quality of received signals but until recently were still largely analog. Frequency modulation and phase modulation presented a certain immunity to noise, whereas amplitude modulation was simpler to demodulate. However, more recently with the advent of low-cost microcontrollers and the introduction of domestic mobile telephones and satellite communications, digital modulation has gained in popularity. With digital modulation techniques come all the advantages that traditional microprocessor circuits have over their analog counterparts. Any shortfalls in the communications link can be eradicated using software. Information can now be encrypted, error correction can ensure more confidence in received data, and the use of DSP can reduce the limited bandwidth allocated to each service. As with traditional analog systems, digital modulation can use amplitude, frequency, or phase modulation with different advantages. As frequency and phase modulation techniques offer more immunity to noise, they are the preferred scheme for the majority of services in use today and will be discussed in detail below.Digital Frequency ModulationA simple variation from traditional analog frequency modulation (FM) can be implemented by applying a digital signal to the modulation input. Thus, the output takes the form of a sine wave at two distinct frequencies. To demodulate this waveform, it is a simple matter of passing the signal through two filters and translating the resultant back into logic levels. Traditionally, this form of modulation has been called frequency-shift keying (FSK).Digital Phase ModulationSpectrally, digital phase modulation, or phase-shift keying (PSK), is very similar to frequency modulation. It involves changing the phase of the transmitted waveform instead of the frequency, these finite phase changes representing digital data. In its simplest form, a phase-modulated waveform can be generated by using the digital data to switch between two signals of equal frequency but opposing phase. If the resultant waveform is multiplied by a sine wave of equal frequency, two components are generated: one cosine waveform of double the received frequency and one frequency-independent term whose amplitude is proportional to the cosine of the phase shift. Thus, filtering out the higher-frequency term yields the original modulating data prior to transmission.This is difficult to picture conceptually, but mathematical proof will be shown later.Quadraphase-Shift ModulationTaking the above concept of PSK a stage further, it can be assumed that the number of phase shifts is not limited to only two states. The transmitted "carrier" can undergo any number of phase changes and, by multiplying the received signal by a sine wave of equal frequency, will demodulate the phase shifts into frequency-independent voltage levels.This is indeed the case in quadraphase-shift keying (QPSK). With QPSK, the carrier undergoes four changes in phase (four symbols) and can thus represent 2 binary bits of data per symbol. Although this may seem insignificant initially, a modulation scheme has now been supposed that enables a carrier to transmit 2 bits of information instead of 1, thus effectively doubling the bandwidth of the carrier.The proof of how phase modulation, and hence QPSK, is demodulated is shown below.The proof begins by defining Euler's relations, from which all the trigonometric identities can be derived.Euler's relations state the following:which gives an output frequencyby any phase-shifted sine wave.To prove this,Thus, the above proves the supposition that the phase shift on a carrier can be demodulated into a varying output voltage by multiplying the carrier with a sine-wave local oscillator and filtering out the high-frequency term. Unfortunately, the phase shift is limited to two quadrants;a phase shift of /2. Therefore, to accurately decode phase shifts present in all four quadrants, the input signal needs to be multiplied by bothsinusoidal and cosinusoidal waveforms, the high frequency filtered out, and the data reconstructed. The proof of this, expanding on the above mathematics, is shown below. Thus,A SPICE simulation verifies the above theory.Figure 1A shows a block diagram of a simple demodulator circuit. The input voltage, QPSK IN, is a 1MHz sine wave whose phase is shifted by 45°, 135°, 225°, and then 315° every 5µs.Figures 2 and 3 show the "in-phase" waveform, Vi, and the "quadrature" waveform, V q, respectively. Both have a frequency of 2MHz with a dc offset proportional to the phase shift, confirming the above mathematics.Figure 1B is the phasor diagram showing the phase shift of QPSK IN and the demodulated data.The above theory is perfectly acceptable, and it would appear that removing the data from the carrier is a simple process of low-pass filtering the output of the mixer and reconstructing the 4 voltages back into logic levels. In practice, getting a receiver local oscillator exactly synchronized with the incoming signal is not easy. If the local oscillator varies in phase with the incoming signal, the signals on the phasor diagram will undergo a phase rotation, its magnitude equal to the phase difference. Moreover, if the phase and frequency of the local oscillator are not fixed with respect to the incoming signal, there will be a continuing rotation on the phasor diagram.Therefore, the output of the front-end demodulator is normally fed into an ADC and any rotation resulting from errors in the phase or frequency of the local oscillator are removed in DSP.With the advances in monolithic silicon germanium (SiGe) technology, all of the above front-end circuitry can be integrated to reduce the problems outlined. A good example of how much of the front-end circuitry can be integrated is illustrated in the MAX2450, ultra-low-power quadrature modulator/demodulator IC. This is one of many devices from Maxim Integrated Products that incorporates the quadraphase shifter, the on-chip oscillator, and the mixer. Once the data has been demodulated, the output can be applied to a high-frequency dual-channel ADC (such as the MAX1002 or the MAX1003) before processing the signal in DSP.As the MAX2450 is designed to be used at an IF of 35MHz to 80MHz, RF signals up to2.5GHz can be downconverted using the MAX2411A. This is a high-frequencyup/downconverter with a low-noise amplifier (LNA) local oscillator, and it has access to the output of the LNA for image-reject filtering.Alternatively, an effective way of converting straight to baseband is using a direct-conversion tuner IC. The MAX2102 is designed to take RF inputs from 2150MHz and convert directly down to baseband I and Q signals, thus providing cost savings over multiple-stage devices. The above devices are part of the rapidly expanding RF chipsets from Maxim Integrated Products. With five high-speed processes, more than 70 high-frequency standard products, and 52 ASICs in development, Maxim is committed to being a major player in the RF/wireless, fiber/cable, and instrumentation markets.MORE INFORMATIONMAX1002:QuickView -- Full (PDF) Data Sheet (120k)-- Free Sample MAX1003:QuickView -- Full (PDF) Data Sheet (128k)-- Free Sample MAX2102:QuickView -- Full (PDF) Data Sheet (160k)-- Free Sample MAX2361:QuickView -- Full (PDF) Data Sheet (40k)-- Free Sample MAX2411A:QuickView -- Full (PDF) Data Sheet (144k)-- Free Sample MAX2450:QuickView -- Full (PDF) Data Sheet (120k)-- Free Sample。

AD9255

14-Bit, 125 MSPS/105 MSPS/80 MSPS,1.8 V Analog-to-Digital ConverterAD9255 Rev. AInformation furnished by Analog Devices is believed to be accurate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ©2009–2010 Analog Devices, Inc. All rights reserved.FEATURESSNR = 78.3 dBFS @ 70 MHz and 125 MSPSSFDR = 93 dBc @ 70 MHz and 125 MSPSLow power: 371 mW @ 125 MSPS1.8 V analog supply operation1.8 V CMOS or LVDS output supplyInteger 1-to-8 input clock dividerIF sampling frequencies to 300 MHz−153.4 dBm/Hz small signal input noise with 200 Ω input impedance @ 70 MHz and 125 MSPSOptional on-chip ditherProgrammable internal ADC voltage reference Integrated ADC sample-and-hold inputsFlexible analog input range: 1 V p-p to 2 V p-p Differential analog inputs with 650 MHz bandwidth ADC clock duty cycle stabilizerSerial port controlUser-configurable, built-in self-test (BIST) capability Energy-saving power-down modes APPLICATIONSCommunicationsMultimode digital receivers (3G)GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, andTD-SCDMASmart antenna systemsGeneral-purpose software radiosBroadband data applicationsUltrasound equipmentPRODUCT HIGHLIGHTS1.On-chip dither option for improved SFDR performancewith low power analog input.2.Proprietary differential input that maintains excellent SNRperformance for input frequencies up to 300 MHz.3.Operation from a single 1.8 V supply and a separate digitaloutput driver supply accommodating 1.8 V CMOS orLVDS outputs.4.Standard serial port interface (SPI) that supports variousproduct features and functions, such as data formatting(offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, test modes, and voltagereference mode.5.Pin compatibility with the AD9265, allowing a simplemigration up to 16 bits.FUNCTIONAL BLOCK DIAGRAM1414DRVDD (1.8V) D13 TO D0 OEBDCODITHERCLK+ CLK–SYNCCLOCKMANAGEMENTADC14-BITCOREOUTPUTSTAGINGCMOS ORLVDS(DDR)VCM VREFVIN+ VIN–TRACK-AND-HOLDREFERENCESERIAL PORTSVDD SCLK/DFSSDIO/DCSCSBAD9255OR855-1Figure 1.查询"AD9255"供应商Rev. A | Page 2 of 44TABLE OF CONTENTSFeatures .............................................................................................. 1 Applications ....................................................................................... 1 Product Highlights ........................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications ..................................................................................... 4 ADC DC Specifications ................................................................. 4 ADC AC Specifications ................................................................. 5 Digital Specifications ................................................................... 6 Switching Specifications ................................................................ 8 Timing Specifications .................................................................. 9 Absolute Maximum Ratings .......................................................... 10 Thermal Characteristics ............................................................ 10 ESD Caution ................................................................................ 10 Pin Configurations and Function Descriptions ......................... 11 Typical Performance Characteristics ........................................... 15 Equivalent Circuits ......................................................................... 23 Theory of Operation ...................................................................... 25 ADC Architecture ...................................................................... 25 Analog Input Considerations .................................................... 25 Voltage Reference ....................................................................... 28 Clock Input Considerations ...................................................... 29 Power Dissipation and Standby Mode .................................... 31 Digital Outputs ........................................................................... 32 Timing ......................................................................................... 32 Built-In Self-Test (BIST) and Output Test .................................. 33 Built-In Self-Test (BIST) ............................................................ 33 Output Test Modes ..................................................................... 33 Serial Port Interface (SPI) .............................................................. 34 Configuration Using the SPI ..................................................... 34 Hardware Interface ..................................................................... 34 Configuration Without the SPI ................................................ 35 SPI Accessible Features .............................................................. 35 Memory Map .................................................................................. 36 Reading the Memory Map Register Table ............................... 36 Memory Map Register Table ..................................................... 37 Memory Map Register Descriptions ........................................ 39 Applications Information .............................................................. 40 Design Guidelines ...................................................................... 40 Outline Dimensions ....................................................................... 41 Ordering Guide .. (41)REVISION HISTORY1/10—Rev. 0 to Rev. AChanges to Worst Other (Harmonic or Spur) Parameter,Table 2 ................................................................................................ 6 Changes to Figure 77 ...................................................................... 29 Changes to Input Clock Divider Section ..................................... 30 Changes to Table 17 ........................................................................ 37 Updated Outline Dimensions . (41)10/09—Revision 0: Initial VersionRev. A | Page 3 of 44GENERAL DESCRIPTIONThe AD9255 is a 14-bit, 125 MSPS analog-to-digital converter (ADC). The AD9255 is designed to support communications applications where high performance combined with low cost, small size, and versatility is desired.The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic to provide 14-bit accuracy at 125 MSPS data rates and guarantees no missing codes over the full operating temperature range. The ADC features a wide bandwidth differential sample-and-hold analog input amplifier supporting a variety of user-selectable input ranges. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the Nyquist rate. Combined with power and cost savings over previously available ADCs, the AD9255 is suitable for applications in communications, instrumentation, and medical imaging. A differential clock input controls all internal conversion cycles. A duty cycle stabilizer provides the means to compensate for vari-ations in the ADC clock duty cycle, allowing the converters to maintain excellent performance over a wide range of input clock duty cycles. An integrated voltage reference eases design considerations.The ADC output data format is either parallel 1.8 V CMOS or LVDS (DDR). A data output clock is provided to ensure proper latch timing with receiving logic.Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface. Flexible power-down options allow significant power savings, when desired. An optional on-chip dither function is available to improve SFDR performance with low power analog input signals.The AD9255 is available in a Pb-free, 48-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.Rev. A | Page 4 of 44SPECIFICATIONSADC DC SPECIFICATIONSAVDD = 1.8 V , DRVDD = 1.8 V , SVDD = 1.8 V , maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 1.Parameter Temp AD9255BCPZ-801 AD9255BCPZ-1051 AD9255BCPZ-1251Unit Min Typ Ma x Min Typ Ma x Min Typ Ma x RESOLUTION Full 14 14 14 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full ±0.05 ±0.25 ±0.05 ±0.25 ±0.05 ±0.25 % FSRGain Error Full ±0.2 ±2.5 ±0.2 ±2.5 ±0.4 ±2.5 % FSR Differential Nonlinearity (DNL)2 Full ±0.4 ±0.4 ±0.45 LSB 25°C ±0.2 ±0.2 ±0.25 LSB Integral Nonlinearity (INL)2 Full ±0.9 ±0.9 ±1.2 LSB25°C ±0.35 ±0.45 ±0.7 LSB TEMPERATURE DRIFT Offset Error Full ±2 ±2 ±2 ppm/°C Gain Error Full ±15 ±15 ±15 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Full +8 ±12 +8 ±12 +8 ±12 mV Load Regulation @ 1.0 mA Full 3 3 3 mV INPUT REFERRED NOISE VREF = 1.0 V 25°C 0.62 0.63 0.61 LSB rmsANALOG INPUTInput Span, VREF = 1.0 V Full 22 2 V p-pInput Capacitance 3 Full88 8 pFInput Common-Mode Voltage Full 0.90.9 0.9 VREFERENCE INPUT RESISTANCE Full 66 6 kΩPOWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 VSVDD Full1.7 3.5 1.7 3.51.7 3.5VSupply CurrentIAVDD 2 Full 126131169176194 202 mA IDRVDD 2 (1.8 V CMOS) Full1319 23 mA IDRVDD 2 (1.8 V LVDS) Full3942 44 mA POWER CONSUMPTIONDC Input Full239248321332371 382 mW Sine Wave Input 2CMOS Output Mode Full252338 391 mW LVDS Output Mode Full306384 437 mW Standby Power 4 Full5454 54 mW Power-Down Power Full0.050.150.050.150.05 0.15 mW1 The suffix following the part number refers to the model found in the Ordering Guide section.2Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. 3Input capacitance refers to the effective capacitance between one differential input pin and AGND. 4Standby power is measured with a dc input, the CLK pins (CLK+, CLK−) inactive (set to AVDD or AGND).Rev. A | Page 5 of 44ADC AC SPECIFICATIONSAVDD = 1.8 V , DRVDD = 1.8 V , SVDD = 1.8 V , maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 2.Parameter 1 Temp AD9255BCPZ-802 AD9255BCPZ-1052 AD9255BCPZ-1252Unit Min Typ Max Min Typ Max Min Typ Max SI G NAL-TO-NOISE-RATIO (SNR) f IN = 2.4 MHz 25°C 79.2 78.9 78.3 dBFS f IN = 70 MHz 25°C 78.9 78.5 78.3 dBFS Full 78.1 77.6 76.9 dBFS f IN = 140 MHz 25°C 78.0 77.7 77.1 dBFS f IN = 200 MHz 25°C 76.9 76.4 75.5 dBFSSIGNAL-TO-NOISE-AND DISTORTION (SINAD)f IN = 2.4 MHz 25°C 78.7 78.6 78.0 dBFS f IN = 70 MHz 25°C 78.7 78.0 78.0 dBFS Full 77.9 77.3 76.7 dBFS f IN = 140 MHz 25°C 76.8 77.0 76.7 dBFSf IN = 200 MHz 25°C 75.8 75.3 74.3 dBFSEFFECTIVE NUMBER OF BITS (ENOB)f IN = 2.4 MHz 25°C 12.812.8 12.7 Bits f IN = 70 MHz 25°C 12.812.7 12.7 Bits f IN = 140 MHz 25°C 12.512.5 12.4 Bits f IN = 200 MHz 25°C 12.312.2 12.0Bits WORST SECOND OR THIRD HARMONIC f IN = 2.4 MHz 25°C −88 −90 −88 dBc f IN = 70 MHz25°C −94 −89 −93 dBc Full −91−88 −85 dBc f IN = 140 MHz 25°C −82 −86 −89 dBc f IN = 200 MHz 25°C −81 −81 −80 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) f IN = 2.4 MHz 25°C 88 90 88 dBc f IN = 70 MHz 25°C 94 89 93 dBcFull 91 88 85 dBcf IN = 140 MHz 25°C 82 86 89 dBc f IN = 200 MHz 25°C 81 81 80 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) Without Dither (AIN @ −23 dBFS) f IN = 2.4 MHz 25°C 102 99 96 dBFS f IN = 70 MHz 25°C 103 97 99 dBFS f IN = 140 MHz 25°C 104 97 98 dBFS f IN = 200 MHz 25°C 102 101 97 dBFS With On-Chip Dither (AIN @ −23 dBFS) f IN = 2.4 MHz 25°C 110 109 108 dBFS f IN = 70 MHz 25°C 110 108 109 dBFS f IN = 140 MHz 25°C 110 108 109 dBFS f IN = 200 MHz 25°C 110 109 109 dBFSRev. A | Page 6 of 44Parameter 1 Temp AD9255BCPZ-802 AD9255BCPZ-1052 AD9255BCPZ-1252Unit Min Typ Max Min Typ Max Min Typ Max WORST OTHER (HARMONIC OR SPUR) Without Ditherf IN = 2.4 MHz 25°C −106 −105 −101dBc f IN = 70 MHz 25°C −106 −104 −104dBc Full −94−95 −91 dBc f IN = 140 MHz 25°C −104 −104 −103dBc f IN = 200 MHz 25°C −102 −103 −100dBc With On-Chip Ditherf IN = 2.4 MHz 25°C −105 −106 −101dBc f IN = 70 MHz 25°C −106 −105 −104dBc Full −97−99 −98 dBc f IN = 140 MHz 25°C −103 −103 −103dBc f IN = 200 MHz 25°C −100 −101 −100 dBc TWO-TONE SFDRWithout Ditherf IN = 29 MHz (−7 dBFS ), 32 MHz (−7 dBFS ) 25°C 9390 95 dBc f IN = 169 MHz (−7 dBFS ), 172 MHz (−7 dBFS ) 25°C 8078 79 dBc ANALOG INPUT BANDWIDTH25°C650650650 MHz1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation , for a complete set of definitions.2The suffix following the part number refers to the model found in the section.Ordering GuideDIGITAL SPECIFICATIONSAVDD = 1.8 V , DRVDD = 1.8 V , SVDD = 1.8 V , maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 3.Parameter Temperature Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.3 3.6 V p-p Input Voltage Range Full AGND AVDD V Input Common-Mode Range Full 0.9 1.4 V High Level Input Current Full −100 +100 μA Low Level Input Current Full −100 +100 μA Input Capacitance Full 4 pF Input Resistance Full 8 10 12 kΩ SYNC INPUT Logic Compliance CMOS Internal Bias Full 0.9 V Input Voltage Range Full AGND AVDD V High Level Input Voltage Full 1.2 AVDD V Low Level Input Voltage Full AGND 0.6 V High Level Input Current Full −100 +100 μA Low Level Input Current Full −100 +100 μA Input Capacitance Full 1 pF Input Resistance Full 12 16 20 kΩRev. A | Page 7 of 44Parameter Temperature Min Typ Max UnitLOGIC INPUT (CSB)1High Level Input Voltage Full 1.22 SVDD V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 40 132 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF LOGIC INPUT (SCLK/DFS)2 High Level Input Voltage Full 1.22 SVDD V Low Level Input Voltage Full 0 0.6 V High Level Input Current (VIN = 1.8 V) Full −92 −135 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF LOGIC INPUT/OUTPUT (SDIO/DCS)1 High Level Input Voltage Full 1.22 SVDD V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 38 128 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF High Level Output Voltage Full 1.70 V Low Level Output Voltage Full 0.2 V LOGIC INPUTS (OEB, PDWN, DITHER, LVDS, LVDS_RS)2 High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current (VIN = 1.8 V) Full −90 −134 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF DIGITAL OUTPUTS (DRVDD = 1.8 V) CMOS Mode High Level Output Voltage I OH = 50 μA Full 1.79 V I OH = 0.5 mA Full 1.75 V Low Level Output Voltage I OL = 1.6 mA Full 0.2 V I OL = 50 μA Full 0.05 V LVDS Mode ANSI Mode Differential Output Voltage (V OD ) Full 290 345 400 mV Output Offset Voltage (V OS ) Full 1.15 1.25 1.35 V Reduced Swing Mode Differential Output Voltage (V OD ) Full 160 200 230 mV Output Offset Voltage (V OS ) Full 1.15 1.25 1.35 V1 Pull-up.2Pull-down.Rev. A | Page 8 of 44SWITCHING SPECIFICATIONSAVDD = 1.8 V , DRVDD = 1.8 V , SVDD = 1.8 V , maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 4.AD9255BCPZ-801 AD9255BCPZ-1051 AD9255BCPZ-1251 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full 625 625 625 MHzConversion Rate 2DCS Enabled Full 20 80 20 105 20 125 MSPS DCS Disabled Full 10 80 10 105 10 125 MSPS CLK Period—Divide-by-1 Mode (t CLK ) Full 12.5 9.5 8 ns CLK Pulse Width High (t CH ) Divide-by-1 Mode DCS Enabled Full 3.75 6.25 8.75 2.85 4.75 6.65 2.4 4 5.6 ns DCS Disabled 5.9 6.25 6.6 4.5 4.75 5.0 3.8 4 4.2 nsDivide-by-3 Mode, Divide-by-5 Mode, andDivide-by-7 Mode, DCS Enabled 3Full 0.8 0.8 0.8 ns Divide-by-2 Mode, Divide-by-4 Mode, Divide-by-6 Mode, and Divide-by-8 Mode, DCSEnabled or DCS Disabled 3Full 0.8 0.8 0.8 ns Aperture Delay (t A ) Full 1.0 1.0 1.0 ns Aperture Uncertainty (Jitter, t J ) Full 0.07 0.07 0.07 ps rms DATA OUTPUT PARAMETERS CMOS Mode Data Propagation Delay (t PD ) Full 2.4 2.8 3.4 2.4 2.8 3.4 2.4 2.8 3.4 ns DCO Propagation Delay (t DCO )4 Full 2.7 3.4 4.2 2.7 3.4 4.2 2.7 3.4 4.2 ns DCO to Data Skew (t SKEW ) Full 0.3 0.6 0.9 0.3 0.6 0.9 0.3 0.6 0.9 ns Pipeline Delay (Latency) Full 12 12 12 Cycles LVDS Mode Data Propagation Delay (t PD ) Full 2.6 3.4 4.2 2.6 3.4 4.2 2.6 3.4 4.2 nsDCO Propagation Delay (t DCO )4Full 3.3 3.8 4.3 3.3 3.8 4.3 3.3 3.8 4.3 ns DCO to Data Skew (t SKEW ) −0.3 +0.4 +1.2 −0.3 +0.4 +1.2 −0.3 +0.4 +1.2 Pipeline Delay (Latency) Full 12.5 12.5 12.5 CyclesWake-Up Time 5Full 500 500 500 μs OUT-OF-RANGE RECOVERY TIME Full 2 2 2 Cycles1 The suffix following the part number refers to the model found in the section. Ordering Guide 2Conversion rate is the clock rate after the divider. 3See the section for additional information on using the DCS with the input clock divider. Input Clock Divider 4Additional DCO delay can be added by writing to Bit 0 through Bit 4 in SPI Register 0x17 (see ). Table 175Wake-up time is defined as the time required to return to normal operation from power-down mode.Rev. A | Page 9 of 44TIMING SPECIFICATIONSTable 5.ParameterConditions Min Typ Max Unit SYNC TIMING REQUIREMENTSt SSYNC SYNC to rising edge of CLK setup time 0.30 ns t HSYNCSYNC to rising edge of CLK hold time 0.40 ns SPI TIMING REQUIREMENTS 1t DS Setup time between the data and the rising edge of SCLK 2 ns t DH Hold time between the data and the rising edge of SCLK 2 ns t CLK Period of the SCLK40 ns t S Setup time between CSB and SCLK 2 ns t H Hold time between CSB and SCLK 2 ns t HIGH SCLK pulse width high 10 ns t LOW SCLK pulse width low10ns t EN_SDIO Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge10 ns t DIS_SDIOTime required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge10ns1Refer to for a detailed timing diagram.Figure 84Timing Diagrams08505-002NOTES1. DEx DENOTES EVEN BIT.2. DOx DENOTES ODD BIT.Figure 2. LVDS (DDR) and CMOS Output Mode Data Output Timing08505-104Figure 3. SYNC Input Timing RequirementsRev. A | Page 10 of 44ABSOLUTE MAXIMUM RATINGSTable 6.Parameter RatingElectrical AVDD to AGND −0.3 V to +2.0 VDRVDD to AGND −0.3 V to +2.0VSVDD to AGND −0.3 V to +3.6 VVIN+, VIN− to AGND −0.3 V to AVDD + 0.2 VCLK+, CLK− to AGND −0.3 V to AVDD + 0.2 VSYNC to AGND −0.3 V to AVDD + 0.2 V VREF to AGND −0.3 V to AVDD + 0.2 V SENSE to AGND −0.3 V to AVDD + 0.2 V VCM to AGND −0.3 V to AVDD + 0.2 V RBIAS to AGND −0.3 V to AVDD + 0.2 V CSB to AGND −0.3 V to SVDD +0.3 V SCLK/DFS to AGND −0.3 V to SVDD +0.3 V SDIO/DCS to AGND −0.3V to SVDD + 0.3 V OEB to AGND −0.3 V to DRVDD + 0.2 V PDWN to AGND −0.3 V to DRVDD + 0.2 V LVDS to AGND −0.3 V to AVDD + 0.2 V LVDS_RS to AGND −0.3 V to AVDD + 0.2 V DITHER to AGND −0.3 V to AVDD + 0.2 V D0 through D13 to AGND −0.3 V to DRVDD + 0.2 V DCO to AGND −0.3 V to DRVDD + 0.2 V EnvironmentalOperating Temperature Range(Ambient)−40°C to +85°C Maximum Junction TemperatureUnder Bias150°C Storage Temperature Range(Ambient)−65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or anyother conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL CHARACTERISTICSThe exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the customer board increases the reliability of the solder joints and maximizes the thermal capability of the package.Typical θJA is specified for a 4-layer PCB with a solid ground plane. As shown, airflow improves heat dissipation, which reduces θJA . In addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes, reduces the θJA . Table 7. Thermal ResistancePackage Type Airflow Velocity(m/s) θJA 1, 2 θJC 1, 3 θJB 1, 4 Unit 48-Lead LFCSP (CP-48-8)0 24.5 1.3 12.7 °C/W 1.0 21.4 °C/W 2.5 19.2 °C/W1Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.2Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3Per MIL-Std 883, Method 1012.1. 4Per JEDEC JESD51-8 (still air).ESD CAUTION131415161718192021222324D R V D D D 2D 3D 4D 5D 6D 7D R V D D D 8D 9D 10D 11484746454443424140393837P D W N R B I A S V C M A V D D L V D S V I N –V I N +L V D S _R S D N C D N C V R E F S E N S E SYNC CLK+CLK–AVDD AVDD OEB DNC DCO DNC DNC D0 (LSB)D1DITHER AVDD SVDD CSBSCLK/DFS SDIO/DCS DRVDD DNC ORD13 (MSB)D1235AVDD 3634333231302928272625PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONSNOTES1.DNC = DO NOT CONNECT.2.THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE INPUT. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.08505-003Figure 4. LFCSP Parallel CMOS Pin Configuration (Top View)Table 8. Pin Function Descriptions (Parallel CMOS Mode)Pin No. Mnemonic Type Description ADC Power Supplies 13, 20, 29 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 4, 5, 34, 36, 45 AVDD Supply Analog Power Supply (1.8 V Nominal). 33 SVDD Supply SPI Input/Output Voltage 7, 9, 10, 28, 39, 40 DNC Do Not Connect. 0 A G ND Ground Analog Ground. The exposed thermal pad on the bottom of the package providesthe analog ground for the input. This exposed pad must be connected to ground for proper operation.ADC Analog 42 VIN+ Input Differential Analog Input Pin (+). 43 VIN− Input Differential Analog Input Pin (−). 38 VREF Input/output Voltage Reference Input/Output. 37 SENSE Input Voltage Reference Mode Select. See Table 11 for details. 47 RBIAS Input/output External Reference Bias Resistor. 46 VCM Output Common-Mode Level Bias Output for Analog Inputs. 2 CLK+ Input ADC Clock Input—True. 3 CLK− Input ADC Clock Input—Complement. Digital Input 1 SYNC Input Digital Synchronization Pin. Slave mode only. Digital Outputs 11 D0 (LSB) Output CMOS Output Data. 12 D1 Output CMOS Output Data. 14 D2 Output CMOS Output Data. 15 D3 Output CMOS Output Data. 16 D4 Output CMOS Output Data. 17 D5 Output CMOS Output Data. 18 D6 Output CMOS Output Data. 19 D7 Output CMOS Output Data. 21 D8 Output CMOS Output Data.Pin No. Mnemonic Type Description22 D9 Output CMOS Output Data.23 D10 Output CMOS Output Data.24 D11 Output CMOS Output Data.25 D12 Output CMOS Output Data.26 D13 (MSB) Output CMOS Output Data.Output.Overrange27 OR Output8 DCO Output Data Clock Output.SPI Control31 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode.Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode.SPIInput/output30 SDIO/DCS32 CSB Input SPI Chip Select (Active Low).ADC Configuration6 OEB Input Output Enable Input (Active Low).Input35 DITHERIn external pin mode, this pin sets dither to on (active high). Pull low for control viaSPI in SPI mode.Input41 LVDS_RSIn external pin mode, this pin sets LVDS reduced swing output mode (active high).Pull low for control via SPI in SPI mode.Input44 LVDSIn external pin mode, this pin sets LVDS output mode (active high). Pull low forcontrol via SPI in SPI mode.48 PDWN Input Power-down input in external pin mode. In SPI mode, this input can be configuredas power-down or standby.131415161718192021222324D R V D D D 2/3–D 2/3+D 4/5–D 4/5+D 6/7–D 6/7+D R V D D D 8/9–D 8/9+D 10/11–D 10/11+484746454443424140393837P D W N R B I A S V C M A V D D L V D S V I N –V I N +L V D S _R S D N C D N C V R E F S E N S ESYNC CLK+CLK–AVDD AVDD OEB DCO–DCO+DNC DNC D0/1–D0/1+DITHER AVDD SVDD CSBSCLK/DFS SDIO/DCS DRVDD OR+OR–D12/13+D12/13–35AVDD 3634333231302928272625NOTES1.DNC = DO NOT CONNECT.2.THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGEPROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.08505-004Figure 5. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View)Table 9. Pin Function Descriptions (Interleaved Parallel LVDS Mode)Pin No. Mnemonic Type Description ADC Power Supplies 13, 20, 29 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 4, 5, 34, 36, 45 AVDD Supply Analog Power Supply (1.8 V Nominal). 33 SVDD Supply SPI Input/Output Voltage. 9, 10, 39, 40 DNC Do Not Connect. 0 A G ND Ground Analog Ground. The exposed thermal pad on the bottom of the package provides theanalog ground for the input. This exposed pad must be connected to ground for proper operation.ADC Analog 42 VIN+ Input Differential Analog Input Pin (+). 43 VIN− Input Differential Analog Input Pin (−). 38 VREF Input/output Voltage Reference Input/Output. 37 SENSE Input Voltage Reference Mode Select. See Table 11 for details. 47 RBIAS Input/output External Reference Bias Resistor. 46 VCM Output Common-Mode Level Bias Output for Analog Inputs. 2 CLK+ Input ADC Clock Input—True. 3 CLK− Input ADC Clock Input—Complement. Digital Input 1 SYNC Input Digital Synchronization Pin. Slave mode only. Digital Outputs 12 D0/1+ Output LVDS Output Data Bit 0/Bit 1 (LSB)—True. 11 D0/1− Output LVDS Output Data Bit 0/Bit 1 (LSB)—Complement. 15 D2/3+ Output LVDS Output Data Bit 2/Bit 3—True. 14 D2/3− Output LVDS Output Data Bit 2/Bit 3—Complement. 17 D4/5+ Output LVDS Output Data Bit 4/Bit 5—True. 16 D4/5− Output LVDS Output Data Bit 4/Bit 5—Complement. 19 D6/7+ Output LVDS Output Data Bit 6/Bit 7—True. 18 D6/7− Output LVDS Output Data Bit 6/Bit 7—Complement. 22 D8/9+ Output LVDS Output Data Bit 8/Bit 9 —True. 21 D8/9− Output LVDS Output Data Bit 8/Bit 9—Complement.。

QPsk 代码加结果

0123456012345678x 10-3误码率和信噪比的关系0200400600800100012001400160018002000-2-112lpf i0200400600800100012001400160018002000-2-112lpf q0200400600800100012001400160018002000-22i 路相乘信号0200400600800100012001400160018002000-22q 路相乘信号0200400600800100012001400160018002000-11解调信号0200400600800100012001400160018002000-4-3-2-11234过带通滤波器后的调制信号0200400600800100012001400160018002000-4-3-2-112340200400600800100012001400160018002000-11基带信号0200400600800100012001400160018002000-202i 路信号0200400600800100012001400160018002000-22q 路信号0200400600800100012001400160018002000-4-3-2-11234clc;y=1;h=1;p=zeros(1,7);perror=zeros(1,7);for SNR=0:6 % 信噪比for f=1:500% 初始化参数T=1e-5; % 基带信号宽度，也就是频率fc=5/T; % 载波频率ml=2; % 调制信号类型的一个标志位nb=20; % 传输的比特数delta_T=T/100; % 采样间隔fs=1/delta_T; % 采样频率t=0:delta_T:nb*T-delta_T; % 限定t 的取值范围N=length(t); % 采样数%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 调制部分%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 基带信号的产生data=randint(1,nb); % 调用一个随机函数（0 or 1），输出到一个1*100的矩阵datanrz=data.*2-1; % 变成极性码data1=zeros(1,2000); % 创建一个1*nb/delta_T 的零矩阵%将基带信号变换成对应波形信号data0=zeros(1,2000); % 创建一个1*nb/delta_T 的零矩阵for q=1:nbdata0((q-1)*100+1:q*100)=data(q); % 将非极性码变成对应的波形信号 end% 串并转换，将奇偶位数据分开idata=datanrz(1:ml:(nb-1)); % 将奇偶位分开，因此间隔m1为2idata0=zeros(1,2000); % 创建一个1*nb/delta_T的零矩阵for q=1:nb/2idata0(2*(q-1)*100+1:2*q*100)=idata(q); % 将其码元宽度扩展成为原来码元的2倍endqdata=datanrz(2:ml:nb);qdata0=zeros(1,2000);for q=1:nb/2qdata0(2*(q-1)*100+1:2*q*100)=qdata(q);end%%%%%%%% QPSK信号的调制%%%%%%%%%%%%for ii=1:Na(ii)=cos(2*pi*fc*t(ii));endidata1=idata0.*a; % 奇数位数据与余弦函数相乘，得到一路的调制信号for jj=1:Nb(jj)=-sin(2*pi*fc*t(jj));endqdata1=qdata0.*b; % 偶数位数据与余弦函数相乘，得到另一路的调制信号s0=idata1+qdata1; % 将奇偶位数据合并，s即为QPSK调制信号%%%%%%%延迟信号%%%%%%%%delay=0.0019;for ii0=1:Na_dl(ii0)=cos(2*pi*fc*t(ii0)+delay);endidata1_dl=idata0.*a_dl; % 奇数位数据与余弦函数相乘，得到一路的调制信号for jj0=1:Nb_dl(jj0)=-sin(2*pi*fc*t(jj0)+delay);endqdata1_dl=qdata0.*b_dl; % 偶数位数据与余弦函数相乘，得到另一路的调制信号s1=idata1_dl+qdata1_dl; % 将奇偶位数据合并，s即为QPSK调制信号%%%%%%%%%%%%%%%%%%%%%%%%%%% 高斯信道si=s0+s1;sk=awgn(si,SNR); % 通过高斯信道之后的信号%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%butter数字带通滤波器[B,A]=butter(4,[0.08,0.12],'bandpass');sr=filter(B,A,sk);%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%解调部分idata_lpf=sr.*a; % 这里面其实隐藏了一个串并转换的过程qdata_lpf=sr.*b; % 对应的信号与正余弦信号相乘%%%%%%低通滤波器%%%%%%%%%[W,M]=butter(4,0.03365,'low');idata2=filter(W,M,idata_lpf);qdata2=filter(W,M,qdata_lpf);idata3=zeros(1,nb/2);% 建立1*nb/2数组，以存放解调之后的信号qdata3=zeros(1,nb/2);% 抽样判决的过程，与0作比较，data>=0,则置1，否则置0for n=1:nb/2% A1(n)=sum(idata2((n-1)/delta_T+1:n/delta_T));if sum(idata2((n-1)*200+1:n*200))>=0idata3(n)=1;else idata3(n)=0;endif sum(qdata2((n-1)*200+1:n*200))>=0qdata3(n)=1;else qdata3(n)=0;endend% 将判决之后的数据存放进数组demodata=zeros(1,nb); %解调信号demodata(1:ml:(nb-1))=idata3; % 存放奇数位demodata(2:ml:nb)=qdata3; % 存放偶数位%为了显示，将它变成波形信号（即传输一个1代表单位宽度的高电平）demodata1=zeros(1,2000); % 创建一个1*nb/delta_T的零矩阵for q=1:nbdemodata1((q-1)*100+1:q*100)=demodata(q); % 将极性码变成对应的波形信号end %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 误码率计算for v=1:length(data);if data(v)~=demodata(v);p(h)=p(h)+1;endendendperror(y)=p(h)/10000;y=y+1;h=h+1;endfigure(1)subplot(311);plot(data0),title('基带信号');axis([0 2000 -1.5 1.5]);subplot(312);plot(idata0),title('i路信号');axis([0 2000 -3 3]);subplot(313);plot(qdata0),title('q路信号');axis([0 2000 -3 3]);figure(2)plot(si),title('过高斯信道前的调制信号'); axis([0 2000 -4 4]);figure(3)plot(a),title('载波信号');axis([0 200 -3 3]);figure(4)plot(sk),title('过高斯信道后的调制信号'); axis([0 2000 -4 4]);figure(5)plot(sr),title('过带通滤波器后的调制信号'); axis([0 2000 -4 4]);figure(6)subplot(311);plot(idata_lpf),title('i路相乘信号');axis([0 2000 -3 3]);subplot(312);plot(qdata_lpf),title('q路相乘信号');axis([0 2000 -3 3]);subplot(313);plot(demodata1),title('解调信号');axis([0 2000 -1.5 1.5]);figure(7)subplot(211);plot(idata2);title('lpf_i');subplot(212);plot(qdata2);title('lpf_q');figure(8)SNR=0:6;plot(SNR,perror);title('误码率和信噪比的关系'); axis([0 6 0 0.008]);。

LTM9011-14, LTM9010-14, LTM9009-14, LTM9008-14, LT

1dc1884afaDescriptionLTM9009-14, LTM9008-14, LTM9007-14,LTM9006-14: 14-Bit, 125/105/80/65/40/25Msps Octal ADC FamilyDC1884 supports the LTM ®9011 high speed, octal ADC family.The versions of the 1884A demo board are listed in Table 1. Depending on the required resolution and sample rate, the DC1884 is supplied with the appropriate ADC. The circuitry on the analog inputs is optimized for analog inputPARAMETERCONDITIONVALUESupply Voltage – DC1884A Depending on Sampling Rate and the A/D Converter Provided, This Supply Must Provide Up to 700mA Optimized for 3.5V[3.3V to 6V Minimum/Maximum]Analog Input Range Depending on SENSE Pin Voltage 1V P-P to 2V P-P Logic Input VoltagesMinimum Logic High 1.3V Maximum Logic Low0.6VLogic Output Voltages (Differential)Nominal Logic Levels (100Ω Load, 3.5mA Mode)350mV/1.25V Common Mode Minimum Logic Levels (100Ω Load, 3.5mA Mode)247mV/1.25V Common Mode Sampling Frequency (Convert Clock Frequency)See Table 1Encode Clock Level Single-Ended Encode Mode (ENC – Tied to GND)0V to 3.6V Encode Clock Level Differential Encode Mode (ENC – Not Tied to GND)0.2V to 3.6VResolutionSee Table 1Input Frequency Range See Table 1SFDR See Applicable Data Sheet SNRSee Applicable Data Sheetperformance summaryfrequencies from 1MHz to 70MHz. Refer to the data sheet for proper input networks for different input frequencies. Design files for this circuit board are available at http://www.linear .com/demo/DC1884AL , L T , L TC, L TM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.Table 1. DC1884 VariantsDC1884 VARIANTSADC PART NUMBER RESOLUTION MAXIMUM SAMPLE RATEINPUT FREQUENCY 1884A-A LTM9011-1414-Bit 125Msps 1MHz to 70MHz 1884A-B LTM9010-1414-Bit 105Msps 1MHz to 70MHz 1884A-C LTM9009-1414-Bit 80Msps 1MHz to 70MHz 1884A-D LTM9008-1414-Bit 65Msps 1MHz to 70MHz 1884A-E LTM9007-1414-Bit 40Msps 1MHz to 70MHz 1884A-FLTM9006-1414-Bit25Msps1MHz to 70MHz(T A = 25°C)2dc1884afaQuick start proceDureDC1884 is easy to set up to evaluate the performance of the LTM9011 family of A/D converters. For proper mea-surement equipment setup, refer to Figure 1 and follow the procedure explained in the following sections.Figure 1. Test Setup of DC1884DC1884A F01ANALOGINPUTSJUMPERS SHOWN INQuick start proceDureSetupIf a DC1371 data acquisition and collection system was supplied with the DC1884, follow the DC1371 Quick Start Guide to install the required software and to connect the DC1371 to the DC1884 and to a PC.DC1884 Board JumpersThe DC1884 board should have the following jumper set-tings as default positions (as per Figure 1):JP14: PAR/SER: Selects Parallel or Serial Programming Mode. (Default: Serial)Optional Jumpers AJ3 and J6: Term: Enables/Disable Optional Output Termination. (Default: Removed)JP5: I LVDS: Selects Either 1.75mA or 3.5mA of Output Current for the LVDS Drivers. (Default: Removed)JP1 and JP2: Lane: Selects Either 1-L ane or 2-L ane Output Modes (Default: Removed)Note: The DC1371 does not support 1-Lane operation. JP9: SHDN: Enables and Disables the LTM9011. (Default: Removed)JP8: WP: Enable/Disables Write Protect for the EEPROM. (Default: Removed)Note: Optional jumper should be left open to ensure proper serial configuration.Applying Power and Signals to the DC1884The DC1371 is used to acquire data from the DC1884. The DC1371 must first be connected to a powered USB port and have 5V applied power before applying 3.5V across the pins marked V+ and “GND” on the DC1884. DC1884 requires 3.5V for proper operation.The DC1884 demonstration circuit requires up to 700mA depending on the sampling rate and the A/D converter supplied.The DC1884 should not be removed or connected to the DC1371 while power is applied.Analog Input NetworkFor optimal distortion and noise performance, the RC network on the analog inputs may need to be optimized for different analog input frequencies. For input frequen-cies above 70MHz, refer to the LTM9011 data sheet for a proper input network.In almost all cases, filters will be required on both analog input and encode clock to provide data sheet SNR. The filters should be located close to the inputs to avoid reflections from impedance discontinuities at the driven end of a long transmission line. Most filters do not present 50Ω outside the passband. In some cases, 3dB to 10dB pads may be required to obtain low distortion.If your generator cannot deliver full-scale signals without distortion, you may benefit from a medium power amplifier based on a gallium arsenide gain block prior to the final filter. This is particularly true at higher frequencies where IC based operational amplifiers may be unable to deliver the combination of low noise figure and high IP3 point required. A high order filter can be used prior to this final amplifier, and a relatively lower Q filter used between the amplifier and the demonstration circuit.Encode ClockNote: Apply an encode clock to the SMA connector on the DC1884 demonstration circuit board marked “J2 CLK+.” As a default, the DC1884 is populated to have a single-ended input.For the best noise performance, the ENCODE input must be driven with a very low jitter, square wave source. The amplitude should be large, up to 3V P-P or 13dBm. When using a sinusoidal signal generator, a squaring circuit can be used. Linear Technology also provides demo board DC1075A that divides a high frequency sine wave by four, producing a low jitter square wave for best results with the LTM9011.3dc1884afaQuick start proceDureUsing bandpass filters on the clock and the analog input will improve the noise performance by reducing the wideband noise power of the signals. In the case of the DC1884 a bandpass filter used for the clock should be used prior to the DC1075A. Data sheet FFT plots are taken with 10 pole LC filters made by TTE (Los Angeles, CA) to suppress signal generator harmonics, non harmonically related spurs and broadband noise. L ow phase noise Agilent 8644B generators are used for both the clock input and the analog input.Digital OutputsData outputs, data clock, and frame clock signals are available on J1 of the DC1884. This connector follows the VITA-57/FMC standard, but all signals should be verified when using an FMC carrier card other than the DC1371. SoftwareThe DC1371 is controlled by the PScope system software that can be downloaded from the L inear Technology website at /software/.To start the data collection software, “PScope.exe,” which is installed by default to \Program Files\LTC\PScope\, double click the PScope icon or bring up the run window under the start menu, and browse to the PScope directory and select “PScope.”If the DC1884 is properly connected to the DC1371, PScope should automatically detect the DC1884 and configure itself accordingly.If everything is hooked up properly and a powered and suitable convert clock is present, clicking the “Collect” button should result in time and frequency plots displayed in the PScope window. Additional information and help for PScope is available in the DC1371 Quick Start Guide, and in the online help feature within the PScope program itself.Serial ProgrammingPScope has the ability to program the DC1884 serially through the DC1371. There are several options available in the LTM9011 family that are only available through serially programming. PScope allows all of these features to be tested.These options are available by first clicking on the “Set Demo Bd Options” icon on the PScope toolbar (Figure 2). This will bring up the menu shown in Figure 3.Figure 2. PScope ToolbarFigure 3. Demo Board Configuration Options4dc1884afa5dc1884afaInformation furnished by L inear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa-tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.Quick start proceDureThis menu allows any of the options available for the LTM9011 family to be programmed serially. The LTM9011 family has the following options:Randomizer : Enables Data Output Randomizer .• Off (Default): Disables data output randomizer . • On: Enables data output randomizer .T wo’s Complement : Enables T wo’s Complement Mode.• Off (Default): Selects offset binary mode.• On: Selects two’s complement mode.Sleep Mode : Selects Between Normal Operation and Sleep Mode.• Off (Default): Entire ADC is powered and active. • On: The entire ADC is powered down.Channel 1 Nap : Selects Between Normal Operation and Putting Channel 1 in Nap Mode.• Off (Default): Channel 1 is active.• On: Channel 1 is in nap mode.Channel 2 Nap : Selects Between Normal Operation and Putting Channel 2 in Nap Mode.• Off (Default): Channel 2 is active.• On: Channel 2 is in nap mode.Channel 3 Nap : Selects Between Normal Operation and Putting Channel 3 in Nap Mode.• Off (Default): Channel 3 is active.• On: Channel 3 is in nap mode.Channel 4 Nap : Selects Between Normal Operation and Putting Channel 4 in Nap Mode.• Off (Default): Channel 4 is active.• On: Channel 4 is in nap mode.Output Current : Selects the LVDS Output Drive Current.• 1.75mA (Default): LVDS output driver current.• 2.1mA: LVDS output driver current.• 2.5mA: LVDS output driver current.• 3.0mA: LVDS output driver current.• 3.5mA: LVDS output driver current.• 4.0mA: LVDS output driver current.• 4.5mA: LVDS output driver current.Internal Termination : Enables L VDS Internal Termination.• Off (Default): Disables internal termination.• On: Enables internal termination.Outputs : Enables Digital Outputs.• Enabled (Default): Enables digital outputs. • Disabled: Disables digital outputs.Test P attern : Selects Digital Output Test Patterns. The desired test pattern can be entered into the text boxes provided.• Off (Default): ADC input data is displayed.• On: Test pattern is displayed.Once the desired settings are selected, click “OK” and PScope will automatically update the register of the device on the DC1884 demo board.6dc1884afaLinear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417(408) 432-1900 ● FAX : (408) 434-0507 ● www.linear .comLINEAR TECHNOLOGY CORPORA TION 2012LT 0117 • PRINTED IN USADEMONSTRATION BOARD IMPORTANT NOTICELinear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions:This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete in terms of required design-, marketing-, and/or manµFacturing-related protective considerations, including but not limited to product safety measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations.If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or agency certified (FCC, UL, CE, etc.).No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.LTC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive .Please read the DEMO BOARD manual prior to handling the product . Persons handling this product must have electronics training and observe good laboratory practice standards. Common sense is encouraged .This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC application engineer.Mailing Address:Linear Technology 1630 McCarthy pitas, CA 95035Copyright © 2004, Linear Technology Corporation。

ProdSel_Edn9产品手册

CML Focus ProductsProducts that are production-released and recommended for new designsCML Microcircuits (CML) has, in over 40 years of operation, grown to be a world-leader in the design, development and support of low-power analogue, digital and mixed-signal semiconductors for telecommunications and control systems worldwide.As an experienced designer and manufacturer of ultra low-power Application Specific Standard and Custom Product ICs for an ever-widening range of communications and control applications, CML builds a wealth of knowledge, experience and support into all of its products.With a primary focus on all facets of wireless and wireline communications and control applications - from sub-audio through baseband to RF frequencies - CML offers a product portfolio that is second-to-none in the field.Highly experienced in the design of IC products to operate to proprietary communications systems and protocols, CML’s fast expanding custom design resource offers, in addition, unique paths to market for customer designs where a stock CML product does not suit. The newest member of this resource is our proprietary FirmASIC® technology, combining lowest overall cost, fastest time-to-market and lowest risk, with unsurpassed flexibility.Ultra Low Power OperationCML’s IC products consume significantly less power and provide more functionality than competing devices. This, of course, offers many ‘power/battery-saving’ advantages to radio, data and telecoms designs.High IntegrationPermits many more individual functions on a single chip. The majority of CML products comprise multiple functions, all designed to serve not only the main application but also its peripheral and system activities.As well as providing the main application functions, CML products generally offer the ‘extra’ analogue and digital functional and interfacing requirements not supplied by a DSP or host processor. This drastically reduces the requirement for extra ICs and their companion components, which in turn shrinks the overall PCB footprint requirement, thus allowing the design and production of a much smaller and lower-power end product.FirmASIC® , RALCWI™, Function Image™, Tone Clone™ are all registered trademark of CML Microsystems PlcTable Contents• RF 4• Analogue Two-way Radio 6• Digital PMR 8• Wireless Data 10• Digital Voice 12• Marine Comms 14• Wireline Telecom - Modems 16• Wireline Telecom - Telephony 18• Custom Resources and Embedded Products 21FirmASIC® Design TechnologyFirmASIC® is a proprietary component technology from CML that reduces cost, time to market and development risk, with increased flexibility for the designer and the end application. FirmASIC® combines Analogue, Digital, Firmware and Memory technologies in a single silicon platform that can be focused to deliver the right feature mix, performance and price for a target application family.Infinite ApplicationsCML’s wide-ranging product portfolio offers an expansive list of application possibilities for these versatile ICs.Due to the ease of implementation, continuous flexibility and the on-going application and technical support available, a CML IC product is the ideal and time-saving solution to the majority of customers communications and/or control problems.Reliable Customer and Product SupportThe CML network of over 100 distributor and representative companies worldwide, allied with its teams of application engineers, provides all CML customers with comprehensive local pre- and after-sales support.From product inception, through the design, manufacture and qualification stages, CML is there providing unequalled technical and application support.CML’s range of Radio Frequency (RF) products provides a selection of modular building blocks for implementation as part or all of the ‘wireless front-end’ of a wide range of constant and non-constant envelope modulation systems.The new RF Building Block range is designed to provide flexible, high-performance ICs required for HF/VHF/UHF professional radios, wireless data terminals, wireless microphones and marine and avionics radio systems.With an operating frequency ranging down to 20MHz and up to 1GHz, the RF products offer: a combination RF transceiver, a separate RF modulator and demodulator, and a Cartesian feedback loop transmitter for efficiency and transmitter PA linearisation.CML’s RF devices are designed for use in a wide range of both narrowband and wideband applications, in the wireless data and digital PMR markets.ApplicationsData over radio:MSK, FSK, GMSK, QPSK, QAM Wideband modulation systems up to 50MHz Linear and non-linear modulation schemes Wireless telemetry Marine AIS systems Software Defined Radio (SDR) Satellite terminals Digital TV - CATV mod. Wi-Max implementationsAnalogue, digital and multimode radio:TETRA, APCO, dPMR, DMR, PDTT/RCML’s two-way radio products address both the full baseband and individual communication requirements of analogue military, PMR/LMR, trunked and leisure radio systems.The analogue two-way radio product features include:• Baseband functions: audio processing, data, CTCSS, DCS, Selcall, XTCSS, single-tone operations and DTMF • Voiceband processing offering flexible functions such as: signal filtering, companding, scrambling, pre and de- emphasis and the digital control of all signal paths and levels• In-band signalling in the form of DTMF, Selcall and general single, dual and multi-tone operations• Sub-audio signalling (CTCSS and DCS), sub-audio signalling functions that operate alongside voicebandoperations.• Data functions are available on-chip, in both raw and packet formats, to enable data-over-radio (telemetry) and/or control signalling• RF support features such as system clocks, RF synthesisers and auxiliary ADCs and DACs.• Control of the majority of CML’s IC products via a serial bus (C-BUS)Applications General Two-way Radio Analogue PMR/LMR Trunked Radio FRS, GMRS, MURS and PMR446 Leisure Radio Wireless Data Comms Fixed and Rolling Code Voice Scramblers Status and Alarm Systems Portable and Mobile Radios On-site Repeaters Community Base Stations Marine VHF Radio Aviation Radio Amateur Radio National Weather Radio Systems Paging Systems Tone Squelch Systems Tone SignallingDoor Access and Gate EntryEV1480 Evkitb-Audio Signalling Filters for CTCSS and DCS Small VQFN and LQFP1. Brief Description The CMX148 is a half-duplex, audio, signalling and data processing IC for use in PMR the host µC to perform signalling, including CTCSS/DCS encoding/decoding. The de use in general leisure and professional PMR terminals. Comprehensive audio processing facilities include complete audio processing, filtering or de-emphasis and frequency inversion scrambling. The CMX148 features an FFSK for packetised or free-format data operations. Signal routing and filtering is included based signal encoding/decoding applications. A DTMF encoder/decoder, a full complement of auxiliary ADCs and DACs and dua outputs are included in this low power PMR processor. The device also has flexible p and is available in 48-pin VQFN and LQFP packages.CML offers a wide range of voice, signalling and data processing ICs for digital communications systems, integrating baseband processing and systems - specific Air Interface.Features include: vocoder support, layer 1 and layer 2 of system Air Interface data coding, data modems, plus auxiliary functions supporting the overall radio design. Solutions are available for both FDMA and TDMA based PMR/LMR systems.FDMA systemsdPMR446, dPMR mode 1/2/3, NXDN, ARIB-STD T98 and ARIB-STD T102Applications Digital Radio, FDMA SystemsdPMR446, dPMR mode 1/2/3NXDN,ARIB STD-T102ARIB STD-T98 DCRTDMA systemsTETRA, APCO P25DMR, PDT RCR-39 Digital WLL Satcoms Terminals Aviation Systems Mixed-mode Analogue/Digital RadiosTDMA systemsTETRA, DMR, APCO P25, PDTDE6181 Demo KitCMX994Wireless Data ProductsCML’s wireless data products address a wide range of communications and control applications, offering operation to custom, freeformat and packet data systems.Most common data-transfer protocols are catered for at a range of speeds from 1.2kbps to 200kbps, utilising: FSK, FFSK, GMSK, 2/4FSK and QAM modulation schemes.The advent of CML’s FirmASIC® technology has enabled the availability of the Multi-Mode Packet Data Modem offering configurable GMSK/GFSK, 2/4FSK, FFSK/MSK and QAM modulation schemes by the up-loading the appropriate Function Image™ file.The CMX7164 multi-mode (GMSK, 2/4FSK and QAM) Packet Data Modem and CMX7163 QAM Packet Data Modem are complemented by CML’s range of RF products, enabling highly-integrated wirelss data modems to be implemented.ApplicationsNarrowband Radio Systems Data Over Radio Radio-pagingWireless TelemetryMachine-to-Machine (M2M) Wireless Control Systems Wireless Monitoring SCADA Implementations Traffic (Vehicle) Location Differential GPS ISM BandsSoftware Defined Radio (SDR)DE9941 Demo Kit2 Block Diagram+3V3D +3V3A +3V3_VCOJ1AntennaJ3J4External LOWireless Data ProductsCML’s DuraTALK® family of digital voice products comprises a range of flexible technologies supporting voice-data generation, coding, transcoding and decoding functions for digital communication systems, as well asmany other in-band audio applications where there is a need for storage and playback.The DuraTALK® family currently consists of the following technologies:• TWELP™: Crystal clear digital voice for professional radio• RALCWI™: CML’s low bit-rate Vocoder• Transcoding: On-chip multi-transcoding/conversion of data formats• CVSD and ADM: Flexible error tolerant encoders/decodersThe flexible, low power, highly integrated TWELP™, RALCWI™, Transcoder and CVSD ICs are suited to wireless and wireline voice applications such as voice scramblers, alarm systems, military field applications and professional or leisure digital two-way radios.ApplicationsDigital FDMA Radios: dPMR/ARIB-STD Digital TDMA Radios: DMR/PDTVoice-over IP (VoIP)Voice Scrambling and Encryption Digital Wireless Local Loop Military Communications Satcom TerminalsTerrestrial Flight Telephone Systems Cordless Telephones Alarm SystemsVoice Store and Forward Voice AnnunciatorsVoice Store and Retrieval Call Center Call LoggingDelay LinesPE0101-7011 EvkitVoice Rx Tx out Voice outCML offers an increasing range of voice and data communication ICs in the support of marine safety equipments.AIS has become the essential navigation/safety equipment onboard leisure sailing yachts/motor cruisers, through to commercial vessels (fishing, cargo and passenger ships).CML’s AIS products include all the necessary signalling functionality, including the GMSK modem, DSC modem and embedded AIS protocol. AIS Class A, AIS Class B, AIS Rx only applications, AIS-SART, MOB/PLB and marine VHF voice communications are all supported.A VHF marine radio is an essential piece of equipment in both coastal and deep-water operations.CML provides complete world voice signalling and data solutions supporting voice communication, DSC, ATIS, DTMF, NWR WAT and SAME.ApplicationsAutomatic Identification System (AIS)AIS Class A transponderAIS Class B transponderAIS-SART (Search and Rescue Transmitter)Man overboard systems (MOB)Personal Location Beacon (PLB)Aids to Navigation (ATON)Marine VHF RadioAutomatic Transmission Identification System (ATIS) Asset trackingCoastal securityFigure 1 Rx-only Block Diagram: DE70321CML’s Low Power Wireline Modem products are employed worldwide in all types of communication applications.CML’s highly integrated ICs demand very little power or µC assistance, a factor that often means that the products can be line powered.The wireline data IC range covers most relevant ITu-T V recommendations and compatible Bellcore data specifications. These single chip wireline data products offer a full suite of wireline signalling functions to cater for complete system operations from line and call set-up right through to the completed data transaction.ApplicationsLow power wireline modems Wireline telemetry Pair-gain systemsPublic Switched Telephone Network (PSTN) Least cost routers Internet appliances Remote meter reading Set-top boxesSubscriber pulse metering Wireless Local Loop (WLL) Banking/billing systemsock DiagramFigure 1 Block DiagramDE8691 Demo KitCMX869BCML’s wireline telephony products cover all aspects of a telephone system’s operating requirements in the analogue, digital and mixed signal fields and are employed worldwide in all types of communication applications.CML’s highly integrated ICs perform the majority of telecoms voice, signalling and data functions whilst demanding very little power or µC assistance, a factor that often means that the product can be line powered.Analogue, digital and mixed-mode (POTS-to-ISDN) products are also available singularly, or in multi-feature combinations.The telephony range of IC products covers all of the voice and signalling requirements of a modern day telephone system.From Rx/Tx DTMF, calling-line ID and call progress functions through-to voice recognition in both the digital and analogue domains, these products also offer on-chip line/phone interfacing.ApplicationsLow power wirelineModems and wireline telemetry Telephones, Featurephones Payphones and PABX Calling line ID (CLI)Public Switched Telephone Network (PSTN) Integrated System Digital Network (ISDN) Least cost routers Pair-gain systems Internet appliances Set-top boxesRemote meter reading Subscriber pulse meteringWireless Local Loop (WLL)CML Microsystems Plc21CML Microcircuits offers a complete ‘turnkey’ service for the design and supply of custom ASIC solutions. Supporting all stages of ASIC development, from concept through design, layout, prototype-testing and the supply of production tested devices.Through CML, customers gain access to leading-edge technologies and a design team with extensive expertise specialising in: Analogue, Digital, Mixed-Signal, Memory and RF integrated circuit design.Technologies available encompass state-of-the-art processes and geometries, including: CMOS, BiCMOS, BiPOLAR and SiGe. Extensive custom cell libraries are available comprising: logic, analogue/mixed-signal, digital; including memory, µController, RISC/DSP and IP cores.FirmASIC ® is a CML proprietary technology that has been successfully deployed in a wide range of standard and custom product offerings. Key benefits of this technology include: fast time-to-market, low cost, low risk, small footprint and unsurpassed flexibility. A growing family of approved and stable FirmASIC ® hardware plaforms is available, each providing a different mix offixed and re-definable functions.The whole essence of FirmASIC ® is delivering a product with the right feature mix, performance and cost for a specifictarget application, in the shortest possible time.For more information on CML's Design Resource please speak to your local CML contact or enquire on-line via thehome page of our website: .As part of CML’s extensive wireline portfolio, CML features the CMX850 Communications Controller IC.This extremely compact and low-power modem/µController integration satisfies all of the communications, control, data and signalling requirements of any wireline end-product using on-line communications.Hyperstone, a fabless semiconductor company and a member of the CML Plc Group, offers a wide range of microprocessor and microcontroller products based on unified RISC/DSP architechture.Hyperstone Inc , based in the USA, represents the full range of Hyperstone products in North and South America,providing distribution and product engineering support.Focus ProductsE2 RISC/DSP MicrocontrollerhyNet XS and S Communication ControllersF4 and S6 Flash Memory ControllersIntegrated Development Tools AvailableYour Local CML DistributorCustom ASIC Design ResourcesEmbedded Products。

ATJ2091N Datasheet V1.1

Copyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.11/46 2007-3-22ATJ2091N DatasheetVersion 1.1DeclarationCircuit diagrams and other information relating to products of Actions Semiconductor Company, Ltd. (“Actions”) are included as a means or illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been examined and is believed to be accurate, Actions makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and disclaims any responsibility for inaccuracies. Information in this document is provided solely to enable use of Actions’ products. The information presented in this document does not form part of any quotation or contract for sale. Actions assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Actions’ products, except as may expressly be provided in Actions’ Terms and Conditions of Sale for such products. All sales of any Actions products are expressly conditional on your agreement to the terms and conditions of the most recently dated version of Actions’ Terms and Conditions of Sale Agreement dated before the date of your order.The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights, copyright, trademark rights, rights in trade secrets and/or know how, or any other intellectual property rights of Actions or others, however denominated, whether by express or implied representation, by estoppel, or otherwise.Information contained herein relates solely to the Actions products described herein and abrogates and supersedes, as of the release date of this publication, all previously published data and specifications relating to such products provided by Actions or by any other person purporting to distribute such information. Actions reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your Actions sales representative to obtain the latest specifications before placing your product order. Actions product may contain design defects or errors known as anomalies or errata which may cause the products functions to deviate from published specifications. Anomaly or “errata” sheets relating to currently characterized anomalies or errata are available upon request. Designers must not rely on the absence or characteristics of any features or instructions of Actions’ products marked “reserved” or “undefined.” Actions reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.Actions’ products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an OfficerCopyright© Actions Semiconductor Co., Ltd 2007. All rights reserved.Ver. 1.1 2/46 2007-3-22Copyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.13/46 2007-3-22 of Actions and further testing and/or modification will be fully at the risk of the customer. Copies of this document and/or other Actions product literature, as well as the Terms and Conditions of Sale Agreement, may be obtained by visiting Actions’ website at http:/ or from an authorized Actions representative. The word “ACTIONS,” the Actions’ LOGO, whether used separately and/or in combination, and the phase “ATJ2097,” are trademarks of Actions Semiconductor Company, Ltd.. Names and brands of other companies and their products that may from time to time descriptively appear in this product data sheet are the trademarks of their respective holders: no affiliation, authorization, or endorsement by such persons is claimed or implied except as may be expressly stated therein. ACTIONS DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE.IN NO EVENT SHALL ACTIONS BE RELIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF ACTIONS OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER ACTIONS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES OR NOT.Additional SupportAdditional product and company information can be obtained by visiting the Actions website at: Table of ContentsRevision History (6)1 .Introduction (7)2. Pin Description (10)2.1 Pin Out (10)2.2 Pin Definition (10)3. Function Description (14)3.1 Functional Block Diagram (14)3.2 MCU Core (15)3.2.1 MCU System Memory Mapping (15)3.3 DSP24 Core (17)3.4 ZRAM1 and ZRAM2 (17)3.5 USB2.0 SIE (18)3.5.1 General Description (18)3.5.2 Features (19)3.5.3 USB Using Memory (20)3.6 NAND Flash Interface (20)3.7 Key Scan Interface (20)3.8 LCD Interface (21)3.9 General Purpose IO Ports (23)3.10 LOSC/RTC (23)3.11 HOSC/PLL (24)3.12 PMU/DC-DC (25)3.13 A/D, D/A and Headphone Driver (25)3.13.1 D/A Interface (25)3.13.2 A/D Interface (26)4. Electrical Characteristics (27)4.1 Absolute Maximum Ratings (27)Copyright© Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.1 4/46 2007-3-22Copyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.15/46 2007-3-22 4.2 Capacitance (27)4.3 DC Characteristics (28)4.4 AC Characteristics (29)4.4.1 AC Test Input Waveform (29)4.4.2 AC Test Output Measuring Points (29)4.4.3 Reset Parameter (30)4.4.4 Initialization Parameter (30)4.4.5 GPIO Interface Parameter (30)4.4.6 Ordinary ROM Parameter (31)4.4.7 External System Bus Parameter (33)4.4.8 Bus Operation (34)4.4.9 Serial Interface Parameter (34)4.4.10 A/D Converter Characteristics (36)4.4.11 I2S Interface Parameter (36)4.4.12 Headphone Driver Characteristics Table (36)4.4.13 LCM Driver Parameter (38)4.4.14 SPI Parameter (39)5. Ordering Information (41)5.1 Soldering Conditions (41)5.2 Precaution Against ESD For Semiconductors (41)5.3 Status Before Initialization of MOS Devices (42)6. ATJ 2091N Package Drawing (43)7. Appendix (44)Copyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.16/46 2007-3-22 Revision History Version Date DescriptionVer1.0 Nov. 2006 1st version created for ATJ2091NVer1.1 Mar. 2007 2nd version modified for ATJ2091N, electrical characteristics added.1 .IntroductionATJ2091N is a third generation single-chip highly-integrated digital music system solution for devices such as dedicated audio players, PDAs, and cell phones. It includes an audio decoder with a high performance DSP with embedded RAM and ROM, ADPCM record capabilities and USB interface for downloading music and uploading voice recordings. ATJ2091N also provides an interface flash memory, LED/LCD, button and switch inputs, headphones, microphone and FM radio input and control. ATJ2091N contains a high performance DSP, which can easily be programmed to support many kinds of digital audio standards such as WMA, etc. For devices like USB-Disk, ATJ2091N can act as a USB mass storage slave device to personal computer system. ATJ2091N has low power consumption to allow long battery life and an efficient flexible on-chip DC-DC converter that allows many different battery configurations, including 1xAA and 1xAAA. The built-in Sigma-Delta DAC includes a headphone driver to directly drive low impedance headphones. The ADC includes inputs for both Microphone and Analog Audio in to support voice recording and FM radio integration features. ATJ2091N provides a true “ALL-IN-ONE” solution that is ideally suited for highly optimized digital audio players.Features:z MPEG1/2/2.5 Audio Layer 1,2,3 decoder, bit rate 8-448Kbps, 8-48KHz, CBR/VBRz Support WMA Decoder, bit rate 32-384Kbps, 8-48KHzz Digital Voice Recording at ultra low 4.4 or 8Kbps w/ Actions Speech Algorithmz24 bits DSP Core with on-chip Debug Support Unit (DSU)Copyright© Actions Semiconductor Co., Ltd 2007. All rights reserved.Ver. 1.1 7/46 2007-3-22Copyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.18/46 2007-3-22 z On-chip DSP PM with SRAM(16K*24) ,can be switched to be MCU memory space z On-chip DSP DM with SRAM(16K*24), can be switched to be MCU memory space z Integrated MCU with DSU, the instruction set is compatible with Z80z Internal (16K-64)x8(ZRAM1),(3K+3K)(ZRAM2) and 6k ZRAM3 accessed by MCU z Internal 12Kx8 BROM build in Boot up and USB Upgrade firmwarez Internal (21K+17K)x8 TROMz Internal SRAM access time<7ns, MROM access time<16nsz External up to 3(pcs)x 32M/64M/128M/256M/512M/1G/2G/4G bytes Nand type Flashaccessed by MCU or DMAz Support 24MHz OSC with on-chip PLL for DSP and about 32KHz RC oscillator z 2-channel DMA , 1-channel CTC(Counter/Timer Controller) and interrupt controller forMCUz Energy saving dynamic power management (PMU), supporting 1xAA and 1xAAA. z Support USB 2.0 Compliance PHY+SIE, Read :7MB/S, Write: 6MB/S( Nand FlashBase )z Build in Stereo 18-bit Sigma-Delta D/Az Build in Key Scan Circuit and GPIOz Support external 8080 Series LCM driver interfacez Support FM Radio input and 32 levels volume controlz Support Stereo 18-bit Sigma-Delta A/D for Microphone/FM Input/Line Input, samplerate at 8/12/16/22/24/32/48KHzz MCU run at 48MHz(typ),F/W can program from DC up to 60MHz transparently z DSP+PM/DM Speed up to 72MIPS,while 48mips@1.4vz D/A+PA SNR :with A weight>92dB,without A weight>=88dBz A/D SNR >79dBCopyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.19/46 2007-3-22 z Headphone driver output 2x11Mw @16ohmz Operating Voltage: IO: 3.0v, Core: 1.8vz Standby Leakage Current: VCC:50uA@3.0V(MAX), VDD: 350uA@1.6V(MAX) z Low Power Consumption : <80mW@1.5V at typical WMA decoder solutionCopyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.110/46 2007-3-22 2. Pin Description2.1 Pin Out2.2 Pin DefinitionNOTE:1： PWR---Power Supply2： AI----Analog InputCopyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.111/46 2007-3-223： AO----Analog Output 4： O-----Output 5： I-----Input 6： BI----Bidirection 7： TBD2C, BD2C, BD2XU, SBD2X, BD2XM5----2 miliampere driver 8： BD4CM2, BD4C, BD4CU----4 miliampere driver 9: BD1XM2----1 miliampere driver 10：USCU----USCHIMITCU Pin No. Pin Name I/O Type Driver Reset Default Description 1 VCC PWR / / Power supply for USB 2UREGAO / / USB precision Resistor 3 GND PWR / / USB ground 4 USBDP A / H USB data plus 5 USBDM A / H USB data minus6 RESET- I USCU H System reset input (active low)7 PAVCC PWR / / Power supply for power amplifier8 AOUTR AO / / Int. PA right channel analog output9 AOUTL AO / / Int. PA left channel analog output 10 PAGND PWR / / Power amplifier ground11VRDAAO / / Bypass capacitor connect pin for Int. D/A Reference voltage12 MICIN AI / / Microphone pre-amplifier input 13 VMIC PWR / / Power supply for Microphone 14FMINLAI / / Left channel of FM line input 15 FMINR AI / / Right channel of FM line input 16 AGND PWR / / Analog ground 17 AVCC PWR / / power supply of Analog 18 VREFI AI / / Voltage reference input 19 AVDD PWR / / Analog Core power pin 20VDDIOPWR/ZCore power input/outputCopyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.112/46 2007-3-2221 VP PWR / / Power pin22 LRADC1 AI / / Low resolution A/D input 1 23 PWRMode0 AI / / POWER mode select 024 HOSCI AI / / High frequency crystal OSC input 25 HOSCO AO / / High frequency crystal OSC output 26 VCC PWR / / PAD power pin 27 BAT I / / Battery Voltage input.GPIO_B0BIZ Bit0 of General purpose I/O port B 28KEYI0 I BD2CH Bit0 of key scan circuit input 29 GPIO_C2 BI BD4CM2/ Bit2 of General purpose I/O port C GPIO_B2BIZ Bit2 of General purpose I/O port B 30 KEYI12 I BD2XUM5 H Bit1 of key scan circuit input 31LXVDDPWR// VDD DC-DC pin 32 GND PWR / / Ground 33 GND PWR / / NMOS Ground 34 LXVCC PWR / / VCC DC-DC pin35 CE2- O NF_PAD H Ext. memory chip enable 2 36 CE1- O NF_PAD H Ext. memory chip enable 1 CE3-OH Ext. memory chip enable 337GPO_A3 O BD4CU/Bit3 of General purpose Output port A GPIO_G0BIZ Bit0 of General purpose I/O port G 38CE4- O TBD2C/ Ext. memory chip enable 4 39 VDD PWR / / Digital Core power40 RB- I BD4C H Nand Type flash Ready/Busy status input.GPO_A1OL Bit1 of General purpose Output port A 41 ICECK I BD4C/Clock input of DSUGPO_A2OL Bit2 of General purpose Output port A 42 ICEDO O BD4C/ Data output of DSUGPO_A0OBD4CM2Bit0 of General purpose Output port ACopyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.113/46 2007-3-2243 ICEDI I / Data input of DSU 44 ICEEN- I BD4C / DSU enable (active low) 45 ICERST- I BD4C / DSU reset (active low)GPIO_B4BIZ Bit4 of General purpose I/O port B 46KEYO0 O BD2XM5/ Bit0 of key scan circuit output GPIO_B5BIZ Bit5 of General purpose I/O port B 47KEYO1 O BD2XM5/ Bit1 of key scan circuit output 48 VCC PWR / / Digital power pad49 D7 BI NF_PAD L Bit7 of ext. memory data bus 50 D6 BI NF_PAD L Bit6 of ext. memory data bus 51 D5 BI NF_PAD L Bit5 of ext. memory data bus 52 D4 BI NF_PAD L Bit4 of ext. memory data bus 53 D3 BI NF_PAD L Bit3 of ext. memory data bus 54D2BINF_PADL Bit2 of ext. memory data bus 55 GND PWR / / Ground56 D1 BI NF_PAD L Bit1 of ext. memory data bus 57 D0 BI NF_PAD L Bit0 of ext. memory data bus 58 MWR- O NF_PAD H Ext. memory write strobe 59MRD-O NF_PAD H Ext. memory read strobe60 CLE O NF_PAD L Command latch enable for NAND flash61 ALE O NF_PAD L Address latch enable for NAND flash GPIO_C1 BI OD Bit1 of General purpose I/O port C I2C_SDAO/ I2C Serial data (Open drain) 62SIRQ- I SBD2X/ Ext. interrupt request input GPIO_C0BIOD Bit0 of General purpose I/O port C 63I2C_SCL OSBD2X / I2C serial clock (Open drain) 64 VDDPWR//Digital Core power3. Function Description3.1 Functional Block DiagramCopyright© Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.1 14/46 2007-3-22Copyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.115/46 2007-3-223.2 MCU Core3.2.1 MCU System Memory MappingEntendedMemory Space (MCU.A15=1)Internal Memory Space (MCU.A15=0)MCU 64KB Memory Space 0000H8000H FFFFHIf IA15=0 -> mapped to internal MemoryIf IA14=0, mapped to internal ZRAM （16K-64 ZRAM1）If IA14=1, mapped to internal DSP IPM/IDM when they are mapped into MCU memory space 3 extended address bits of a IO mapped register (Mapped at registered are used to decode the access to one of these memory blocks Bit 2 1 0 Accessed Block 0 0 0IPM low byteCopyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.116/46 2007-3-220 0 1 IPM middle byte 0 1 0 IPM high byte 0 1 1 ZRAM3 1 0 0 IDM low byte 1 0 1 IDM middle byte 1 1 0 IDM high byte 1 1 1ZRAM2 （B1+B2）Since IPM/IDM is mapped to MCU memory space per 8K block, IA13 is used toselect low/high block of 8K bytes in each 16K byte block.If IA15=1 -> Extended address bits are IO mapped at 01h and 02h for EMA15-28.EMA15-25 are output as address bus, while the EMA26-28 are used to decode CE0- ~ CE3-.CE0- is used to access boot code from ROM/MASK/NOR- type Flash.CE1- to CE3- can be configured to access ROM, or RAM or NAND-type Flash.ATJ2091N’s internal MCU MROM/SRAM memory mapping:1) (16K-64) byte ZRAM1(IA15=0,IA14=0): 0000H-3FBFH2) 6Kbyte ZRAM2 (IA15=0, IA14=1, IOReg05.[2:0]=111): 4000H-57FFH 3) (2K+256) byte URAM: 5800H-60FFH it has synchronization andasynchronism accessing mode.4) 12Kbyte BROM (IA15=1,Reg02=00h, Reg01=00h): 8000h-AFFFh 5) 21Kbyte TROM1 (IA15=1,Reg02=00h,Reg01=02h): 8000h-D3FFh 6) 17Kbyte TROM2 (IA15=1,Reg02=00h,Reg01=03h): 8000h-C400h 7) 6Kbyte ZRAM3 (IA15=0,IA14=1,IOReg05.[2:0]=011): 4000H-57FFHCopyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.117/46 2007-3-22ATJ2091N’s internal DSP IPM/IDM memory mapping:1) 16K x24bit IPM SRAM: 0000H-3FFFH 2) 16K x24bit IDM SRAM : 0000H-3FFFHATJ2091N’s internal DSP IPM/IDM memory mapping accessed by MCU:1) 16K x3 byte IPM SRAM: 4000H-7FFFH 2) 16K x3 byte IDM SRAM : 4000H-7FFFH(Hi/Mid/Low Byte Select and Mapping Mode controlled by IOReg05)DMA Mode Notes:1: When DMA1 and DMA2 are active, MCU will halt, and DMA1 and DMA2 have priority. 2: FLASHDMA or USB DMA is active, MCU will not halt.3.3 DSP24 CoreThis Core is a high performance, programmable Digital Signal Processor (DSP) suitable for a variety of digital audio compounding functions, such as Dolby AC-3 Surround, MPEG1 Layer3 which require large memory provided and the higher accuracy. RDSP24 is a general purpose DSP which can be appended various peripherals circuitry to implement some advanced signal processing algorithms for audio application.3.4 ZRAM1 and ZRAM2Input: A[13:0], ID[7:0], ZRAMRD-, ZRAMWR- Output: RD[7:0] (Tri-state)Speed: max read time 30 ns from ZRAMRD- going lowCopyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.118/46 2007-3-22Power consumption: stand by when both WR- and RD- are inactive, access current as low as possible.ZRAM2 is composed of B1 and B2, and each of them is 2k*8 byte SRAM. B1, B2 and ZRAM1(B0) can be operated independently. It has the following modes:1) MCU running at B0, while DMA[M] read B1 and DMA[N] write B2.B1 and B2 are viseversa. M=1, 2, 3, 4, 5, 6; N=1, 2, 3, 4, 5, 6; M!=N. 2) MCU running at B0+B1+B2 or B0+B1 or B0+B2. IPM and IDM Notes:Power consumption: stand by when both WR- and RD- are inactive, access current is as low as possible. PM/DM can be visited by MCU, DSP , DMA1, DMA2 and DMA5. When DSP visits low(high) bytes of 8Kbytes, MCU/DMA1,2,5 can visit high(low) bytes of 8Kbytes at the same time.3.5 USB2.0 SIE3.5.1 General DescriptionThe Actions USB2.0 device controller is fully compliant with the Universal Serial Bus 2.0 specification. In high-speed mode this device is capable of transmitting or receiving data up to 480Mbps.This high performance USB2.0 device controller integrates USB transceiver, SIE, and provides multifarious interfaces for generic MCU, RAM, ROM and DMA controller. So it is suitable for a variety of peripherals, such as: scanners, printers, mass storage devices, and digital cameras. It is designed to be a cost-effective USB total solution.Copyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.119/46 2007-3-223.5.2 Features¾ Fully compliant with USB Specification 2.0¾ Supports USB High Speed (480Mb/s) and Full Speed (12Mb/s) ¾ Supports Control, Bulk, Isochronous and Interrupt Transfers¾ Embedded USB high-speed Transceiver which complies with Inter UTMI ¾ Supports DMA interface (16-bit)¾ 2K bytes configurable FIFO for endpoints and provides double buffer to increasethroughput.¾ Supports USB remote wake-up feature¾ Software controlled connection to USB bus for re-enumerationCopyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.120/46 2007-3-223.5.3 USB Using Memory3.6 NAND Flash InterfaceATJ2091N can support NAND type flash from 32M to 4G bytes.3.7 Key Scan InterfaceKEY Scan Timing ：Cycle 1 Cycle 2KeyOut0KeyOut1KeyOut7T8TT=De-bouncing Time/8Key Scan TimingWhen key scan circuit is enabled, ATJ2091N will scan the keyboard periodically. It drives pin KEYOUTn [n=2…7] scan pulse in turn. When any key is pressed, the corresponding Keyout N will send out the scan pulse. When a key is pressed, pin Keyin N connecting the key will be found low level.There are 12 internal 8-bit registers for key value latch per scan. But only another one register (Key Scan Data Register) for MCU may access key value. Those 12 internal registers are mapped into this register, and an internal pointer is used to point to the current register to return scan data when read. Any IO write to this register will clear the internal register, and the pointer will increase by 1 and point to the next register after read is performed.3.8 LCD InterfaceIt is an ICON LCD control interface. We can operate 4*19 icons using the 10 registersCopyright© Actions Semiconductor Co., Ltd 2007. All rights reserved.Ver. 1.1 21/46 2007-3-22Copyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.122/46 2007-3-22from 0xc2 to 0xcb.ICON LCD 4*19OFF=V2OFF=V1ON OFF √ 32+1+1+1√√ 122√3 1.732Copyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.123/46 2007-3-223.9 General Purpose IO PortsATJ2091N has GPOA, GPIOB, GPIOC and GPIOG. They have different functions in different modes.GPIOF1(CE0S=H default)F2(key8*12)F3(ILCD)F4(CE0S=L default)MROM)GPO_A0 GPO_A0/ICEDI GPO_A1 GPO_A1/ICECK GPO_A2 GPO_A2/ICEDO GPO_A3 CE3-/GPOA3/MMC_CMDCE3-/GPOA3GPIO_B0 KEYI0/GPIO_B0 GPIO_B2 KEYI2/GPIO_B2KEYI2/GPIO_B2/SPI_SCKGPIO_B4 KEYO0/GPIO_B4 GPIO_B5 KEYO1/GPIO_B5 KEYO1/GPIO_B5/SPI_MOSIGPIO_C0 GPIO_C0 GPIO_C0/I2C_SCL GPIO_C1 GPIO_C1GPIO_C1/I2C_SDA/SIRQ-GPIO_C2 GPIO_C2 /MMC_SCLK GPIO_C2 GPIO_C2GPIO_G0 GPIO_G0GPIO_G0 GPIO_G0/SEG16 GPIO_G03.10 LOSC/RTCRTC is a 24-bits counter with the following functions; the clock source is LOSC/INTK32.¾ Time ¾ Alarm ¾ TimerCopyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.124/46 2007-3-22RTC Timer IRQ3.11 HOSC/PLLInput: A[7:0], DI[7:0], IOW-, IOR-, RESET- Output: HCK, PLLCK, CK48MHZATJ2091N supports 24Mhz crystal, and it is the system clock source.A low jitter PLL referenced to 24MHz is used to generate clock for DSP and for serial communication protocols such as USB, UART, etc. The clock used in serial communications is 48MHz. Another PLL referenced to 24MHz is used to generateCopyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.125/46 2007-3-2222.5792MHz for sample rate 44.1K/22.05KHz/11.025KHz and 24.576MHz for audio sequence of 48khz.3.12 PMU/DC-DCThe power management unit, PMU, includes:1. VDD (for core), VCC (for I/O) DC-DC PFM converter2. VDD regulator3. RC oscillator for one battery DC-DC startup4. IC oscillator for DC-DC controller5. Control management6. Voltage monitor7. External L & CParticular Suggestion: Both DCOP1/2 and internal NMOS are working at the beginningof power up. The unused line should be turned off after level off to reduce power consumption and interference.3.13 A/D, D/A and Headphone Driver3.13.1 D/A InterfaceATJ2091N’s internal D/A is an on-chip Sigma-Delta Modulator, a high performance D/A is composed of it and the D/A analog block referenced to 17.2. The D/A interface support 4-level play back FIFO (8 X 20-bit PCM data for L/R channel and variable sample rates, such as 48K/44.1K/32K/24K/22.05K/16K/12K/11.025K/8KHz. An on-chip PLL2 is used to generate 22.5792MHz from 24MHz to support 44.1K/22.05K/11.025KHz with 256XFS clock for over-sampling, while 24.576MHz supports 48K/32K/24K/16K/12K/8KHzCopyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.126/46 2007-3-22with 256XFS for over-sampling. D/A Block DiagramInternal D/A can drive earphone directly and the pin PAVCC need a bypass capacitor about 100uF to eliminate the “PENG” when D/A is powered on or off. D/A includes an analog mixer, reference to the ADDA block diagram.Power Amplifier Diagram3.13.2 A/D InterfaceThe internal microphone amplifier has gain for recording. The VMIC pin is the power supply (2.2V) for microphone.The audio A/D is a 18 bits sigma delta Analog-to-Digital Converter. Its input source can be selected from MIC amplifier or external FM or line-in, and it has two FIFO.BATTERY A/D is used for battery voltage monitoring, and the voltage range is 0.7~2.2V.LRADC1 works as line controller, and the voltage range is 0.7~2.2V. When LRADC1 PAD voltage<2.0V, it will send an interrupt request to MCU to reduce MCU’s dealing time to line controller.Copyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.127/46 2007-3-224. Electrical Characteristics4.1 Absolute Maximum RatingsParameter SymbolTypicalRatingUnitVDD 1.6 -0.3~2.0 V Supply voltage VCC 3.0 -0.3~3.6 V Input voltage V I -0.3~3.6 V Storage temperature T stg 25-65~150 ℃Note:1. T O = 25℃（Operating Temperature ）2. Do not short-circuit two or more output pins simultaneously.3. If even one of the above parameters exceeds the absolute maximum ratings even momentarily, the quality of the product may be degraded. The absolute maximum ratings, therefore, specify the value exceeding which the product may be physically damaged. Use the product well within these ratings.4. The specifications and conditions shown in DC Characteristics and AC characteristics are the ranges for normal operation and quality assurance of the product.4.2 CapacitanceCopyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.128/46 2007-3-22Parameter Symbol Condition MIN. MAX. UnitInput capacitance C I 15 pF I/O capacitanceC IOf C = 1 MHz Unmeasured pins returned to 0 V15 pFNote: T O = 25℃, VCC = 0 V.4.3 DC CharacteristicsParameter SymbolConditionMIN.TYP .MAX.UnitHigh-level outputvoltage V OHI OH = -2 mA2.4VLow-level outputvoltageV OLI OL = 2 mA0.4VHigh-level input voltage V IH 0.6*VCC VCC+0.6 VLow-level input voltage V IL -0.3 0.4*VCC V Input leakage current I LIVCC = 3.6 V, VI = VCC, 0 V +5 uA Tri-State leakagecurrentI LOVCC = 3.6 V, VI = VCC, 0 V+3 uA I drive1 GPOA0,GPOA1,GPOA24mAI drive2GPIO_B2, GPIO_B4,GPIO_B510 mAGPIO DriveI drive3 OtherGPIO 2 mASupply Current （One battery mode ）I VDDIn Full speed mode(MCU run 24MHz ininternal SRAM, DSP run 36MIPS)13.5 14.5 18 mACopyright © Actions Semiconductor Co., Ltd 2007. All rights reserved. Ver. 1.129/46 2007-3-22In Standby mode 30 45 60 uAIn Full speed mode (MCU run 24MHz ininternal SRAM, DSPrun 36MIPS) 0.15 0.21mAI VCCIn Standby mode506070uANOTES:1. T o = -10 to +70, VDD = ℃ 1.6 V, VCC = 3.0 V2. I VDD is a total power supply current for the 1.6 V power supply. I VDD is applied to theLOGIC and PLL and OSC block.3. I VCC is a total power supply current for the 3.0 V power supply. I VCC is applied to the USB, IO and AD block.4.4 AC CharacteristicsT o = -10 to +70℃4.4.1 AC Test Input Waveform4.4.2 AC Test Output Measuring PointsAll Input Pins。

A1_Datacom：来自 IEEE 802.3 和 OIF-CEI 的 (1)

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• •
This ends up being ~1.8x the data rate. OIF-CEI (28Gbps NRZ) calls out 40GHz electrical BW (BT response). The 28GBaud PAM4 (2X the signal rate) translates to ~48GHz acquisition BW. Remember this is a rule of thumb. Some specs are very precise here.
City
CFP8
Router
400GBASE-SR16 400GBASE-FR8 400GBASE-DR4
Backplane, chip to module
400G-PM-QPSK
Blade Servers
CDAUI-8 CEI-56G-VSR-PAM4 CEI-56G-LR-PAM4
TEKTRONIX 400G PAM4 TECHNOLOGY UPDATE
•
•
TEKTRONIX 400G PAM4 TECHNOLOGY UPDl Communications
Channel Distance Lane Rate Multiplex Signaling rate Modulation Format 400GBASE-SR16 100m 400GBASE-DR4 500m 400GBASE-FR8 2Km 400GBASE-LR8 10Km 16 lane x 16 parallel 25.78G Baud NRZ 25.78Gbps MMF 4 lane x 106Gbps 8 lanes x 53.12Gbps 4 parallel SMF 1 SMF 8 λ WDM 53.12G Baud PAM4 26.56G Baud PAM4 26.56G Baud PAM4

RTL8189ES模块规格书(RL-SM02B-8189ES)

尊敬的客户：请收到我公司样品承认书三日内传首页，谢谢！
Байду номын сангаас
SDIO PRODUCT SPECIFICATION
IEEE 802.11 b/g/n 2.4GHz 1T1R WiFi Module
RL-SM02B -RTL8189ES Single Module
Version 1.0
General Description
客户栏 Customer 核准Approve 审核Auditing 承认Admit
RL-SM02B -RTL8189ES
供应商栏 Provider 核准Approve 审核Auditing 承认Admit
客户名称：公司地址：电话：传真：联系人： E-mail:
供方名称：HK NATER TECH LIMITED 公司地址：深圳市宝安区宝民二路贤基大厦2楼电话：0755-61522172/13510620050 传真：0755-61522171 联系人：王先生 E-mail：hsdgood@
Features
General 32-pin QFN CMOS MAC, Baseband PHY, and RF in a single chip for IEEE 802.11b/g/n compatible WLAN Complete 802.11n solution for 2.4GHz band 72.2Mbps receive PHY rate and 72.2Mbps transmit PHY rate using 20MHz bandwidth 150Mbps receive PHY rate and 150Mbps transmit PHY rate using 40MHz bandwidth Compatible with 802.11n specification Backward compatible with 802.11b/g devices while operating in 802.11n mode Host Interface Complies with SDIO 1.1/ 2.0/ 3.0 for WLAN with clock rate up to 100MHz GSPI interface for configurable endian for WLAN Standards Supported IEEE 802.11b/g/n compatible WLAN IEEE 802.11e QoS Enhancement (WMM) 802.11i (WPA, WPA2). Open, shared key, and pair-wise key authentication services Selectable receiver FIR filters Programmable scaling in transmitter and receiver to trade quantization noise against increased probability of clipping Fast receiver Automatic Gain Control (AGC) WLAN MAC Features Frame aggregation for increased MAC efficiency (A-MSDU, A-MPDU) Low latency immediate High-Throughput Block Acknowledgement (HT-BA) PHY-level spoofing to enhance legacy compatibility Power saving mechanism Channel management and co-existence Transmit Opportunity (TXOP) Short Inter-Frame Space (SIFS) bursting for higher multimedia bandwidth WLAN PHY Features IEEE 802.11n OFDM One Transmit and one Receive path (1T1R) 20MHz and 40MHz bandwidth transmission Short Guard Interval (400ns) DSSS with DBPSK and DQPSK, CCK modulation with long and short preamble OFDM with BPSK, QPSK, 16QAM, and 64QAM modulation. Convolutional Coding Rate: 1/2, 2/3, 3/4, and 5/6 Maximum data rate 54Mbps in 802.11g and 150Mbps in 802.11n Switch diversity for DSSS/CCK Hardware antenna diversity in per packet base On-chip ADC and DAC Peripheral Interfaces General Purpose Input/Output (8 pins) One configurable LED pins

Zigbee System-on-Chip

16High Frequency ElectronicsHigh Frequency DesignZIGBEE SoC DESIGNIEEE 802.15.4 PHY are summarized in Table 1.Figure 1 · IEEE 802.15.4 and Zigbee working model.Figure 2 · Zigbee network topologies.From January 2006 High Frequency Electronics Copyright © 2006 Summit Technical Mediastripped away. 18High Frequency ElectronicsFigure 3 · SoC content mapping. 20High Frequency ElectronicsFigure 5 · RF and analog part of the CC2430.step I/Q-up-conversion,which provides excellent perfor-mance and is extremely flexible with respect to supportingrelatively high transmission rates and modulation for-mats of both constant and non-constant envelope nature.The CC2430 transmitter employs a direct-conversionmodulator.The device buffers the supplied data in a 128byte TX FIFO,and the preamble and start of frame delim-iter (SFD) are generated in HW.The bit mapping andmodulation are performed according to the IEEE 802.15.4specification.The data bit stream is coded into pre-defined4-bit symbols where each of the 16 symbols consists a 22High Frequency ElectronicsMAC HW SupportSaving processing bandwidth for network and appli-cation operations,the SoC design should relieve the mC for MAC-related timing critical operations that could be handled more effectively by dedicated circuitries. Therefore,the CC2430 integrates a significant set of the IEEE 802.15.4 MAC requirements to off-load the micro-controller.These include:• CSMA-CA coprocessor• Automatic preamble generator• Synchronisation word insertion/detection• CRC-16 computation and checking over the MAC pay-load• Clear Channel Assessment• Energy detection / digital RSSI• Link Quality IndicationAn embedded coprocessor handles the encryption/ decryption operations employing the AES (Advanced Encryption Standard) algorithm with 128-bit keys required by I EEE 802.15.4 MAC security,the ZigBee™network layer and the application layer.This dedicated AES coprocessor allows encryption/decryption to be per-formed with minimum mC usage.MCU and MemoryThe processing capability for execution of protocol stack,network and application SW of the CC2430 includes an enhanced version of the industry standard 8-bit 8051 microcontroller core with three different memo-ry access buses, a debug interface and an 18-input extended interrupt unit.The enhanced 8051 core uses the standard 8051 instruction set but with typically 8×the performance of a standard 8051 core due to faster execu-tion times and by eliminating wasted bus states.The CC2430 includes a direct memory access (DMA) controller,which can be used to relieve the 8051 MCU core of moving data operations,thus achieving high over-all performance with good power efficiency.The DMA con-troller can move data from a peripheral unit to memory with minimum mC intervention.At the heart of the sys-tem,a memory arbitrator connects the mC and the DMA controller with the physical memories and all peripherals through an SFR bus.There are 8K bytes of static RAM available on the CC2430.The on-chip Flash block of either 32K,64K or 128K bytes provides in-circuit programmable non-volatile pro-gram memory and is primarily intended to hold program code for the protocol stack,network and user application. Peripherals and Supporting FeaturesWell-defined SoC’s must also allow easy and flexible implementation of user-defined features.The CC2430integrates a wide range of peripherals for this purpose.Interrupts are useful for interfering with the normal program flow in case of important external or internal events that need immediate attention.Interrupt control together with incorporated sleep modes are very useful for saving power.The CC2430 interrupt controller ser-vices a total of 18 interrupt sources,divided into six inter-rupt groups,each of which is associated with one of four interrupt priorities.The debug interface on the CC2430 implements a pro-prietary two-wire serial interface that is used for in-cir-cuit debugging.Through this debug interface it is possible to perform an erasure of the entire flash memory,stop and start execution of the user program,execute supplied instructions on the 8051 core,set code breakpoints,and single step through instructions in the ing these techniques,it is possible to elegantly perform in-circuit debugging and external flash programming.An I/O-controller is responsible for flexible assignment and reliable control of the 21 general-purpose I/O pins.The CC2430 integrates four oscillators: a high-fre-quency 32 MHz crystal oscillator,a 16 MHz high-frequen-cy RC-oscillator,an optional crystal oscillator,and an optional RC oscillator both at 32.768 kHz.The CC2430 uses one internal system clock,either by the 32 MHz crys-tal oscillator or the 16 MHz RC-oscillator.The choice of oscillator allows a trade-off between high-accuracy in the case of the crystal oscillator and low power consumption when the high-frequency RC oscillator is used.The sys-tem clock also feeds all 8051 peripherals,and operation of the RF transceiver requires active 32 MHz XOSC.Four timers are available on the CC2430:one MAC timer,one general 16-bit timer,and two general 8-bit timers.The MAC 16-bit timer is mainly used to provide timing for I EEE 802.15.4 CSMA-CA algorithms and for general timekeeping in the 802.15.4 MAC layer.The other three timers support typical timer/counter functions such as input capture,output compare and PWM functions.CC2430 has a built-in watchdog timer providing recovery mechanism in case of an out-of-control micro-processor,for example,due to software upset.To provide stable and robust operation,the CC2430 includes a power-on-reset and brown-out detector to protect the memory contents during supply voltage variations and provide correct initialisation during power-up.The CC2430 also includes an eight channel,8-14 bit delta-sigma ADC,a real time clock with 32.768 kHz crys-tal oscillator and two programmable USARTs for mas-ter/slave SPI or UART operation.Tailored for Cost, Performance and PowerThe CC2430 device [3] surpasses the I EEE 802.15.4 specification and delivers excellent RF performance in terms of selectivity and sensitivity for better co-existence24High Frequency Electronics。

JESD47I中文版

JEDECSTANDARDStress-Test-Driven Qualification of Integrated CircuitsIC集成电路压力测试考核JESD47I(R evision of JESD47H.01, April 2011)JULY 2012JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONNOTICEJEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and approvedby the JEDEC legal counsel.JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is tobe used either domestically or internationally.JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adoptingthe JEDEC standards or publications.The information included in JEDEC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard.No claims to be in conformance with this standard may be made unless all requirements stated inthe standard are met.Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or refer to under Standards and Documents for alternative contact information.Published by©JEDEC Solid State Technology Association 20123103 North 10th Street Suite240 SouthArlington, V A 22201-2107This document may be downloaded free of charge; however JEDEC retains thecopyright on this material. By downloading this file the individual agrees not tocharge for or resell the resulting material.PRICE: Contact JEDECPrinted in the U.S.A.All rights reservedJEDEC Standard No. 47IPage 5 5.5 Device qualification requirements (cont’d)STRESS DRIVEN QUALIFICATION OF INTEGRATED CIRCUITSIC集成电路压力测试考核(From JEDEC Board Ballot, JCB-12-24, formulated under the cognizance of the JC14.3 Subcommittee on Silicon Devices Reliability Qualification and Monitoring.)通过JEDEC委员会JCB-12-24号投票，在JC14.3硅晶圆器件可靠性考核和监控小组委员会审理后系统地阐述和制定1 Scope 范围This standard describes a baseline set of acceptance tests for use in qualifying electronic components as new products, a product family, or as products in a process which is being changed.这个文档描述了用于考核新产品、同族器件或工艺变更的可接受的基准测试标准These tests are capable of stimulating and precipitating semiconductor device and packaging failures. The objective is to precipitate failures in an accelerated manner compared to use conditions. Failure Rate projections usually require larger sample sizes than are called out in qualification testing. For guidance on projecting failure rates, refer to JESD85 Methods for Calculating Failure Rates in Units of FITs. This qualification standard is aimed at a generic qualification for a range of use conditions, but is not applicable at extreme use conditions such as military applications, automotive under-the-hood applications, or uncontrolled avionics environments, nor does it address 2nd level reliability considerations, which are addressed in JEP150. Where specific use conditions are established, qualification testing tailored to meet those specific requirements can be developed, using JESD94 that will result in a better optimization of resources.这些测试用于加速和诱发半导体器件和封装的失效。

DMD20操作手册

调制解调器是卫星通信网传输设备中一个关键环节，处于地面通信设备与发射设备的上下变频器之间，在很大程度上决定着传输信道的质量。

指标：支持BPSK，QPSK，8PSK，16QAM 调制解调数据速率：4.8 Kbps 到20 Mbps50 MHz 到180 MHz 每Hz 可调（L_band: 950 到2050 MHz.)多种接口类型可选: V.35, RS449, G.703,RS232,ASI/RS422, ASI/LVDS, DVB/M2,Ehter Net,HSSI等IDR方式：1 发射端设置：a. 快速配置: Modulator> STRAPE CODE ,选择032 并确认.b. MOD IF 设置: Modulator > IF发射频率: > Frequency(MHZ), 按系统要求设置.此处为Lband 频率上行频率：>UPLINK FREQ(MHz),按系统要求设置.此处为实际频率发射功率: > Power, 按系统要求设置并调整.发射载波: > Carrier , 可控制载波.(最后一步)频谱反转: > Spectrum ,按系统要求设置.一般为Normal.调制方式: > Modulation,检查是否为QPSK.频谱包络: > Spectrl Msk, 设为INTELSAT 0.35功率补偿：>COMPENSATION, 一般设为0.0c. ODU-BUC 设置:FSK通信: > FSK COMMS，忽略。

本振频率：>LO FREQ(MHz), 本系统为15450 MHZ本振位置: > OSC SIDE BAND, 本系统为HIGH SIDEBAND BUC本振: > 10 MHZ BUC REF, 设为ENABLED.BUC电压: > BUC VOLTAGE,设为ENABLED.低压门限: > LOW ALARM THRSH, 设为40.0 Volts.高压门限: > HI ALARM THRSH,设为52.0 Volts.低电门限: > LOW ALARM THRSH, 设为0.00 AMPS.高电门限: > HI ALARM THRSH,设为 2.50 AMPS.发射延迟: > CARR DLY(SEC),设为000.d. MOD Data设置: Modulator > DATA速率设置: > Data Rate, 自动设为2048Kbps.符号率: > Symbol Rate, MODEM自动计算.码率设置: > INNER FEC, 检查是否为VIT3/4 .差分控制: > Diff Coding,检查是否为ENABLE.扰码选择: > Scrambler Sel,检查是否为V35（IESS）.扰码控制: > Scrambler Ctrl,检查是否为ENABLE.帧类型: > SAT Framing,检查是否为IDR 96K.地面帧: > TERR FRAMING，忽略数据反转: > Data Polarity按系统要求设置. 一般为INVERT NONE ESC报头: > ESC OVERHEAD, 设为VOICE X2e. 发射数据端口设置: Interface > TX Set up时钟代号: > Circuit ID, 可忽略.接口类型: > Terr Interface, 选择G.703.E1.Unbal 并确认.发射时钟: > TX Clk Src, 检查是否为SCTE .时钟极性: > TX Clk Pol,按系统要求设置,一般设为Auto内时钟源: > SCT CLK SRC, 一般为Internal2 接收端设置:a.快速配置: Modulator> STRAP CODE ,选择032 并确认.b. DEMOD IF 设置: Demodulator > Demod IF接收频率: > Frequency(MHZ), 按系统要求设置.此处为Lband 频率下行频率：>DWLINK FREQ(MHz),按系统要求设置.此处为实际频率频谱反转: > Spectrum ,按系统要求设置. 一般为NORMAL.解调方式: > Modulation,检查是否为QPSK.频谱包络: > Spectrl Msk, 设为INTELSAT.扫描带宽: >Sweep Range, 一般设为25 Khz.扫描延时: > Swp Delay, 一般设为0000.0 sec.重捕带宽: > ReAcq Sweep,一般设为500 Hz临频功率: > ADJ CARRIER PWR,一般设为NORMAL快速捕获: > FAST ACQUISITION,一般设为ENABLED输入门限: > INPUT LVL THRSH, 一般设为-90.0EBNO门限: > EB/NO ALARM, 一般设为0.1 dB.本振频率：>LO FREQ(MHz), 本系统为11300 MHZ本振位置: > OSC SIDE BAND, 本系统为LOW SIDEBANDLNB本振: > 10 MHZ BUC REF, 设为ENABLED.电压选择：> VOLTAGE SELECT, 设为15 VoltsLNB电压: > LNB VOLTAGE,设为ENABLED.低压门限: > LOW ALARM THRSH, 设为10.0 Volts.高压门限: > HI ALARM THRSH,设为22.0 Volts.低电门限: > LOW ALARM THRSH, 设为0.00 AMPS.高电门限: > HI ALARM THRSH,设为 2.50 AMPS.d. DEMOD Data设置: Demodulator > Demod Data速率设置: > Data Rate, 自动设为2048 Kbps.符号率: > Symb Rate, MODEM自动计算.码率设置: > INNER FEC, 检查是否为VIT3/4 .差分控制: > Diff Coding, 检查是否为ENABLED.解扰选择: > Scrambler Sel, 检查是否为V35（IESS）.解扰控制: > Scrambler Ctrl, 检查是否为Enable .帧类型: > SAT Framing, 检查是否为IDR.地面帧: > 忽略数据反转: > Data Polarity按系统要求设置. 一般为INVERT NONE ESC报头: > ESC OVERHEAD, 设为VOICE X2e. 接收数据端口设置: Interface > RX Set up时钟代号: > Circuit ID, 可忽略.接口类型: > TERR Interface, 选择G.703.E1.Unbal 并确认.缓冲大小: > Buff Size, 按系统要求设置,一般设为32 毫秒.缓冲时钟: > Buffer CLK SRC > SCT 3 of 3. (此设置为特殊设置,见后页)时钟极性: > Clk Polarity,按系统要求设置,一般设为Normalf. 接收数据端口设置: .缓冲时钟: > Buff Clk SRC, SCT 3 of 3 (时钟总数)SCT 当前工作时钟, 3 为该时钟(SCT)的时钟级别解释: DMD20 支持多种缓存器时钟方式,远端站采用3种时钟. EXT B NC, RX SAT和SCT. 其中EXT BNC优先级别最高, RX SAT其次, SCT为最低.设置时,1.按ENTER键进入, 移动光标至时钟总数位置,将时钟总数更改为3, 然后按ENTER 确认.2.按ENTER键进入,右移光标至时钟级别处(即第一个数字处), 然后上下移动光标,直至EXT BNC 出现, 右移光标至时钟级别处, 按1, 然后按ENTER确认.3.按ENTER键进入,右移光标至时钟级别处, 然后上下移动光标,直至RX SAT出现, 右移光标至时钟级别处, 按2, 然后按ENTER确认.4.按ENTER键进入,右移光标至时钟级别处, 然后上下移动光标,直至SCT 出现, 右移光标至时钟级别处, 按3, 然后按ENTER确认.5.按ENTER键进入, 右移光标至时钟级别处, 然后上下移动光标, 检查时钟设置是否正确, 如不正确,重新进行上述2-4 步操作. 见下页正确的时钟设置示意.g. 接收数据端口设置: .正确时钟设置应该为:SCTE 1 of 3RX SAT 2 of 3SCT 3 of 3后向告警屏蔽:ALARMS > BACKWARD ALARMS> IDR1 SAT CNTRL, 设为FRC OFF(TX=PASS)> IDR2 SAT CNTRL, 设为FRC OFF(TX=PASS)> IDR3 SAT CNTRL, 设为FRC OFF(TX=PASS)> IDR4 SAT CNTRL, 设为FRC OFF(TX=PASS配置参数存储与调用: System > Config将出现: Current > Config2DMD20内部有10个配置存储器, 分别为Config1到Config10, 还有一个就是Current. Current存储的是当前DMD20运行所用的配置参数. Config1到Config5可存储不同的配置, 方便用户进行DMD20的快速配置. 并可进行配置间的复制. 例:A. 将当前的配置存储于Config2中:进入上述菜单后选择两边的参数表直至出现:Current > Config2按ENTER键后即可完成操作.B.将Config2的参数调出使用:进入上述菜单后选择两边的参数表直至出现: Config2 > Current按ENTER键后即可完成操作.DMD20设备故障判断测试手段环路测试-主要用于检测MODEM误码测试-主要用于检测信道质量CW –用于信道测试获取告警信息告警信息读取常见故障:接收告警数据接口部分TX 和RX Minor Alarm复帧同步告警MrfSync Alarm环路测试设置:进入TEST > LOOPBACKS按测试目的选择测试方式. 可选:Tx Terr - 发射本地环回模式(主要测试手段)Rx Terr - 接收本地环回模式(主要测试手段)Tx/Rx Terr - 同时打开上述两个测试模式IF - 中频环回模式None –关闭测试, MODEM正常工作.发射本地环回模式(主要测试手段):数据由接口进入后直接由输出口送出. 主要用于与地面接口的联接测试.接收本地环回模式:本地MODEM将接收到的数据经基带数据处理后由调制器发回.可用于卫星信道测试.中频环回模式(主要测试手段):数据经调制器直接输入本地解调器后输出.用于测试本地MODEM的功能.发射/接收本地环回模式:本地MODEM将接收到的数据经基带处理后由调制器发回.同时本地数据由接口进入后直接由输出口送出.发射/接收基带环回模式:本地MODEM将接收到的数据直接由调制器发回.同时本地数据由接口进入后经基带处理后由本地输出口送出.误码测试设置与结果检查:测试设置: 进入TEST > 2047 Test (测试前需确认端口无任何告警)按测试目的选择测试方式. 可选:Tx - 打开调制器误码测试序列Rx - 打开解调器误玛测试功能Tx/Rx - 同时打开上述两个测试模式None –关闭测试, MODEM正常工作进入TEST > 2047 Insert Errors设置插入误码的个数(0000-9999), 确认将插入到发射误码序结果检查: 进入TEST > 2047 Errors ( 2047 Test RX 打开时有效)显示接收到的误码个数.进入TEST > 2047 BER ( 2047 Test RX 打开时有效)显示测试的误码率BER进入TEST > Clear 2047确认后将清除误码记录,并重新开始误码测试记录误码测试方法建议:1. 本地上下行信道测试:打开2047 TX/RX, 设置Demodulator接收本地Modulator所发射的载波.2. 本地加远端上下行信道测试:A. 打开本地2047 TX/RX, 将远端MODEM设置为接收本地环回或接收基带环回模式. 检查本地MODEM的2047测试结果.B. 打开本地和远端MODEM的2047 TX/RX, 检查两个MODEM的2 047结果.2047误码测试重要提示:1. 不能在G.703.U.E1下测试:如接口为G.703.U.E1则时钟为外时钟SCTE,且不可更改,将影响测试效果.2. 不能在DROP&INSERT模式下测试:此时的数据传输会因成帧受到影响. 如需测试DROP&INSERT情况下的信道质量,可采取外挂误码仪的方法进行测试.3. 建议测试方法: 将接口类型改为V.35, 使用内时钟SCT. Interface > TX Set up > Tx Type > V.35Interface > TX Set up > Tx Clock > SCTInterface > TX D&I > DisableInterface > RX Set up > Rx Type > V.35Interface > RX D&I > DisableCW测试设置:(纯载波测试, 用于功率和极化的检查. )测试设置: 进入TEST > CarrierCW - MODEM将发射纯载波Normal –MODEM将发射正常载波常见故障：Modem不能锁定接收载波1、接收异常解决办法：检查线缆连接2、接收载波电平过低或过高解决办法：检查线缆连接，ODU下行增益设置正确与否。

(完整版)QPSK调制与解调在MATLAB平台上的实现

QPSK 调制与解调在 MATLAB 平台上的实现李悦QPSK 即四进制移向键控(Quaternary Phase Shift Keyi ng ,它利用载波的四种不同相位来表示数字信息，由于每一种载波相位代表两个比特信息，因此每个四进制码元可以用两个二进制码元的组合来表示。

两个二进制码元中的前一个码元用a 表示，后一个码元用 b 表示。

QPSK 信号可以看作两个载波正交 2PSK 信号的合成，下图表示QPSK 正交调制器。

由QPSK 信号的调制可知，对它的解调可以采用与 2PSK 信号类似的解调方法进行解调。

解调原理图如下所示，同相支路和正交支路分别采用相干解调方式解调，得到l(t)和Q(t)，经过抽样判决和并/串交换器，将上下支路得到的并行数据恢复成串行数据载波输入磯波振沏—移相输出输入滤波器抽样刿决变换低通.抽样判决输出cos g低通滤液器位定时b%调相法clear all close all t=[-1:0.01:7-0.01];tt=le ngth(t);x1=o nes(1,800);for i=1:ttif (t(i)>=-1 & t(i)<=1) | (t(i)>=5& t(i)<=7); x1(i)=1;else x1(i)=-1;endend t仁[0:0.01:8-0.01]; t2=0:0.01:7-0.01; t3=-1:0.01:7.1-0.01; t4=0:0.01:8.1-0.01;tt1=le ngth(t1); x2=o nes(1,800); for i=1:tt1if (t1(i)>=0 & t1(i)<=2) | (t1(i)>=4& t1(i)<=8); x2(i)=1;else x2(i)=-1;endend f=0:0.1:1;xrc=0.5+0.5*cos(pi*f);y1=c on v(x1,xrc)/5.5;y2=c on v(x2,xrc)/5.5;n0=randn( size(t2));f1=1;i=x1.*cos(2*pi*f1*t);q=x2.*si n( 2*pi*f1*t1);I=i(101:800);Q=q(1:700);QPSK=sqrt(1/2).*l+sqrt(1/2).*Q;QPSK_n=(sqrt(1/2).*l+sqrt(1/2).*Q)+n0;n 1=ra ndn( size(t2)); i_rc=y1.*cos(2*pi*f1*t3); q_rc=y2.*si n(2*pi*f1*t4);I_rc=i_rc(101:800);Q_rc=q_rc(1:700);QPSK_rc=(sqrt(1/2).*I_rc+sqrt(1/2).*Q_rc);QPSK_rc_n1=QPSK_rc+ n1;figure(1)subplot(4,1,1);plot(t3,i_rc);axis([-1 8 -1 1]);ylabel('a 序列'); subplot(4,1,2);plot(t4,q_rc);axis([-1 8 -1 1]);ylabel('b 序列'); subplot(4,1,3);plot(t2,QPSK_rc);axis([-1 8 -1 1]);ylabel('合成序列');subplot(4,1,4);plot(t2,QPSK_rc_n 1);axis([-1 8 -1 1]);ylabel(' 加入噪声'); 效果图：%设定T=1,加入高斯噪声clear allclose all%调制bit_in = randin t(1e3, 1, [0 1]);bit」=bit_i n(1:2:1e3);bit_Q = bit_i n(2:2:1e3);data_I = -2*bit_l+1;data_Q = -2*bit_Q+1;data_I1=repmat(data_I',20,1);data_Q 1=repmat(data_Q',20,1);for i=1:1e4data_I2(i)=data_I1(i);data_Q2(i)=data_Q1(i);en d;f=0:0.1:1;xrc=0.5+0.5*cos(pi*f);data_I2_rc=c on v(data_l2,xrc)/5.5;data_Q2_rc=co nv(data_Q2,xrc)/5.5;f1=1;t1=0:0.1:1e3+0.9;n0=ran d(size(t1));I_rc=data_I2_rc.*cos(2*pi*f1*t1);Q_rc=data_Q2_rc.*si n(2*pi*f1*t1);QPSK_rc=(sqrt(1/2).*I_rc+sqrt(1/2).*Q_rc); QPSK_rc_n0=QPSK_rc+ n0;%解调I_demo=QPSK_rc_ n0.*cos(2*pi*f1*t1);Q_demo=QPSK_rc_n0.*si n(2*pi*f1*t1);%低通滤波I_recover=c on v(I_demo,xrc);Q_recover=c on v(Q_demo,xrc);l=l_recover(11:10010);Q=Q_recover(11:10010);t2=0:0.05:1e3-0.05;t3=0:0.1:1e3-0.1;%抽样判决data_recover=[];for i=1:20:10000data_recover=[data_recover l(i:1:i+19) Q(i:1:i+19)]; en d;bit_recover=[];for i=1:20:20000if sum(data_recover(i:i+19))>0 data_recover_a(i:i+19)=1; bit_recover=[bit_recover 1];elsedata_recover_a(i:i+19)=-1; bit_recover=[bit_recover -1];endenderror=0;dd = -2*bit_i n+1;ddd=[dd'];ddd1=repmat(ddd,20,1);for i=1:2e4ddd2(i)=ddd1(i);endfor i=1:1e3if bit_recover(i)~=ddd(i) error=error+1;endend p=error/1000;figure(1) subplot(2,1,1);plot(t2,ddd2);axis([0 100 -2 2]);title(' 原序列');subplot(2,1,2);plot(t2,data_recover_a);axis([0 100 -2 2]);title('解调后序列’);效果图:%设定T=1,不加噪声clear allclose all%调制bit_in = randin t(1e3, 1, [0 1]);bit」=bit_i n(1:2:1e3);bit_Q = bit_i n(2:2:1e3);data_I = -2*bit_l+1;data_Q = -2*bit_Q+1;data_I1=repmat(data_I',20,1);data_Q 1=repmat(data_Q',20,1);for i=1:1e4data_I2(i)=data_I1(i);data_Q2(i)=data_Q1(i);en d;t=0:0.1:1e3-0.1;f=0:0.1:1;xrc=0.5+0.5*cos(pi*f);data_I2_rc=c on v(data_l2,xrc)/5.5;data_Q2_rc=co nv(data_Q2,xrc)/5.5;f1=1;t1=0:0.1:1e3+0.9;I_rc=data_I2_rc.*cos(2*pi*f1*t1);Q_rc=data_Q2_rc.*si n(2*pi*f1*t1);QPSK_rc=(sqrt(1/2).*I_rc+sqrt(1/2).*Q_rc);%解调I_demo=QPSK_rc.*cos(2*pi*f1*t1);Q_demo=QPSK_rc.*si n(2*pi*f1*t1);I_recover=c on v(I_demo,xrc);Q_recover=c on v(Q_demo,xrc);I=I_recover(11:10010);Q=Q_recover(11:10010);t2=0:0.05:1e3-0.05;t3=0:0.1:1e3-0.1;data_recover=[];for i=1:20:10000data_recover=[data_recover l(i:1:i+19) Q(i:1:i+19)];en d;ddd = -2*bit_i n+1;ddd 1= repmat(ddd',10,1);for i=1:1e4ddd2(i)=ddd1(i);endfigure(1)subplot(4,1,1);plot(t3,l);axis([0 20 -6 6]);subplot(4,1,2);plot(t3,Q);axis([0 20 -6 6]);subplot(4,1,3);plot(t2,data_recover);axis([0 20 -6 6]);subplot(4,1,4);plot(t,ddd2);axis([0 20 -6 6]);效果图：20% QPSK误码率分析SNRi ndB仁0:2:10;SNRi ndB2=0:0.1:10;for i=1:le ngth(SNRi ndB1)[pb,ps]=cm_sm32(SNR in dB1(i));smld_bit_err_prb(i)=pb;smld_symbol_err_prb(i)=ps;en d;for i=1:le ngth(SNR in dB2)SNR=exp(SNRi ndB2(i)*log(10)/10);theo_err_prb(i)=Qfu nct(sqrt(2*SNR));en d;title('QPSK误码率分析');semilogy(SNRi ndB1,smld_bit_err_prb,'*');axis([0 10 10e-8 1]);hold on;% semilogy(SNRindB1,smld_symbol_err_prb,'o'); semilogy(SNR in dB2,theo_err_prb);legend('仿真比特误码率','理论比特误码率'); hold off;fun ctio n[y]=Qfu nct(x) y=(1/2)*erfc(x/sqrt(2));fun ctio n[ pb,ps]=cm_sm32(SNRi ndB) N=10000; E=1;SNR=10A(SNRi ndB/10);sgma=sqrt(E/SNR)/2;s00=[1 0];s0仁[0 1];si 仁[-1 0];s10=[0 -1];for i=1:Ntemp=ra nd;if (temp<0.25)dsource1(i)=0;dsource2(i)=0;elseif (temp<0.5) dsource1(i)=0;dsource2(i)=1;elseif (temp<0.75)dsource1(i)=1;dsource2(i)=0;elsedsource1(i)=1;dsource2(i)=1;en d;en d;numo fsymbolerror=0;num ofbiterror=0;for i=1:Nn=sgma*ra ndn( size(s00));if((dsource1(i)==0)&(dsource2(i)==0))r=s00+n;elseif((dsource1(i)==0)&(dsource2(i)==1))r=s01+ n;elseif((dsource1(i)==1)&(dsource2(i)==0))r=s10+n;elser=s11+ n;en d;c00=dot(r,s00);c0仁dot(r,s01);c10=dot(r,s10);c11=dot(r,s11);c_max=max([c00 c01 c10 c11]);if (c00==c_max)decis 1=0 ;decis2=0;elseif(c01==c_max)decis 1=0 ;decis2=1;elseif(c10==c_max)decis 1= 1;decis2=0;elsedecis1=1;decis2=1;en d;symbolerror=0; if(decis1~=dsource1(i)) numofbiterror= num ofbiterror+1; symbolerror=1;en d;if(decis2~=dsource2(i))num ofbiterror= num ofbiterror+1;symbolerror=1;en d;if(symbolerror==1)numo fsymbolerror =numo fsymbolerror+1; en d;en d;ps=numo fsymbolerror/N;pb=num ofbiterror/(2*N);效果图：。

RTL8821CU双频wifi蓝牙4.2二合一USB接口模块

Product SpecificationRevision V1.0Date2017-4-15Model Name BL-M8821CU1ProductName IEEE802.11b/g/n/ac(1T1R)USB WLANAnd BT ModuleBilian Approve FieldEngineer QC SalesCustomer Approve FieldEngineer QC Manufactory PurchasingShenzhen Bilian Electronic Co.，LtdAddress:No268,Fuqian Rd.,JuTang Community,Guanlan Town,Baoan District,Shenzhen,518110,PRCHomepage:Table of ContentsRevision History (1)1.Introduction (1)1.1General Description (1)1.2Features (1)1.3Applications (2)2.Functional Block Diagram (2)3.Product Technical Specifications (2)3.1General Specifications (2)3.2DC Power Consumption (3)3.3RF Specifications (4)4.Pin Assignments (7)5.Application Information (8)5.1Supported Platform (8)5.2Typical Application Circuit (8)6.Mechanical Specifications (10)7.Others (11)7.1Package Information (11)7.2Storage Temperature and Humidity (11)7.3Recommended Reflow Profile (11)Revision HistoryDate DocumentRevisionProductRevisionDescription2017/4/60.1V1.0Preliminary release2017/4/15V1.0V1.0Ver1.0release1.Introduction1.1General DescriptionBL-M8821CU1product is a highly integrated single-chip802.11a/b/g/n/ac1T1R USB2.0WLAN controller It combines a WLAN MAC,a1T1R capable WLAN baseband,BT Protocol(LM,LL and LE),BT Baseband,modem, and WLAN/BT RF in a single chip.The module provides a complete solution for ahigh-performance wireless LAN and Bluetooth device.The BT controller supports BT4.2system and compatibles Bluetooth2.1+EDR.Figure1Top View Figure2Bottom ViewNote:The above picturesare for reference only1.2Features●Operating Frequencies:2.4~2.4835GHz and5.15~5.85GHz●Host Interface is USB2.0for WLAN and BT controller●IEEE Standards:IEEE802.11a/b/g/n/ac●Wireless data rate can reach up to433.3Mbps●Bluetooth Low Energy Support●Connect to external antenna through the half hole●Power Supply:3.3V±0.2V1.3Applications●MID●IP Camera●STB●Smart TV●E-book●Other devices which need to be supported by wireless network2.Functional Block DiagramFigure3BL-M8821CU1block diagram 3.Product Technical Specifications3.1General SpecificationsItem DescriptionProduct Name BL-M8821CU1Main Chip RTL8821CU-CGHost Interface USB2.0IEEE Standards IEEE802.11a/b/g/n/acOperating Frequencies 2.4GHz~2.4835GHz/5.15GHz~5.85GHz Modulation WiFi:802.11b:CCK,DQPSK,DBPSK802.11a/g:64-QAM,16-QAM,QPSK,BPSK802.11n:64-QAM,16-QAM,QPSK,BPSK802.11ac:256-QAM,64-QAM,16-QAM,QPSK,BPSKBT:8DPSK,π/4DQPSK,GFSKWorking Mode Infrastructure,Ad-HocWireless Data Rate WiFi:802.11b:1,2,5.5,11Mbps802.11a/g:6,9,12,18,24,36,48,54Mbps802.11n:HT20reach up to144.4Mbps,HT40reach up to300Mbps802.11ac:VHT20reach up to173.3Mbps,VHT40reach up to239Mbps,VHT80 reach up to433.3MbpsBT:1Mbps for Basic Rate2,3Mbps for Enhanced Date RateRx Sensitivity-96dBm(Min)TX Power18.5dBm(Max)Antenna Type Connect to external antenna through the IPEX connectorDimension(L*W*H)13.0*12.2*1.5mm(L*W*H)，Tolerance:±0.15mmPower Supply 3.3V±0.2VPower Consumption Standby192mA@3.3V(Max)TX mode908mA@3.3V(Max)Clock Source40MHzWorking Temperature-10°C to+50°CStorage Temperature-40°C to+70°CESD CAUTION:Although this module is designed to be as robust as possible,Electrostatic Discharge(ESD) can damage this module.It must be protected from ESD at all times and handled under the protection of ESD.3.2DC Power ConsumptionVcc=5V，T a=25°C，unit:mASupply current Typ.MaxStandby(RF disabled)82104802.11b1Mbps11MbpsSupply current Typ.Max.Typ.Max.TX mode375404350420Rxmode8010480104 802.11g6Mbps54Mbps Supply current Typ.Max.Typ.Max. TX mode325388240376 Rxmode8511286116 802.11n HT20MCS0MCS7 Supply current Typ.Max.Typ.Max. TX mode320380239372 Rxmode8711288116 802.11n HT40MCS0MCS7 Supply current Typ.Max.Typ.Max. TX mode286352215360 Rxmode8911690120 802.11a6Mbps54Mbps Supply current Typ.Max.Typ.Max. TX mode340420270380 Rxmode9012091124 802.11n HT40(5G)MCS0MCS7 Supply current Typ.Max.Typ.Max. TX mode320392240384 Rxmode9212493128 802.11ac MCS0MCS9 Supply current Typ.Max.Typ.Max. TX mode300380240388 Rxmode1041321061443.3RF SpecificationsTX Power 2.4G:802.11b:17±1.5dBm802.11g/11n-HT20:15±1.5dBm 802.11n-HT40:15±1.5dBm5G:802.11a/11n-HT20:15±1.5dBm 802.11n-HT40:14±1.5dBm 802.11ac:13±1.5dBmTX Constellation Error(EVM)2.4G:802.11b:<-22dB@11Mbps802.11g:<-28dB@54Mbps 802.11n-HT20:<-28dB@72.2Mbps 802.11n-HT40:<-28dB@150Mbps 5G:802.11a:<-28dB@54Mbps 802.11n-HT20:<-28dB@72.2Mbps 802.11n-HT40:<-28dB@150Mbps 802.11ac:<-33dB@433MbpsReceiver Minimum Input Sensitivity@PER 1Mbps:-96dBm@PER<8%; 11Mbps:-90dBm@PER<8%; 54Mbps:-72dBm@PER<10%; 150Mbps:-69dBm@PER<10%; 433Mbps:-59dBm@PER<10%;RFTest Report PathA2.4GMode Rate(Mbps)Power(dBm)EVM(dB)Sensitivity(dBm)CH1CH7CH13CH1CH7CH13CH1CH7CH1311b 118.9318.3719.22-33.81-37.73-37.84-96-96-96 1117.1916.7916.92-26.74-27.27-24.98-90-90-9011g 917.8318.0517.69-26.19-24.04-24.94-91-91-91 5415.7215.4415.48-34.08-32.80-31.81-75-75-75Mode Rate(Mbps)Power(dBm)EVM(dB)Sensitivity(dBm)CH3CH7CH11CH3CH7CH11CH3CH7CH1111n HT40MCS016.7817.2816.87-30.13-27.60-27.78-89-89-89 MCS714.9714.9914.99-34.46-33.68-34.61-70-70-70BT Rate(Mbps)Power(dBm)Sensitivity(dBm)(LE mode) 05075373839DH11 5.94 5.35 5.31-77-77-77 3DH53 5.28 5.08 5.07-73-73-73RFTest ReportPathA5GMod Rate(Power(dBm)EVM(dB)Sensitivity(dBm)e Mbps)CH36CH100CH140CH161CH36CH100CH140CH161CH36CH100CH140CH16111a 915.5616.0216.2216.08-24.32-26.25-24.10-24.93-90-90-90-90 5414.2914.8614.6014.48-29.62-31.00-30.43-30.92-74-74-74-74Mod e Rate(Mbps)Power(dBm)EVM(dB)Sensitivity(dBm)CH38CH102CH142CH159CH38CH102CH142CH159CH38CH102CH142CH15911n 40MCS016.7516.6316.7616.99-25.09-27.21-26.30-25.59-88-87-87-87 MCS714.4414.4814.3314.74-30.65-31.13-30.45-31.74-69-69-69-69Mod e Rate(Mbps)Power(dBm)EVM(dB)Sensitivity(dBm)CH42CH106CH138CH155CH42CH106CH138CH155CH42CH106CH138CH15511ac MCS015.9915.4715.2115.50-27.71-27.64-28.39-28.33-84-84-84-84 MCS913.7313.3413.2913.40-35.50-32.91-36.04-35.52-60-59-59-594.Pin AssignmentsFigure4Pin Assignments(Top view)The following signal type codes are used in the tables: I:Input O:OutputO/D:Open Drain P:Power PinPin No：Pin Name Type Description1GND P Ground2RF_0I/O5G WIFI and BT ANT3RF_1I/O2G WIFI ANT4GND P Ground5、6、7、8NC/Floating(Don’t connected to groundO Bluetooth device to wake up HOST9BT_WAKE_HOSTI HOST to wake up Bluetooth device10HOST_WAKE_BT11VIN P VDD3.3VPower Supply12USB_DM I/O USB Transmitter/Receiver Differential Pair13USB_DP I/O USB Transmitter/Receiver Differential Pair14GND P ground153DD_SYNC I/O PCM_OUT/GPIO116WL_DIS I WIFI DISABLE（Low potential）17BT_DIS I BT DISABLE（Low potential）18CHIP_EN I High asserting for use/Low asserting resetI HOST to wake up WIFI19HST_WAKE_WLO WIFI to wake up HOST20WL_WAKE_HST21WPS/WPS Switch22LED/External LED Control5.Application Information5.1Supported PlatformOperating System CPU Framework Driver LINUX(Kernel2.6.24~3.19.3)ARM,MIPSII,X86Platform Enable5.2Typical Application CircuitLED CircuitWPS CircuitRF reference circuitFigure5Typical application circuit NOTE：1、RF trace need to keep50ohm impedance.2、USB differential pair need to keep90ohm impedance.3、C110uF closed to Module pin114、Reserved0R between Module pin16pin17and Host6.Mechanical SpecificationsModule dimension:Typical(L*W*H):13.0mm*12.2mm*1.5mm Tolerance:+/-0.15mmFigure6Module dimension7.Others7.1Package InformationFigure7Package Information7.2Storage Temperature and Humidity1.Storage Condition:Moisture barrier bag must be stored under30℃,humidity under85%RH.The calculated shelf life for the dry packed product shall be a12months from the bag seal date.Humidity indicator cards must be blue,<30%.2.Products require baking before mounting if humidity indicator cards reads>30%temp<30℃, humidity<70%RH,over96hours.Baking condition:125℃,12hours.Baking times:1time.7.3Recommended Reflow ProfileReflow soldering shall be done according to the solder reflow profile,Typical Solder Reflow Profile is illustrated in Figures8.The peak temperature is245℃.Figure8Typical Solder Reflow Profile。

RTL8723DU模块(RL-UM02WBS-8723DU-V1.0)规格书

Module Specification
Module Name Module Description
RL-UM02WBS-8723DU-V1.0 IEEE 802.11b/g/n (1T1R) WiFi+BT4.2/2.1 V1.0 USB Interface
Reversion Date
Nater Approve Field Engineer Cruz.Zeng QC Mike.Liu Sales Lingo.Wang 13510620050
WLAN MAC Features Host Interface n Frame aggregation for increased MAC n Complies with USB2.0 for WLAN and efficiency (A-MSDU, A-MPDU) BT controller n Low latency immediate n USB Multi-Function for both BT High-Throughput Block (USB function 0) and WLAN (USB Acknowledgement (HT-BA) function 1) n PHY-level spoofing to enhance legacy n USB LPM and USB Selective Suspend compatibility supported n Power saving mechanism n Multi MACID support with Fast WLAN Controller Channel switch n CMOS MAC, Baseband PHY, and RF n Channel management and co-existence in a single chip for 802.11b/g/n n Transmit Opportunity (TXOP) Short compatible WLAN Inter-Frame Space (SIFS) bursting for n Integrated Balun and DPDT higher multimedia bandwidth n Complete 802.11n solution for 2.4GHz n WiFi Direct supports wireless peer to band peer applications n 72.2Mbps receive PHY rate and n Supports Wake-On-WLAN via Magic 72.2Mbps transmit PHY rate using Packets and Wake-up frame 20MHz bandwidth n Support S3/S4 AES/TKIP group key n 150Mbps receive PHY rate and update 150Mbps transmit PHY rate using n Support Win8 Network List Offload 40MHz bandwidth n Support TCP/UDP/IP checksum offload n Backward compatible with 802.11b/g devices while operating in 802.11n mode n I 802.11b/g/n compatible WLAN n 802.11e QoS Enhancement (WMM) WLAN PHY Features n 802.11n OFDM n One Transmit and one Receive path (1T1R) Integrated MCU to execute Bluetooth protocol stack n Supports all packet types in basic rate and enhanced data rate n

Skyworks Si2160C 数字电视解调器.pdf_1718750811.0801241说明书

D I SE Q C DescriptionThe Si2160C integrates digital demodulators for all first and second generation DVB standards (DVB-T/C/C2/S/S2 and S2X) in a single advanced CMOS die. Leveraging Skyworks' proven digital demodulation architecture, the Si2160C achieves excellent reception performance for each media while significantly minimizing front-end design complexity, cost, and power dissipation. Connecting the Si2160C to a hybrid TV tuner or digital only tuner, such as Skyworks' Si217x/5x/4x devices, results in a high-performance and cost optimized TV or STB front-end solution.Skyworks' internally developed DVB-C2 demodulator can accept a standard IF (36 MHz) or low-IF input (differential) and support all modes specified by the DVB-C2 standard. The main features of the DVB-C2 mode are 4096-QAM, 6 or 8 MHz bandwidth,management of notch insertion (broadband and narrowband), and support of multiple data slices and PLPs.DVB-T, DVB-C2/C and DVB-S2/S demodulators are next-generation enhanced versions of proven and broadly-used Skyworks’ Si2169/68/67/66/64/62/60 devices.The satellite reception allows demodulating widespread DVB-S,DIRECTV™ (DSS), DVB-S2, DIRECTV™ (AMC) legacy standards, and new Part II of DVB-S2 (S2X) satellite broadcast standard. A zero-IF interface (differential) allows for a seamless connection to market proven satellite silicon tuners. Si2160C embeds DiSEqC TM 2.0 LNB interface for satellite dish control and an equalizer to compensate for echoes in long cable feeds from the antenna to the satellite tuner input.Features-Pin-to-pin compatible with all Si216x/8x single demods family -API compatible with all single and dual demods families -DVB-C2 (ETSI EN 302 769)16-QAM to 4096-QAM OFDM demodulation-DVB-S2 (ETSI EN 302 307-1 V1.4.1)QPSK/8PSK demodulator-DVB-S2X (ETSI EN302 307-2 V1.1.1)QPSK/8PSK, 8/16/32APSKdemodulator Roll-off factors from 0.05 to 0.35-DVB-T (ETSI EN 300 744)OFDM demodulator and enhanced FEC decoder NorDig Unified 2.5 and D-Book 8 compliant-DVB-C (ETSI EN 300 429) and ITU-T J.83 Annex A/B/CQAM demodulator and FEC decoder 1 to 7.2MSymbol/s-DVB-S and DSS supportedQPSK demodulator and enhanced FEC decoder- 1 to 45MSymbol/s for all satellite standards (<40 MSps in 32APSK)-LDPC and BCH FEC decoding for C2 and S2 standards -I 2C serial bus interfaces (master and host)-Firmware control (embedded ROM/NVM)-Upgradeable with patch download via fast SPI or I 2C (broadcast mode supported)-Flexible TS output interface (serial, parallel, and slave)-DiSEqC TM 2.0 interface and Unicable TM support for satelliteSkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************•Selected Electrical Specifications(T A =–10 to 75°C)Parameter Test Condition Min Typ Max Unit GeneralInput clock reference 4—30MHz Supported XTAL frequency 16—30MHz Total power consumptionDVB-T 1—182—mW DVB-C22—327—mW DVB-C 3—142—mW DVB-S24—421—mW DVB-S 5—230—mW Thermal resistance 2 layer PCB —35—°C/W 4 layer PCB—23—°C/W Power Supplies V DD _VCORE 1.14 1.20 1.30V V DD _VANA 3.00 3.30 3.60V V DD _VIO3.003.303.60VNotes:1. Test conditions: 8MHz, 8K FFT, 64-QAM, parallel TS.2. Test conditions: 4096-QAM, CR =5/6, GI =1/128, C/N =34dB (at picture failure).3. Test conditions: 6.9Mbaud, 256-QAM, parallel TS.4. Test conditions: 32Mbaud, CR =3/5, 8PSK, pilots On, parallel TS, C/N at picture failure.5. Test conditions: 30Mbaud, CR =7/8, parallel TS, at QEF: BER =2 x 10–4.Pin AssignmentsSelection GuidePart Number DescriptionSi2160-C60-GMDVB-C2/S2/S2X/T/C/S Digital TV demodulator, 7x7mm QFN-48G NM P _D I S E Q C _O U M P _S C L _H O S D I S E Q C _C M S D A _H O S T S _V A D I S E Q C _I GND VDD_VIO S _D A T A [7]E S E T B T A L _I /C L K _I NT A L _ON D D D _V C O R ED D _V A N AD D RN DG P I O _S _E R R /G P I O _1V D D _V C O R V D D _V I P _DP _C。

LPC2364中文资料

1.General descriptionThe LPC2364/66/68microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time emulation that combines the microcontroller with up to 512kB of embedded high-speed ﬂash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For criticalperformance in interrupt service routines and DSP algorithms,this increases performance up to 30% over Thumb mode. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30% with minimal performance penalty.The LPC2364/66/68 are ideal for multi-purpose serial communication applications. They incorporate a 10/100 Ethernet Media Access Controller (MAC), USB full speed device with 4kB of endpoint RAM, four UARTs, two CAN channels, an SPI interface, twoSynchronous Serial Ports (SSP), three I 2C interfaces, and an I 2S interface. This blend of serial communications interfaces combined with an on-chip 4MHz internal oscillator,SRAM of up to 32 kB, 16kB SRAM for Ethernet, 8kB SRAM for USB and general purpose use, together with 2kB battery powered SRAM make these devices very well suited for communication gateways and protocol converters. Various 32-bit timers, an improved 10-bit ADC, 10-bit DAC, one PWM unit, a CAN control unit, and up to 70 fast GPIO lines with up to 12 edge or level sensitive external interrupt pins make these microcontrollers particularly suitable for industrial control and medical systems.2.FeaturesI ARM7TDMI-S processor, running at up to 72MHz.I Up to 512kB on-chip ﬂash program memory with In-System Programming (ISP) and In-Application Programming (IAP) capabilities. Flash program memory is on the ARM local bus for high performance CPU access.I 8/32kB of SRAM on the ARM local bus for high performance CPU access.I 16kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.I 8kB SRAM for general purpose DMA use also accessible by the USB.I Dual Advanced High-performance Bus (AHB) system that provides for simultaneous Ethernet DMA, USB DMA, and program execution from on-chip ﬂash with nocontention between those functions. A bus bridge allows the Ethernet DMA to access the other AHB subsystem.I Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.I General Purpose AHB DMA controller (GPDMA)that can be used with the SSP serial interfaces, the I 2S port, and the Secure Digital/MultiMediaCard (SD/MMC) card port,as well as for memory-to-memory transfers.LPC2364/66/68Single-chip 16-bit/32-bit microcontrollers; up to 512 kB ﬂash with ISP/IAP , Ethernet, USB 2.0, CAN, and 10-bit ADC/DACRev. 02 — 1 October 2007Preliminary data sheetI Serial interfaces:N Ethernet MAC with associated DMA controller. These functions reside on an independent AHB bus.N USB 2.0 full-speed device with on-chip PHY and associated DMA controller.N Four UARTs with fractional baud rate generation,one with modem control I/O,one with IrDA support, all with FIFO.N CAN controller with two channels.N SPI controller.N Two SSP controllers,with FIFO and multi-protocol capabilities.One is an alternate for the SPI port,sharing its interrupt and pins.These can be used with the GPDMA controller.N Three I2C-bus interfaces (one with open-drain and two with standard port pins).N I2S (Inter-IC Sound) interface for digital audio input or output. It can be used with the GPDMA.I Other peripherals:N SD/MMC memory card interface (LPC2368 only).N70 general purpose I/O pins with conﬁgurable pull-up/down resistors.N10-bit ADC with input multiplexing among 6 pins.N10-bit DAC.N Four general purpose timers/counters with a total of 8 capture inputs and 10 compare outputs. Each timer block has an external count input.N One PWM/timer block with support for three-phase motor control. The PWM has two external count inputs.N Real-Time Clock (RTC) with separate power pin, clock source can be the RTC oscillator or the APB clock.N2kB SRAM powered from the RTC power pin,allowing data to be stored when the rest of the chip is powered off.N WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock.I Standard ARM test/debug interface for compatibility with existing tools.I Emulation trace module supports real-time trace.I Single 3.3V power supply (3.0V to 3.6V).I Four reduced power modes: idle, sleep, power-down, and deep power-down.I Four external interrupt inputs conﬁgurable as edge/level sensitive. All pins on PORT0and PORT2 can be used as edge sensitive interrupt sources.I Processor wake-up from Power-down mode via any interrupt able to operate duringPower-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet wake-up interrupt).I Two independent power domains allow ﬁne tuning of power consumption based onneeded features.I Each peripheral has its own clock divider for further power saving.I Brownout detect with separate thresholds for interrupt and forced reset.I On-chip power-on reset.I On-chip crystal oscillator with an operating range of 1MHz to 24MHz.I4MHz internal RC oscillator trimmed to 1% accuracy that can optionally be used as the system clock. When used as the CPU clock, does not allow CAN and USB to run.I On-chip PLL allows CPU operation up to the maximum CPU rate without the need for a high frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the RTC oscillator.I Versatile pin function selections allow more possibilities for using on-chip peripheral functions.3.ApplicationsI Industrial control I Medical systems I Protocol converter ICommunications4.Ordering information4.1Ordering optionsTable 1.Ordering informationType numberPackage NameDescriptionVersion LPC2364FBD100LQFP100plastic low proﬁle quad ﬂat package; 100 leads; body 14× 14× 1.4 mmSOT407-1LPC2366FBD100LPC2368FBD100Table 2.Ordering optionsType numberFlash(kB)SRAM (kB)Ether netUSB device +4kB FIFO SD/MMC GP DMA Channels Temprange LocalbusEthernet buffers GP/USBRTC Total CAN ADC DAC LPC2364FBD1001288168234RMIIyesnoyes261−40°C to+85°C LPC2366FBD10025632168258RMII yes no yes 261−40°C to+85°C LPC2368FBD10051232168258RMII yes yes yes 261−40°C to+85°C5.Block diagram(1)LPC2368 only.Fig 1.LPC2364/66/68 block diagramPWM1ARM7TDMI-SPLL EINT3 to EINT0FLASHP3, P4P0, P1, P2,LEGACY GPI/O 52 PINS TOT AL P0, P1SCK, SCK0MOSI, MOSI0SSEL, SSEL1SCK1MOSI1MIS01SSEL1SCL0, SCL1, SCL2I2SRX_CLK I2STX_CLK I2SRX_WS I2STX_WS 6 × AD0RTCX1RTCX2MCICLK, MCIPWR RXD0, RXD2, RXD3TXD1RXD1RD1, RD2TD1, TD2CAN1, CAN2USB_D+, USB_D −XTAL1TCK TDOEXTIN0XTAL2RESETTRST TDI TMS HIGH-SPEEDGPI/O 70 PINS TOTALLPC2364/66/688/32 kB SRAM128/256/512 kB FLASHINTERNAL CONTROLLERS TEST/DEBUG INTERFACEE M U L A T I O N T R A C E M O D U L Etrace signalsAHB BRIDGEAHB BRIDGEETHERNET MAC WITH DMA16 kB SRAMMASTER PORT AHB TO APB BRIDGE SLAVE PORTsystem clockSYSTEM FUNCTIONS INTERNAL RC OSCILLATORV DDAV DD(3V3)VREFV SSA , V SSVECTORED INTERRUPT CONTROLLER8 kB SRAMUSB WITH 4 kB RAM AND DMAGP DMA CONTROLLERI 2S INTERFACESPI, SSP0 INTERFACEI2SRX_SDA I2STX_SDA MISO, MISO0SSP1 INTERFACESD/MMC CARD INTERFACE (1)MCICMD,MCIDAT[3:0]TXD0, TXD2, TXD3UART0, UART2, UART3UART1DTR1, RTS1DSR1, CTS1, DCD1,RI1I 2C0, I 2C1, I 2C2SDA0, SDA1, SDA2EXTERNAL INTERRUPTS CAPTURE/COMPARE TIMER0/TIMER1/TIMER2/TIMER3A/D CONVERTERD/A CONVERTER 2 kB BATTERY RAMRTCOSCILLATORREAL-TIME CLOCKWATCHDOG TIMER SYSTEM CONTROL2 × CAP0/CAP1/CAP2/CAP34 × MAT2,2 × MA T0/MA T1/MAT36 × PWM12 × PCAP1AOUT VBA TAHB TO APB BRIDGESRAM RMII(8)V BUSUSB_CONNECT USB_UP_LED002aac566P0, P2power domain 2AHB2AHB1power domain 2V DD(DCDC)(3V3)6.Pinning information6.1Pinning6.2Pin descriptionFig 2.LPC2364/66/68 pinningLPC2364FBD100LPC2366FBD100LPC2368FBD1007526501007651125002aac576Table 3.Pin descriptionSymbol PinType DescriptionP0[0] to P0[31]I/OPort 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 0 pins depends upon the pin function selected via the Pin Connect block. Pins 12, 13, 14, and 31 of this port are not available.P0[0]/RD1/TXD3/SDA146[1]I/O P0[0] —General purpose digital input/output pin.I RD1 —CAN1 receiver input.O TXD3 —T ransmitter output for UART3.I/OSDA1 —I 2C1 data input/output (this is not an open-drain pin).P0[1]/TD1/RXD3/SCL147[1]I/O P0[1] —General purpose digital input/output pin.O TD1 —CAN1 transmitter output.I RXD3 —Receiver input for UART3.I/OSCL1 —I 2C1 clock input/output (this is not an open-drain pin).P0[2]/TXD098[1]I/O P0[2] —General purpose digital input/output pin.O TXD0 —T ransmitter output for UART0.P0[3]/RXD099[1]I/O P0[3] —General purpose digital input/output pin.I RXD0 —Receiver input for UART0.P0[4]/I2SRX_CLK/RD2/CAP2[0]81[1]I/O P0[4] —General purpose digital input/output pin.I/O I2SRX_CLK —Receive Clock. It is driven by the master and received by the slave.Corresponds to the signal SCK in the I 2S-bus speciﬁcation .I RD2 —CAN2 receiver input.ICAP2[0] —Capture input for Timer 2, channel 0.P0[5]/I2SRX_WS/ TD2/CAP2[1]80[1]I/O P0[5] —General purpose digital input/output pin.I/O I2SRX_WS —Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus speciﬁcation.O TD2 —CAN2 transmitter output.I CAP2[1] —Capture input for Timer2, channel 1.P0[6]/I2SRX_SDA/ SSEL1/MA T2[0]79[1]I/O P0[6] —General purpose digital input/output pin.I/O I2SRX_SDA —Receive data. It is driven by the transmitter and read by the receiver.Corresponds to the signal SD in the I2S-bus speciﬁcation.I/O SSEL1 —Slave Select for SSP1.O MAT2[0] —Match output for Timer2, channel 0.P0[7]/I2STX_CLK/ SCK1/MA T2[1]78[1]I/O P0[7] —General purpose digital input/output pin.I/O I2STX_CLK —Transmit Clock. It is driven by the master and received by the slave.Corresponds to the signal SCK in the I2S-bus speciﬁcation.I/O SCK1 —Serial Clock for SSP1.O MAT2[1] —Match output for Timer2, channel 1.P0[8]/I2STX_WS/ MISO1/MA T2[2]77[1]I/O P0[8] —General purpose digital input/output pin.I/O I2STX_WS —Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus speciﬁcation.I/O MISO1 —Master In Slave Out for SSP1.O MAT2[2] —Match output for Timer2, channel 2.P0[9]/I2STX_SDA/ MOSI1/MA T2[3]76[1]I/O P0[9] —General purpose digital input/output pin.I/O I2STX_SDA —Transmit data. It is driven by the transmitter and read by the receiver.Corresponds to the signal SD in the I2S-bus speciﬁcation.I/O MOSI1 —Master Out Slave In for SSP1.O MAT2[3] —Match output for Timer2, channel 3.P0[10]/TXD2/ SDA2/MA T3[0]48[1]I/O P0[10] —General purpose digital input/output pin.O TXD2 —Transmitter output for UART2.I/O SDA2 —I2C2 data input/output (this is not an open-drain pin).O MAT3[0] —Match output for Timer3, channel 0.P0[11]/RXD2/ SCL2/MAT3[1]49[1]I/O P0[11] —General purpose digital input/output pin.I RXD2 —Receiver input for UART2.I/O SCL2 —I2C2 clock input/output (this is not an open-drain pin).O MAT3[1] —Match output for Timer3, channel 1.P0[15]/TXD1/ SCK0/SCK 62[1]I/O P0[15] —General purpose digital input/output pin.O TXD1 —Transmitter output for UART1.I/O SCK0 —Serial clock for SSP0.I/O SCK —Serial clock for SPI.P0[16]/RXD1/ SSEL0/SSEL 63[1]I/O P0[16] —General purpose digital input/output pin.I RXD1 —Receiver input for UART1.I/O SSEL0 —Slave Select for SSP0.I/O SSEL —Slave Select for SPI.Table 3.Pin description …continuedSymbol Pin Type DescriptionP0[17]/CTS1/ MISO0/MISO 61[1]I/O P0[17] —General purpose digital input/output pin.I CTS1 —Clear to Send input for UART1.I/O MISO0 —Master In Slave Out for SS1I/O MISO —Master In Slave Out for SPI.P0[18]/DCD1/ MOSI0/MOSI 60[1]I/O P0[18] —General purpose digital input/output pin.I DCD1 —Data Carrier Detect input for UART1.I/O MOSI0 —Master Out Slave In for SSP0.I/O MOSI —Master Out Slave In for SPI.P0[19]/DSR1/ MCICLK/SDA159[1]I/O P0[19] —General purpose digital input/output pin.I DSR1 —Data Set Ready input for UART1.O MCICLK —Clock output line for SD/MMC interface. (LPC2368 only)I/O SDA1 —I2C1 data input/output (this is not an open-drain pin).P0[20]/DTR1/ MCICMD/SCL158[1]I/O P0[20] —General purpose digital input/output pin.O DTR1 —Data T erminal Ready output for UART1.I MCICMD —Command line for SD/MMC interface. (LPC2368 only)I/O SCL1 —I2C1 clock input/output (this is not an open-drain pin).P0[21]/RI1/ MCIPWR/RD157[1]I/O P0[21] —General purpose digital input/output pin.I RI1 —Ring Indicator input for UART1.O MCIPWR —Power Supply Enable for external SD/MMC power supply. (LPC2368 only)I RD1 —CAN1 receiver input.P0[22]/RTS1/ MCIDAT0/TD156[1]I/O P0[22] —General purpose digital input/output pin.O RTS1 —Request to Send output for UART1.O MCIDAT0 —Data line for SD/MMC interface. (LPC2368 only)O TD1 —CAN1 transmitter output.P0[23]/AD0[0]/ I2SRX_CLK/ CAP3[0]9[2]I/O P0[23] —General purpose digital input/output pin.I AD0[0] —A/D converter 0, input 0.I/O I2SRX_CLK —Receive Clock. It is driven by the master and received by the slave.Corresponds to the signal SCK in the I2S-bus speciﬁcation.I CAP3[0] —Capture input for Timer3, channel 0.P0[24]/AD0[1]/ I2SRX_WS/ CAP3[1]8[2]I/O P0[24] —General purpose digital input/output pin.I AD0[1] —A/D converter 0, input 1.I/O I2SRX_WS —Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus speciﬁcation.I CAP3[1] —Capture input for Timer3, channel 1.P0[25]/AD0[2]/ I2SRX_SDA/ TXD37[2]I/O P0[25] —General purpose digital input/output pin.I AD0[2] —A/D converter 0, input 2.I/O I2SRX_SDA —Receive data. It is driven by the transmitter and read by the receiver.Corresponds to the signal SD in the I2S-bus speciﬁcation.O TXD3 —T ransmitter output for UART3.Table 3.Pin description …continuedSymbol Pin Type DescriptionP0[26]/AD0[3]/ AOUT/RXD36[3]I/O P0[26] —General purpose digital input/output pin.I AD0[3] —A/D converter 0, input 3.O AOUT —D/A converter output.I RXD3 —Receiver input for UART3.P0[27]/SDA025[4]I/O P0[27] —General purpose digital input/output pin.I/O SDA0 —I2C0 data input/output. Open-drain output (for I2C-bus compliance).P0[28]/SCL024[4]I/O P0[28] —General purpose digital input/output pin.I/O SCL0 —I2C0 clock input/output. Open-drain output (for I2C-bus compliance).P0[29]/USB_D+29[5]I/O P0[29] —General purpose digital input/output pin.I/O USB_D+ —USB bidirectional D+ line.P0[30]/USB_D−30[5]I/O P0[30] —General purpose digital input/output pin.I/O USB_D− —USB bidirectional D− line.P1[0] to P1[31]I/O Port 1: Port 1 is a 32-bit I/O port with individual direction controls for each bit. Theoperation of port 1 pins depends upon the pin function selected via the Pin Connectblock. Pins 2, 3, 5, 6, 7, 11, 12, and 13 of this port are not available.P1[0]/ ENET_TXD095[1]I/O P1[0] —General purpose digital input/output pin.O ENET_TXD0 —Ethernet transmit data 0.P1[1]/ ENET_TXD194[1]I/O P1[1] —General purpose digital input/output pin.O ENET_TXD1 —Ethernet transmit data 1.P1[4]/ENET_TX_EN 93[1]I/O P1[4] —General purpose digital input/output pin.O ENET_TX_EN —Ethernet transmit data enable.P1[8]/ ENET_CRS 92[1]I/O P1[8] —General purpose digital input/output pin.I ENET_CRS —Ethernet carrier sense.P1[9]/ENET_RXD091[1]I/O P1[9] —General purpose digital input/output pin.I ENET_RXD0 —Ethernet receive data.P1[10]/ ENET_RXD190[1]I/O P1[10] —General purpose digital input/output pin.I ENET_RXD1 —Ethernet receive data.P1[14]/ENET_RX_ER 89[1]I/O P1[14] —General purpose digital input/output pin.I ENET_RX_ER —Ethernet receive error.P1[15]/ENET_REF_CLK 88[1]I/O P1[15] —General purpose digital input/output pin.I ENET_REF_CLK/ENET_RX_CLK —Ethernet receiver clock.P1[16]/ ENET_MDC 87[1]I/O P1[16] —General purpose digital input/output pin.I ENET_MDC —Ethernet MIIM clock.P1[17]/ ENET_MDIO 86[1]I/O P1[17] —General purpose digital input/output pin.I/O ENET_MDIO —Ethernet MI data input and output.P1[18]/USB_UP_LED/ PWM1[1]/ CAP1[0]32[1]I/O P1[18] —General purpose digital input/output pin.O USB_UP_LED —USB GoodLink LED indicator. It is LOW when device is conﬁgured (non-control endpoints enabled). It is HIGH when the device is not conﬁgured orduring global suspend.O PWM1[1] —Pulse Width Modulator 1, channel 1 output.I CAP1[0] —Capture input for Timer1, channel 0.Table 3.Pin description …continuedSymbol Pin Type DescriptionP1[19]/CAP1[1]33[1]I/O P1[19] —General purpose digital input/output pin.I CAP1[1] —Capture input for Timer 1, channel 1.P1[20]/PWM1[2]/SCK034[1]I/O P1[20] —General purpose digital input/output pin.O PWM1[2] —Pulse Width Modulator 1, channel 2 output.I/OSCK0 —Serial clock for SSP0.P1[21]/PWM1[3]/SSEL035[1]I/O P1[21] —General purpose digital input/output pin.O PWM1[3] —Pulse Width Modulator 1, channel 3 output.I/OSSEL0 —Slave Select for SSP0.P1[22]/MA T1[0]36[1]I/O P1[22] —General purpose digital input/output pin.O MAT1[0] —Match output for Timer 1, channel 0.P1[23]/PWM1[4]/MISO037[1]I/O P1[23] —General purpose digital input/output pin.O PWM1[4] —Pulse Width Modulator 1, channel 4 output.I/OMISO0 —Master In Slave Out for SSP0.P1[24]/PWM1[5]/MOSI038[1]I/O P1[24] —General purpose digital input/output pin.O PWM1[5] —Pulse Width Modulator 1, channel 5 output.I/OMOSI0 —Master Out Slave in for SSP0.P1[25]/MA T1[1]39[1]I/O P1[25] —General purpose digital input/output pin.O MAT1[1] —Match output for Timer 1, channel 1.P1[26]/PWM1[6]/CAP0[0]40[1]I/O P1[26] —General purpose digital input/output pin.O PWM1[6] —Pulse Width Modulator 1, channel 6 output.ICAP0[0] —Capture input for Timer 0, channel 0.P1[27]/CAP0[1]43[1]I/O P1[27] —General purpose digital input/output pin.I CAP0[1] —Capture input for Timer 0, channel 1.P1[28]/PCAP1[0]/MA T0[0]44[1]I/O P1[28] —General purpose digital input/output pin.I PCAP1[0] —Capture input for PWM1, channel 0.OMAT0[0] —Match output for Timer 0, channel 0.P1[29]/PCAP1[1]/MA T0[1]45[1]I/O P1[29] —General purpose digital input/output pin.I PCAP1[1] —Capture input for PWM1, channel 1.OMAT0[1] —Match output for Timer 0, channel 0.P1[30]/V BUS /AD0[4]21[2]I/O P1[30] —General purpose digital input/output pin.I V BUS —Indicates the presence of USB bus power.Note: This signal must be HIGH for USB reset to occur.IAD0[4] —A/D converter 0, input 4.P1[31]/SCK1/AD0[5]20[2]I/O P1[31] —General purpose digital input/output pin.I/O SCK1 —Serial Clock for SSP1.I AD0[5] —A/D converter 0, input 5.P2[0] to P2[31]I/OPort 2: Port 2 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 2 pins depends upon the pin function selected via the Pin Connect block. Pins 14 through 31 of this port are not available.Table 3.Pin description …continuedSymbolPin Type DescriptionP2[0]/PWM1[1]/ TXD1/ TRACECLK 75[1]I/O P2[0] —General purpose digital input/output pin.O PWM1[1] —Pulse Width Modulator 1, channel 1 output.O TXD1 —T ransmitter output for UART1.O TRACECLK —Trace Clock.P2[1]/PWM1[2]/ RXD1/ PIPEST A T074[1]I/O P2[1] —General purpose digital input/output pin.O PWM1[2] —Pulse Width Modulator 1, channel 2 output.I RXD1 —Receiver input for UART1.O PIPESTAT0 —Pipeline Status, bit 0.P2[2]/PWM1[3]/ CTS1/ PIPEST A T173[1]I/O P2[2] —General purpose digital input/output pin.O PWM1[3] —Pulse Width Modulator 1, channel 3 output.I CTS1 —Clear to Send input for UART1.O PIPESTAT1 —Pipeline Status, bit 1.P2[3]/PWM1[4]/ DCD1/ PIPEST A T270[1]I/O P2[3] —General purpose digital input/output pin.O PWM1[4] —Pulse Width Modulator 1, channel 4 output.I DCD1 —Data Carrier Detect input for UART1.O PIPESTAT2 —Pipeline Status, bit 2.P2[4]/PWM1[5]/ DSR1/ TRACESYNC 69[1]I/O P2[4] —General purpose digital input/output pin.O PWM1[5] —Pulse Width Modulator 1, channel 5 output.I DSR1 —Data Set Ready input for UART1.O TRACESYNC —Trace Synchronization.P2[5]/PWM1[6]/ DTR1/ TRACEPKT068[1]I/O P2[5] —General purpose digital input/output pin.O PWM1[6] —Pulse Width Modulator 1, channel 6 output.O DTR1 —Data T erminal Ready output for UART1.O TRACEPKT0 —Trace Packet, bit 0.P2[6]/PCAP1[0]/ RI1/ TRACEPKT167[1]I/O P2[6] —General purpose digital input/output pin.I PCAP1[0] —Capture input for PWM1, channel 0.I RI1 —Ring Indicator input for UART1.O TRACEPKT1 —Trace Packet, bit 1.P2[7]/RD2/ RTS1/ TRACEPKT266[1]I/O P2[7] —General purpose digital input/output pin.I RD2 —CAN2 receiver input.O RTS1 —Request to Send output for UART1.O TRACEPKT2 —Trace Packet, bit 2.P2[8]/TD2/ TXD2/ TRACEPKT365[1]I/O P2[8] —General purpose digital input/output pin.O TD2 —CAN2 transmitter output.O TXD2 —T ransmitter output for UART2.O TRACEPKT3 —Trace Packet, bit 3.P2[9]/USB_CONNECT/ RXD2/EXTIN064[1]I/O P2[9] —General purpose digital input/output pin.O USB_CONNECT —Signal used to switch an external 1.5 kΩ resistor under software control. Used with the SoftConnect USB feature.I RXD2 —Receiver input for UART2.I EXTIN0 —External T rigger Input.Table 3.Pin description …continuedSymbol Pin Type DescriptionP2[10]/EINT053[6]I/O P2[10] —General purpose digital input/output pin.Note: LOW on this pin while RESET is LOW forces on-chip bootloader to take overcontrol of the part after a reset.I EINT0 —External interrupt 0 input.P2[11]/EINT1/MCIDAT1/I2STX_CLK 52[6]I/O P2[11] —General purpose digital input/output pin.I EINT1 —External interrupt 1 input.O MCIDAT1 —Data line for SD/MMC interface. (LPC2368 only)I/O I2STX_CLK —Transmit Clock. It is driven by the master and received by the slave.Corresponds to the signal SCK in the I 2S-bus speciﬁcation .P2[12]/EINT2/MCIDAT2/I2STX_WS 51[6]I/O P2[12] —General purpose digital input/output pin.I EINT2 —External interrupt 2 input.O MCIDAT2 —Data line for SD/MMC interface. (LPC2368 only)I/O I2STX_WS —Transmit Word Select. It is driven by the master and received by theslave. Corresponds to the signal WS in the I 2S-bus speciﬁcation .P2[13]/EINT3/MCIDAT3/I2STX_SDA 50[6]I/O P2[13] —General purpose digital input/output pin.I EINT3 —External interrupt 3 input.O MCIDAT3 —Data line for SD/MMC interface. (LPC2368 only)I/O I2STX_SDA —Transmit data. It is driven by the transmitter and read by the receiver.Corresponds to the signal SD in the I 2S-bus speciﬁcation .P3[0] to P3[31]I/O Port 3: Port 3 is a 32-bit I/O port with individual direction controls for each bit. Theoperation of port 3 pins depends upon the pin function selected via the Pin Connectblock. Pins 0 through 24, and 27 through 31 of this port are not available.P3[25]/MA T0[0]/PWM1[2]27[1]I/O P3[25] —General purpose digital input/output pin.O MAT0[0] —Match output for Timer 0, channel 0.O PWM1[2] —Pulse Width Modulator 1, output 2.P3[26]/MA T0[1]/PWM1[3]26[1]I/O P3[26] —General purpose digital input/output pin.O MAT0[1] —Match output for Timer 0, channel 1.O PWM1[3] —Pulse Width Modulator 1, output 3.P4[0] to P4[31]I/O Port 4: Port 4 is a 32-bit I/O port with individual direction controls for each bit. Theoperation of port 4 pins depends upon the pin function selected via the Pin Connectblock. Pins 0 through 27, 30, and 31 of this port are not available.P4[28]/MA T2[0]/TXD382[1]I/O P4[28] —General purpose digital input/output pin.O MAT2[0] —Match output for Timer 2, channel 0.O TXD3 —T ransmitter output for UART3.P4[29]/MA T2[1]/RXD385[1]I/O P4[29] —General purpose digital input/output pin.O MAT2[1] —Match output for Timer 2, channel 1.I RXD3 —Receiver input for UART3.TDO 1[1]O TDO —T est Data out for JTAG interface.TDI 2[1]I TDI —T est Data in for JTAG interface.TMS 3[1]I TMS —T est Mode Select for JTAG interface.TRST 4[1]I TRST —T est Reset for JTAG interface.TCK 5[1]ITCK —T est Clock for JTAG interface.Table 3.Pin description …continued Symbol PinType Description[1]5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.[2]5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When conﬁgured as a DAC input,digital section of the pad is disabled.[3]5V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When conﬁgured as the DAC output,digital section of the pad is disabled.[4]Open-drain 5 V tolerant digital I/O I 2C-bus 400 kHz speciﬁcation compatible pad. It requires an external pull-up to provide output functionality. When power is switched off, this pin connected to the I 2C-bus is ﬂoating and does not disturb the I 2C lines.[5]Pad provides digital I/O and USB functions. It is designed in accordance with the USB speciﬁcation, revision 2.0 (Full-speed and Low-speed mode only).[6]5 V tolerant pad with 5ns glitch ﬁlter providing digital I/O functions with TTL levels and hysteresis [7]5 V tolerant pad with 20ns glitch ﬁlter providing digital I/O function with TTL levels and hysteresis [8]Pad provides special analog functionality.[9]Pad provides special analog functionality.[10]Pad provides special analog functionality.[11]Pad provides special analog functionality.[12]Pad provides special analog functionality.[13]Pad provides special analog functionality.RTCK 100[1]I/O RTCK —JT AG interface control signal.Note:LOW on this pin while RESET is LOW enables ETM pins (P2[9:0])to operate asT race port after reset.RSTOUT14[1]O RSTOUT —This is a 1.8V pin. LOW on this pin indicates LPC2364/66/68 being in Reset state.RESET 17[7]I external reset input: A LOW on this pin resets the device, causing I/O ports andperipherals to take on their default states, and processor execution to begin ataddress 0. TTL with hysteresis, 5V tolerant.XT AL122[8]I Input to the oscillator circuit and internal clock generator circuits.XTAL223[8]O Output from the oscillator ampliﬁer.RTCX116[8]I Input to the RTC oscillator circuit.RTCX218[8]O Output from the RTC oscillator circuit.V SS 15, 31,41, 55,72, 97,83[9]I ground: 0V reference.V SSA 11[10]I analog ground: 0V reference. This should nominally be the same voltage as V SS ,but should be isolated to minimize noise and error.V DD(3V3)28, 54,71,96[11]I 3.3V supply voltage: This is the power supply voltage for the I/O ports.V DD(DCDC)(3V3)13, 42,84[12]I 3.3V DC-to-DC converter supply voltage:This is the supply voltage for the on-chip DC-to-DC converter only.V DDA 10[13]I analog 3.3V pad supply voltage: This should be nominally the same voltage asV DD(3V3) but should be isolated to minimize noise and error. This voltage is used topower the ADC and DAC.VREF 12[13]I ADC reference:This should be nominally the same voltage as V DD(3V3)but should beisolated to minimize noise and error. Level on this pin is used as a reference for ADCand DAC.VBAT19[13]I RTC power supply: 3.3V on this pin supplies the power to the RTC.Table 3.Pin description …continued SymbolPin Type Description。

混合集成电路外文文献

240
A 5-bit 150 MS/s, 3.3 V CMOS A/D Converter with a 32 Step Adjustable Reference Circuit
Thomas Desel, Franz Kuttner*, Claus Kropf*, Manfred Haas*
Fraunhofer Institute for Integrated Circuits D-91058 Erlangen, Am Weichselgarten 3, Germany
24 1
ADC Architecture
The A/D converter uses full-flash architecture with integrated samplehold (Fig. 1). Consisting of two parts, the reference stage is divided into a resistor network and a capacitor network [6]. Three coarse reference voltages are defined by the resistors, whereas the capacitors create fine 62 the reference voltages. The 31 comparators' output signals are encoded in a 2's complement 5-bit word. Generation of the control signals and bias currents for the comparators is also included on chip.

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