2012-APSURSI -94 GHz power amplifier device architecture in SiGe for active phased arrays

94 GHz Power Amfor A

Thomas J. Farmer, Ali Darwish, EdwardH. Alfred Hung U.S. Army Research Laboratory Adelphi, MD 20783, USA Abstract— This paper discusses the first implemHigh Voltage / High Power (HiVP) Amplifier Asilicon in the W-band. Designed and laidcommercial 120 nm SiGe HBT BiCMOS proceoutput power of 9.7 dBm, gain of 7.7 dB, and a in an area of 0.20 mm2 have been achieved at signal gain > 10 dB has been simulated from GHz. The intent of this paper is to introducdevice architecture intended for inclusion inreceiver ICs that would become a part of anarray operating in the W-band. In addition, prwith a simplified simulation technique, layout an architecture with a small layout footprinttechniques employed in current research. I. INTRODUCTION The benefits and applications of electriphased arrays over mechanical methods are wand have been well discussed since being pr1930s [1]. However, current phased arratransmit/receive modules with III-V front-end and/or InP) and silicon-based baseband with scontrol chipset module implementations are prohibitive. Integration of all the transmitfunctions onto a single integrated circuit integration of multiple transmitter / receiverswafer make solutions based in a SiGe BiCexcellent candidates to allow for more wideactive phased arrays in defense, science, anapplications due to the lowered cost of imple[2]. Currently silicon-based research in transmitters suffers from a lack of quality poin terms of output power, gain, bandwidth, anthe W-band (75 GHz to 110 GHz). Siliconamplifier architectures in the W-band have focsomewhat traditional device architectures to metrics. These architectures have includebalanced and cascoded, slow-wave, and multThe research reported here aims to introducnew architecture to the W-band, the High VPower (HiVP) architecture. This architectusilicon device breakdown limitations throtransistors in a unique manner which allooutput voltage swings to increase output powematching. With recent success of this archiGHz and 30 GHz in SiGe, the authors mplifier Device ArchitectActive Phased Arrays d Viveiros, Mona E. ZaghlElectrical and Computer EnginThe George WashingtonWashington, DC 2 mentation of the Architecture in d out using a ess, a saturated PAE of 12.0 % 94 GHz. Small 50 GHz to 110 ce an amplifier n transmitter / n active phased ovide designers examples, and t over classical

ically scanned well understood roposed in the ays based on d MMIC (GaAs separate digital size and cost tter / receiver or even the s onto a single CMOS process espread use of nd commercial ementation [1]-the area of ower amplifiers nd efficiency at n-based power cused on using improve these ed differential, ti-stage [3]-[6]. ce a relatively Voltage / High ure overcomes ough stacking ows for larger er and simplify itecture at 2.4 adapted this architecture to the W-band as adevice architectures in terms ofconsumption [7]. The results are pII. DESIGN AND IMThe schematic and layout of thshown in Fig. 1 and 2. A detaildesign of the HiVP is given in [7]devices, Q1-Q4 provide the amplThey are surrounded by a mirnetwork where devices QB1-QB4 pnegative feedback path for the aarrangement, Q1-Q4 split the DCcascode, C2-C4 and L2-L4 are sizetransistor to be the optimum transistor. The stack of transistorcombiner. The bias to QB1-QB4 asignal to protect Q1-Q4 from reacand BVCBO breakdown limitations Figure 1. SiGe HiVP schematic (c TABLE

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Schematic Label

RQ1 / Q2/ Q3 / Q4 EmitteQB1 / QB2/ QB3 / QB4 EmitteC2/ C3 / C4 Total: 95 fFL2 / L3/ L4 21 pH / 90R1A / R2A / R3A / R4A

Each: 101R1B / R2B / R3B / R4B Each: LCHOKE/ CC OfVCC / IC L4 C4 R4BR4ALCHOKE QB4L3 C3 R3BR3AQB3L2 C2 R2BR2AQB2R1BR1AQB1CC RFINture in SiGe

loul neering Department n University 20052 an alternative to traditional f both simulation and area presented in this paper. MPLEMENTATION his 94 GHz SiGe HiVP are led discussion on the basic ]. The four main SiGe HBT lification of the RF signal. rrored biasing / feedback provide both DC bias and a amplifier. Like a cascoded C bias voltage, but unlike a d to allow each proceeding match for the preceding rs acts as its own RF power adjusts with the RF output hing their individual BVCEO .

component sizes in Table I). SED IN THIS IMPLEMENTATION Relevant Propertieser Area: 120 nm × 18 µm er Area: 120 nm ×1.0 µm F / 44 fF / 24 fF (Al MIMCAP) 0 pH / 90 pH (Metal Layer 2) .5 k• (P+ PolySi, 15 % tol.) 7 k• (P+ PolySi,15% tol.) ff-Chip Components 4.32 V / 16.4 mA Q4 C4 R4B R4ACC RFOUTVCC=4×VCEQB4Q3 C3 R3B R3AQB3Q2 C2 R2B R2AQB2Q1 R1B R1AQB1Chip Boundary

978-1-4673-0462-7/12/$31.00 ©2012 IEEE Figure. 2. SiGe HiVP layout without probe pads (130 µm × 160 µm). III. RESULTS Figure. 3. Large signal characteristics of SiGe HiVP at 94 GHz.