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zl30414中文资料_数据手册_IC数据表

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1Features•Meets jitter requirements of Telcordia GR-253-CORE for OC-192, OC-48, OC-12, and OC-3 rates•Meets jitter requirements of ITU-T G.813 for STM-64, STM-16, STM-4 and STM-1 rates•Provides four LVPECL differential output clocks at 622.08 MHz•Provides a CML differential clock at 155.52 MHz •Provides a single-ended CMOS clock at 19.44 MHz•Lock Indicator•Provides enable/disable control of output clocks •Accepts a CMOS reference at 19.44 MHz •3.3 V supplyApplications•SONET/SDH line cards •Network Element timing cardsDescriptionThe ZL30414 is an analog phase-locked loop (APLL)designed to provide jitter attenuation and rate conversion for SDH (Synchronous Digital Hierarchy)and SONET (Synchronous Optical Network)networking equipment. The ZL30414 generates very low jitter clocks that meet the jitter requirements of Telcordia GR-253-CORE OC-192, OC-48, OC-12, OC-3 rates and ITU-T G.813 STM-64, STM-16, STM-4 and STM-1 rates.The ZL30414 accepts a CMOS compatible reference at 19.44MHz and generates four LVPECL differential output clocks at 622.08 MHz, a CML differential clock at 155.52MHz and a single-ended CMOS clock at 19.44MHz. The output clocks can be individually enabled or disabled. The ZL30414provides a LOCK indication.February 2005Ordering InformationZL30414QGC 64 Pin TQFP Trays ZL30414QGC164 Pin TQFP*Trays*Pb Free Matte Tin-40°C to +85°CZL30414SONET/SDH Clock Multiplier PLLData SheetFigure 1 - Functional Block DiagramFrequency DetectorVCOC622oP/N-AFrequency LPFC622oP/N-B C622oP/N-C VDD GND VCCC622oP/N-D C19oC19oENC155oP/N C155oEN Loop FilterC622oEN-C C19iC622oEN-B BIAS C622oEN-A C622oEN-D& Phase 19.44MHz05State MachineLOCK Reference Bias Circuitand Dividers and Clock DriversZL30414Data SheetFigure 2 - TQFP 64 pin (Top View)Pin DescriptionPin Description TablePin #Name Description1GND Ground. 0 volt2VCC1Positive Analog Power Supply. +3.3V ±10%.3VCC Positive Analog Power Supply. +3.3V ±10%.45C155oN C155oP C155 Clock Output (CML). These outputs provide a differential 155.52MHz clock.6GND Ground. 0 volt7VCC2Positive Analog Power Supply. +3.3V ±10%8LPF Low Pass Filter (Analog). Connect to this pin external RC network (R F and C F ) for the low pass filter.9GND Ground. 0 volt 10GNDGround. 0 volt505254565860626434363840444648423230282624222018GND VDD GND VCC VDD VDD GNDGND NC GND GND LOCK GND C19o VCC G N D V D D C 19o E N N C N C I C N C V D D C 19i V D D N C N C V D D G N D V C C C 622o P -C C 622o N -C G N D V C C C 622o P -B C 622o N -B G N D V C C C 622o P -A C 622o N -A G N D C 622o P -D C 622o N -D V C C161412106428GND VCC1VCC C155oN C155oP GND VCC2LPF C622oEN-B C622oEN-DGND BIAS C155oEN C622oEN-A C622oEN-C GND G N D G N D G N DGND ZL3041465 - EP_GNDZL30414Data Sheet11BIASBias. See Figure 13 for the recommended bias circuit.12C155oEN C155o Clock Enable (CMOS Input). If tied high this control pin enables the C155oP/N differential driver. Pulling this input low disables the output clock and deactivates differential drivers.13C622oEN-AC622 Clock Output Enable A (CMOS Input). If tied high this control pinenables the C622oP/N-A output clock. Pulling this input low disables the output clock without deactivating differential drivers.14C622oEN-BC622 Clock Output Enable B (CMOS Input). If tied high this control pinenables the C622oP/N-B output clock. Pulling this input low disables the output clock without deactivating differential drivers.15C622oEN-CC622 Clock Output Enable C (CMOS Input). If tied high this control pinenables the C622oP/N-C output clock.Pulling this input low disables the output clock without deactivating differential drivers.16C622oEN-DC622 Clock Output Enable D (CMOS Input). If tied high this control pinenables the C622oP/N-D output clock.Pulling this input low disables the output clock without deactivating differential drivers.17GND Ground. 0 volt18VDD Positive Digital Power Supply. +3.3V ±10%19NC No internal bonding Connection. Leave unconnected.20NC No internal bonding Connection. Leave unconnected.21NC No internal bonding Connection. Leave unconnected.22VDD Positive Digital Power Supply. +3.3V ±10%23IC Internal Connection. Connect this pin to Ground (GND).24NC No internal bonding Connection. Leave unconnected.25NC No internal bonding Connection. Leave unconnected.26C19oENC19o Output Enable (CMOS Input). If tied high this control pin enables the C19o output clock. Pulling this pin low forces output driver into a high impedance state.27GND Ground. 0 volt28C19i C19 Reference Input (CMOS Input). This pin is a single-ended input reference source used for synchronization. This pin accepts 19.44MHz. 29VDD Positive Digital Power Supply. +3.3V ±10%30GND Ground. 0 volt31VDD Positive Digital Power Supply. +3.3V ±10%32GNDGround. 0 voltPin Description Table (continued)Pin #Name DescriptionZL30414Data Sheet33GND Ground. 0 volt34VDD Positive Digital Power Supply. +3.3V ±10%35C19o C19 Clock Output (CMOS Output). This pin provides a single-ended CMOSclock at 19.44 MHz.36GND Ground. 0 volt37LOCK Lock Indicator (CMOS Output). This output goes high when PLL is frequencylocked to the input reference C19i.38GND Ground. 0 volt39GND Ground. 0 volt40NC No internal bonding Connection. Leave unconnected.41GND Ground. 0 volt42VDD Positive Digital Power Supply. +3.3V ±10%43GND Ground. 0 volt44VCC Positive Analog Power Supply. +3.3V ±10%45GND Ground. 0 volt46VDD Positive Digital Power Supply. +3.3V ±10%47VCC Positive Analog Power Supply. +3.3V ±10%48GND Ground. 0 volt49VCC Positive Analog Power Supply. +3.3V ±10%.5051C622oN-DC622oP-D C622 Clock Output (LVPECL). These outputs provide a differential LVPECL clock at 622.08MHz. Unused LVPECL port should be left unterminated to decrease supply current.52GND Ground. 0 volt53VCC Positive Analog Power Supply. +3.3V ±10%.5455C622oP-CC622oN-C C622 Clock Output (LVPECL). These outputs provide a differential LVPECL clock at 622.08MHz. Unused LVPECL port should be left unterminated to decrease supply current.56GND Ground. 0 volt57VCC Positive Analog Power Supply. +3.3V ±10%.5859C622oN-BC622oP-B C622 Clock Output (LVPECL). These outputs provide a differential LVPECL clock at 622.08MHz. Unused LVPECL port should be left unterminated to decrease supply current.Pin Description Table (continued)Pin #Name DescriptionZL30414Data Sheet1.0 Functional DescriptionThe ZL30414 is an analog phased-locked loop which provides rate conversion and jitter attenuation for SONET/SDH OC-192/STM-64, OC-48/STM-16, OC-12/STM-4 and OC-3/STM-1 applications. A functional block diagram of the ZL30414 is shown in Figure 1 and a brief description is presented in the following sections.1.1 Frequency/Phase DetectorThe Frequency/Phase Detector compares the frequency/phase of the input reference signal with the feedback signal from the Frequency Divider circuit and provides an error signal corresponding to the frequency/phase difference between the two. This error signal is passed to the Loop Filter circuit.1.2 Lock IndicatorThe ZL30414 has a built-in LOCK detector that measures frequency difference between input reference clock C19i and the VCO frequency. When the VCO frequency is less than ±300ppm apart from the input reference frequency then the LOCK pin is set high. The LOCK pin is pulled low if the frequency difference exceeds ±1000ppm.1.3 Loop FilterThe Loop Filter is a low pass filter. This low pass filter ensures that the network jitter requirements are met for an input reference frequency of 19.44MHz. The corner frequency of the Loop Filter is configurable with an external capacitor and resistor connected to the LPF pin and ground as shown in Figure 3.Figure 3 - Loop Filter Elements60GND Ground. 0 volt61VCC Positive Analog Power Supply. +3.3V ±10%.6263C622oP-A C622oN-A C622 Clock Output (LVPECL). These outputs provide a differential LVPECL clock at 622.08MHz. Unused LVPECL port should be left unterminated to decrease supply current.64GND Ground. 0 volt65NCNo internal bonding Connection. Leave unconnected.Pin Description Table (continued)Pin #Name DescriptionR F C FZL30414LPFR F =8.2 k Ω, C F =470 nFFilterLoop Frequency and Phase DetectorVCOZL30414Data Sheet 1.4 VCOThe voltage-controlled oscillator (VCO) receives the filtered error signal from the Loop Filter, and based on the voltage of the error signal generates a primary frequency. The VCO output is connected to the "Frequency Dividers and Clock Drivers" block that divides VCO frequency and buffer generated clocks.1.5 Output Interface CircuitThe output of the VCO is used by the Output Interface Circuit to provide four LVPECL differential clocks at 622.08MHz, one CML differential clock at 155.52MHz and a single-ended 19.44MHz output clock. This block provides also a 19.44MHz feedback clock that closes PLL loop. Each output clock can be enabled or disabled individually with the associated Output Enable pin.Output Clocks Output Enable PinsC622oP/N-A C622oEN-AC622oP/N-B C622oEN-BC622oP/N-C C622oEN-CC622oP/N-D C622oEN-DC155oP/N C155oENC19o C19oENTable 1 - Output Enable ControlTo reduce power consumption and achieve the lowest possible intrinsic jitter the unused output clocks must be disabled. If any of the LVPECL outputs are disabled they must be left open without any terminations.ZL30414Data Sheet 2.0 ZL30414 PerformanceThe following are some of the ZL30414 performance indicators that complement results listed in the Characteristics section of this data sheet.2.1 Input Jitter ToleranceJitter tolerance is a measure of the PLL’s ability to operate properly (i.e., remain in lock and/or regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its input reference. The input jitter tolerance of the ZL30414 is shown in Figure 4. On this graph, the single line at the top represents measured input jitter tolerance and the three overlapping lines below represent minimum input jitter tolerance for OC-192, OC-48, and OC-12 network interfaces. The jitter tolerance is expressed in picoseconds (pk-pk) to accommodate requirements for interfaces operating at different rates.Figure 4 - Input Jitter ToleranceZL30414Data Sheet 2.2 Jitter Transfer CharacteristicJitter Transfer Characteristic represents a ratio of the jitter at the output of a PLL to the jitter applied to the input of a PLL. This ratio is expressed in dB and it characterizes the PLLs ability to attenuate (filter) jitter. The jitter transfer characteristic for the ZL30414 configured with recommended loop filter components (R F=8.2 kΩ, C F=470 nF) is shown in Figure 5. The plotted curves represent jitter transfer characteristics over the recommended voltage (3.0V to 3.6V) and temperature (-40C to 85C) ranges.Figure 5 - Jitter Transfer CharacteristicZL30414Data Sheet3.0 Applications3.1 Ultra-Low Jitter SONET/SDH Equipment ClocksThe ZL30414 functionality and performance complements the entire family of the Zarlink’s advanced network synchronization PLLs. Its superior jitter filtering characteristics exceed requirements of SONET/SDH optical interfaces operating up to OC-192/STM-64 rate (10 Gbit/s). The ZL30414 in combination with the MT90401 or the ZL30407 (SONET/SDH Network Element PLLs) provides the core building blocks for high quality equipment clocks suitable for network synchronization (see Figure 6) .Figure 6 - SONET/SDH Equipment ClockMT90401ZL30414C155o CML622.08 MHz 19.44 MHzC622oA LVPECL C622oB LVPECLC622oC LVPECL C622oD LVPECL C19o CMOSC19iC19o CMOS C155o LVDS C34o/C44o CMOS C16o CMOS C8o CMOS C6o CMOS 19.44 MHz C2o CMOS C1.5o CMOS F8o CMOS F0o CMOS622.08 MHz 622.08 MHz 622.08 MHz 155.52 MHzC4o CMOS 34.368 MHz or 44.736 MHz 16.384 MHz 8.192 MHz 6.312 MHz 4.096 MHz 2.048 MHz 1.544 MHz 8 kHz 8 kHzPRI SECPRIOR SECOR LOCKHOLDOVERRefSel RefAlignR FLPFC FC 155o E N155.52 MHz C 622o E N -AC 622o E N -BC 622o E N -CC 622o E N -DC 19o E ND SC SR /WA 0 - A 6D 0 - D 7uPData PortController PortSynchronization Reference ClocksNote: Only main functional connections are shown20 MHz C 20iF16o CMOS OCXO8 kHz or ZL30407L O C KZL30414Data SheetThe ZL30414 in combination with the MT9046 provides an optimum solution for SONET/SDH line cards (see Figure 7).Figure 7 - SONET/SDH Line CardMT9046ZL30414C19iC19o CMOS C16o CMOS C8o CMOS C6o CMOS 19.44 MHz C2o CMOS C1.5o CMOS F8o CMOS F0o CMOSC4o CMOS16.384 MHz 8.192 MHz 6.312 MHz 4.096 MHz 2.048 MHz 1.544 MHz 8 kHz 8 kHzPRI SECLOCKHOLDOVERRSELR 1LPFC 1C 155o E NC 622o E N -AC 622o E N -BC 622o E N -CC 622o E N -DC 19o E NM S 1F S 2F L O C KuCSynchronization Reference ClocksNote: Only main functional connections are shown20 MHz F16o CMOS TCXO8 kHz C 2R 1 = 680 ΩC 1 = 820 nF C 2 = 22 nFC20iM S 2F S 1P C C iHardware ControlT C L RC155o CML622.08 MHz 19.44 MHzC622oA LVPECL C622oB LVPECLC622oC LVPECLC622oD LVPECL C19o CMOS622.08 MHz 622.08 MHz 622.08 MHz 155.52 MHz L O C KZL30414Data Sheet3.2 Recommended Interface circuit 3.2.1 LVPECL to LVPECL InterfaceThe C622oP/N-A, C622oP/N-B, C622oP/N-B, and C622oP/N-D outputs provide differential LVPECL clocks at 622.08MHz. The LVPECL output drivers require a 50Ω termination connected to the Vcc-2V source for each output terminal at the terminating end as shown below. The terminating resistors should be placed as close as possible to the LVPECL receiver.Figure 8 - LVPECL to LVPECL Interface3.2.2 CML to CML InterfaceThe C155o output provides a differential CML/LVDS compatible clock at 155.52MHz. The output drivers require a 50Ω load at the terminating end if the receiver is CML type.Figure 9 - CML to CML InterfaceLVPECL LVPECL ZL30414Z=50 ΩZ=50 ΩC622oP-AC622oN-AReceiverGNDTypical resistor values: R1 = 130 Ω, R2 =82 ΩR1R2VCC=+3.3 VR1R2VCC0.1 uF+3.3 VDriver 622.08 MHzZL30414CML Z=50 ΩCML 50 ΩC155oPC155oNDriver GNDVCCReceiver0.1 uF+3.3 V50 ΩZ=50 Ω0.1 uF0.1 uFLow impedance DC bias source155.52 MHzZL30414Data Sheet3.2.3 CML to LVDS InterfaceTo configure the driver as an LVDS driver, external biasing resistors are required to set up the common mode voltage as specified by ANSI/TIA/EIA-644 LVDS standard. The standard specifies the V CM (common mode voltage)as minimum 1.125V, typical 1.2V, and maximum 1.375V. The following figure provides a recommendation for LVDS applications.Figure 10 - LVDS Termination3.2.4 CML to LVPECL InterfaceThe CML output can drive LVPECL input as is shown in Figure 11. The terminating resistors should be placed as close as possible to the LVPECL receiver.Figure 11 - CML to LVPECL InterfaceZL30414CML Z=50 ΩZ=50 ΩDriver 0.1 uF+3.3 VGNDVCCLVDS 10 nF10 nFReceiverR1R2VCC=+3.3 VR1R2100 ΩTypical resistor values: R1 = 16k Ω, R2 = 10k ΩC155oPC155oN155.52 MHzLVPECL CML ZL30414Z=50 ΩZ=50 ΩReceiverGNDTypical resistor values: R1 = 82 Ω, R2 =130 ΩR1R2VCC=+3.3 VR1R2VCC0.1 uF+3.3 VDriver 10 nF10 nFC155oPC155oN155.52 MHzZL30414Data Sheet3.3 Tristating LVPECL OutputsThe ZL30414 has four differential 622.08MHz LVPECL outputs, which can be used to drive four different OC-3/OC-12/OC-48/OC-192 devices such as framers, mappers and SERDES. In the case where fewer than four clocks are required, a user can disable unused LVPECL outputs on the ZL30414 by pulling the corresponding enable pins low.When disabled, voltage at the both pins of the differential LVPECL output will be pulled up to Vcc - 0.7V.For applications requiring the LVPECL outputs to be in a tri-state mode, external AC coupling can be used as shown in Figure 12. Typically this might be required in hot swappable applications.Resistors R1 and R2 are required for DC bias of the LVPECL driver. Capacitors C1 and C2 are used as AC coupling capacitors. During disable mode (C622oEN pin pulled low) those capacitors present infinite impedance to the DC signal and to the receiving device this looks like a tristated (High-Z) output. Resistors R3, R4, R5 and R6are used to terminate the transmission line with 50ohm impedance and to generate DC bias voltage for the LVPECL receiver. If the LVPECL receiver has an integrated 50ohm termination and bias source, resistors R3, R4,R5 and R6 should not be populated.Figure 12 - Tristatable LVPECL OutputsZ=50Z=50C622oENZL304140.1 uC10.1 uC2R482.5R682.5R5127R3127R1200R2200 3.3 V 3.3 VZL30414Data Sheet 3.4 Power Supply and BIAS Circuit Filtering RecommendationsFigure 13 presents a complete filtering arrangement that is recommended for applications requiring maximum jitter performance. The level of required filtering is subject to further optimization and simplification. Please check Zarlink’s web site for updates.Figure 13 - Power Supply and BIAS Circuit FilteringZL30414Data Sheet4.0 Characteristics†Voltages are with respect to ground unless otherwise stated.‡Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.†Voltages are with respect to ground unless otherwise stated.‡Typical figures are for design aid only: not guaranteed and not subject to production testing.Absolute Maximum Ratings †CharacteristicsSym.Min.‡Max.‡Units 1Supply voltage V DDR , V CCRTBD TBD V 2Voltage on any pin V PIN -0.5V CC + 0.5V DD + 0.5V 3Current on any pin I PIN -0.530mA 4ESD Rating V ESD 1250V 5Storage temperature T ST -55125°C 6Package power dissipationP PD1.8WRecommended Operating Conditions †CharacteristicsSym.Min.Typ.‡Max.Units Notes1Operating Temperature T OP -4025+85°C 2Positive SupplyV DD , V CC3.03.33.6VDC Electrical Characteristics †CharacteristicsSym.Min.Typ.‡Max.Units Notes 1Supply CurrentI DD +I CC146mALVPECL, CMLdrivers disabled and unterminated2Incremental Supply Current to single LVPECL driver (driver enabled and terminated, see Figure 8)I LVPECL37mANote 1Note 23Incremental Supply Current to CML driver (driver enabled and terminated, see Figure 9)I CML26mA Note 34CMOS: High-level input voltageV IH 0.7V DDV DD V 5CMOS: Low-level input voltageV IL 00.3V DDV 6CMOS: Input leakage currentI IL15uAV I = V DD or 0VZL30414Data Sheet-†: Voltages are with respect to ground unless otherwise stated.-‡:Typical figures are for design aid only: not guaranteed and not subject to production testing.-Supply voltage and operating temperature are as per Recommended Operating Conditions-Note 1: The I LVPECL current is determined by the termination network connected to LVPECL outputs. More than 25% of this current flows outside the chip and it does not contribute to the internal power dissipation.-Note 2: LVPECL outputs terminated with Z T = 50Ω resistors biased to V CC -2V (see Figure 8)-Note 3: CML outputs terminated with Z T = 50Ω resistors connected to low impedance DC bias voltage source (see Figure 9)7CMOS: Input bias current for pulled-down inputs:C622oEN-A, C622oEN-C, C622oEN-D, OC-CLKoEN I B-PU300uAV I = V DD8CMOS: Input bias current for pulled-up inputs: , C622oEN-B, C19oENI B-PD90uAV I = 0V9CMOS: High-level output voltageV OH 2.4V I OH = 8 mA 10CMOS: Low-level output voltageV OL 0.4VI OL = 4 mA 11LOCK pin: High-level output voltageV OH 2.4I OH = 0.5 mA 12LOCK pin: Low-level output voltageV OL 0.4I OL = 0.5 mA13CMOS: C19o output rise time T R 1.8 3.3ns 18 pF load 14CMOS: C19o output fall time T F 1.1 1.4ns 18 pF load 15LVPECL: Differential output voltage (622.08MHz)IV OD_LVPECL I 1.17V Note 216LVPECL: Offset voltage (622.08MHz)V OS_LVPECLVcc-1.31Vcc-1.20Vcc-1.09V Note 217LVPECL: Output rise/fall times (622.08MHz)T RF 170ps Note 218CML: Differential output voltage (155.52MHz)IV OD_CML I 0.73V Note 319CML: Offset voltage (155.52MHz)V OS_CML Vcc-0.58Vcc-0.54Vcc-0.50V Note 320CML: Output rise/fall times (155.52 MHz)T RF220psNote 3DC Electrical Characteristics † (continued)CharacteristicsSym.Min.Typ.‡Max.Units NotesZL30414Data Sheet†Voltages are with respect to ground unless otherwise stated.Figure 14 - Output Timing Parameter Measurement Voltage LevelsAC Electrical Characteristics †- Output Timing Parameters Measurement Voltage LevelsCharacteristicsSym CMOS LVPECL CMLUnits 1Threshold VoltageV T-CMOS V T-LVPECL V T-CML0.5V DD0.5V OD_LVPECL0.5V OD_CMLV2Rise and Fall Threshold Voltage High V HM 0.7V DD 0.8V OD_LVPECL 0.8V OD_CML V 3Rise and Fall Threshold Voltage LowV LM0.3V DD0.2V OD_LVPECL0.2V OD_CMLVV T All SignalsV HM V LMt IF , t OFt IR , t ORTiming Reference PointsZL30414Data SheetAC Electrical Characteristics†- C19i Input to C19o, C155o and C622o Output TimingCharacteristics Sym.Min.Typ.‡Max.Units Notes1C19i to C19o delay t C19D 6.27.28.2ns2C19i to C155o delay tc155D345ns3C19i to C622oA delay t C622D00.8 1.6ns4C155o duty cycle d C155L485052%5C622o duty cycle d C622L485052%† Supply voltage and operating temperature are as per Recommended Operating Conditions‡Typical figures are for design aid only: not guaranteed and not subject to production testing.Figure 15 - C19i Input to C19o, C155o and C622o Output TimingZL30414Data SheetAC Electrical Characteristics†- C622 Clocks Output TimingCharacteristics Sym.Min.Typ.‡Max.Units Notes1C622oA to C622oB t C622D-AB-500+50ps2C622oA to C622oC t C622D-AC-500+50ps3C622oA to C622oD t C622D-AD-500+50ps† Supply voltage and operating temperature are as per Recommended Operating Conditions‡Typical figures are for design aid only: not guaranteed and not subject to production testing.Figure 16 - C622oB, C622oC, C622oD Outputs TimingZL30414Data SheetPerformance Characteristics - Functional (V CC = 3.3V ±10%; T A = -40 to 85°C )Performance Characteristics : Output Jitter Generation - GR-253-CORE conformance (V CC = 3.3V ±10%;T A = -40 to 85°C )†Typical figures are for design aid only: not guaranteed and not subject to production testing.‡Loop Filter components: R F =8.2 k Ω, C F =470 nFCharacteristicsMin.Typ.Max.Units Notes1Pull-in range±1000ppmAt nominal input reference frequency C19i = 19.44MHz2Lock Time 300msGR-253-CORE Jitter Generation RequirementsZL30414 Jitter GenerationPerformance Interface (Category II)JitterMeasurementFilter Limit in UI Equivalent limit in time domainTyp.†Max.‡Units 1OC-192STS-19250kHz - 80MHz0.1 UI PP 10.0-7.31ps P-P 0.01 UI RMS 1.00.520.94ps RMS 2OC-48STS-4812kHz - 20MHz0.1 UI PP 40.2-7.32ps P-P 0.01 UI RMS 4.020.580.83ps RMS 3OC-12STS-1212kHz - 5MHz0.1 UI PP 161- 4.37ps P-P 0.01 UI RMS16.10.340.60ps RMSZL30414Data SheetPerformance Characteristics : Output Jitter Generation - G.813 conformance (Option 1 and 2) (V CC = 3.3V ±10%; T A = -40 to 85°C )†Typical figures are for design aid only: not guaranteed and not subject to production testing.‡Loop Filter components: R F =8.2 k Ω, C F =470 nFG.813 Jitter Generation RequirementsZL30414 Jitter GenerationPerformanceInterfaceJitterMeasurementFilter Limit in UIEquivalent limit in time domainTyp.†Max.‡UnitsOption 11STM-644 MHz to 80 MHz0.1 UIpp10.0- 6.95ps P-P 0.490.89ps RMS 20 kHz to 80 MHz0.5 UIpp50.2-11.5ps P-P 0.821.04ps RMS 2STM-161 MHz to 20 MHz0.1 UIpp40.2- 6.40ps P-P 0.500.68ps RMS 5 kHz to 20 MHz0.5 UIpp201-8.67ps P-P 0.681.06ps RMS 3STM-4250 kHz to 5 MHz0.1 UIpp161- 3.33ps P-P 0.260.42ps RMS 1 kHz to 5 MHz0.5 UIpp804-19.1ps P-P 1.512.88ps RMS Option 25STM-644 MHz to 80 MHz0.1 UIpp10.0- 6.95ps P-P 0.490.89ps RMS 20 kHz to 80 MHz0.3 UIpp30.1-11.5ps P-P 0.821.04ps RMS 6STM-1612 kHz - 20 MHz0.1 UIpp40.2-7.32ps P-P 0.580.83ps RMS 7STM-412 kHz - 5 MHz0.1 UIpp161- 4.37ps P-P 0.340.60ps RMSZL30414Data SheetPerformance Characteristics : Output Jitter Generation - ETSI EN 300 462-7-1conformance (V CC = 3.3V ±10%; T A = -40 to 85°C )†Typical figures are for design aid only: not guaranteed and not subject to production testing.‡Loop Filter components: R F =8.2 k Ω, C F =470 nFEN 300 462-7-1 Jitter Generation RequirementsZL30414 Jitter GenerationPerformance Interface JitterMeasurementFilter Limit in UI Equivalent limit in time domainTyp.†Max.‡Units 1STM-161 MHz to 20 MHz0.1 UIpp40.2- 6.40ps P-P 0.500.68ps RMS 5 kHz to 20 MHz 0.5UIpp 201-8.67ps P-P 0.681.06ps RMS 2STM-4250 kHz to 5 MHz 0.1 UIpp 161- 3.33ps P-P 0.260.42ps RMS 1 kHz to 5 MHz 0.5 UIpp 804-19.1ps P-P 1.512.88ps RMS。

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zl30119中文资料_数据手册_IC数据表

zl30119中文资料_数据手册_IC数据表

1A full Design Manual is available to qualified customers.To register, please send an email to TimingandSync@.Features•Synchronizes with standard telecom system references and synthesizes a wide variety of protected telecom line interface clocks that are compliant with Telcordia GR-253-CORE and ITU-T G.813•Internal APLL provides standard output clock frequencies up to 622.08MHz that meet jitter requirements for interfaces up to OC-192/STM-64•Programmable output synthesizers (P0, P1) generate clock frequencies from any multiple of 8kHz up to 77.76MHz in addition to 2kHz •Provides two DPLLs which are independently configurable through a serial peripheral interface •DPLL1 provides all the features necessary forgenerating SONET/SDH compliant clocks including automatic hitless reference switching, automatic mode selection (locked, free-run, holdover), and selectable loop bandwidth•DPLL2 provides a comprehensive set of features for generating derived output clocks and other general purpose clocks•Provides 8 reference inputs which support clock frequencies with any multiples of 8kHz up to 77.76MHz in addition to 2kHz•Provides 3 sync inputs for output frame pulse alignment•Generates several styles of output frame pulses with selectable pulse width, polarity, and frequency •Configurable input to output delay, and output to output phase alignment•Flexible input reference monitoring automatically disqualifies references based on frequency and phase irregularities•Supports IEEE 1149.1 JTAG Boundary ScanJune 2006Figure 1 - Block DiagramZL30119 SONET/SDHOC-48/OC-192 Line Card SynchronizerData SheetOrdering InformationZL30119GGG 100 Pin CABGA Trays ZL30119GGG2100 Pin CABGA*Trays*Pb Free Tin/Silver/Copper-40o C to +85o CZL30119Data SheetApplications•AMCs for AdvancedTCA TM and MicroTCA Systems•Multi-Service Edge Switches or Routers•DSLAM Line Cards•WAN Line Cards•RNC/Mobile Switching Center Line Cards•ADM Line CardsZL30119Data SheetTable of Contents1.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121.1 DPLL Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121.2 DPLL Mode Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131.3 Ref and Sync Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141.4 Ref and Sync Monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151.5 Output Clocks and Frame Pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161.6 Configurable Input-to-Output and Output-to-Output Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182.0 Software Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193.0 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26ZL30119Data SheetList of FiguresFigure 1 - Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - Automatic Mode State Machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 3 - Reference and Sync Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 4 - Output Frame Pulse Alignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 5 - Behaviour of the Guard Soak Timer during CFM or SCM Failures. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 6 - Output Clock Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 7 - Phase Delay Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18ZL30119Data SheetList of TablesTable 1 - DPLL1 and DPLL2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 2 - Set of Pre-Defined Auto-Detect Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 3 - Set of Pre-Defined Auto-Detect Sync Frequencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 4 - Output Clock and Frame Pulse Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 5 - Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19ZL30119Data Sheet The following table captures the changes from the December 2005 issue.Page Item Change22-23Software Register Description Changed the naming and description of the framepulse delay offset registers to clearly show thatthey form a 22-bit register spread out over 3 8-bitregisters. The 22-bit register must be considered amulti-byte register during a read or write operation.This affects registers 0x40-0x42, 0x45-0x47, and0x58-0x5A.ZL30119Data Sheet Pin DescriptionPin # Name I/OType DescriptionInput ReferenceC1 B2 A3 C3 B3 B4 C4 A4ref0ref1ref2ref3ref4ref5ref6ref7I d Input References (LVCMOS, Schmitt Trigger). These are input referencesavailable to both DPLL1 and DPLL2 for synchronizing output clocks. All eightinput references can be automatically or manually selected using softwareregisters. These pins are internally pulled down to Vss.B1 A1 A2sync0sync1sync2I d Frame Pulse Synchronization References (LVCMOS, Schmitt Trigger).These are the frame pulse synchronization inputs associated with inputreferences 0, 1 and 2. These inputs accept frame pulses in a clock format (50%duty cycle) or a basic frame pulse format with minimum pulse width of 5 ns.These pins are internally pulled down to V ss.Output Clocks and Frame PulsesD10sdh_clk0O SONET/SDH Output Clock 0 (LVCMOS). This output can be configured toprovide any one of the SONET/SDH clock outputs up to 77.76MHz. The defaultfrequency for this output is 77.76MHz.G10sdh_clk1O SONET/SDH Output Clock 1 (LVCMOS). This output can be configured toprovide any one of the SONET/SDH clock outputs up to 77.76MHz. The defaultfrequency for this output is 19.44MHz.E10sdh_fp0O SONET/SDH Output Frame Pulse 0 (LVCMOS). This output can be configuredto provide virtually any style of output frame pulse synchronized with anassociated SONET/SDH family output clock. The default frequency for this framepulse output is 8kHz.F10sdh_fp1O SONET/SDH Output Frame Pulse 1 (LVCMOS). This output can be configuredto provide virtually any style of output frame pulse synchronized with anassociated SONET/SDH family output clock. The default frequency for this framepulse output is 2kHz.K9p0_clk0O Programmable Synthesizer 0 - Output Clock 0 (LVCMOS). This output can beconfigured to provide any frequency with a multiple of 8kHz up to 77.76MHz inaddition to 2kHz. The default frequency for this output is 2.048MHz.K7p0_clk1O Programmable Synthesizer 0 - Output Clock 1 (LVCMOS). This is aprogrammable clock output configurable as a multiple or division of the p0_clk0frequency within the range of 2 kHz to 77.76 MHz. The default frequency for thisoutput is 8.192MHz.K8p0_fp0O Programmable Synthesizer 0 - Output Frame Pulse 0 (LVCMOS). This outputcan be configured to provide virtually any style of output frame pulse associatedwith the p0 clocks. The default frequency for this frame pulse output is 8kHz.J7p0_fp1O Programmable Synthesizer 0 - Output Frame Pulse 1 (LVCMOS). This outputcan be configured to provide virtually any style of output frame pulse associatedwith the p0 clocks. The default frequency for this frame pulse output is 8kHz.ZL30119Data SheetJ10p1_clk0OProgrammable Synthesizer 1 - Output Clock 0 (LVCMOS). This output can be configured to provide any frequency with a multiple of 8kHz up to 77.76MHz in addition to 2kHz. The default frequency for this output is 1.544MHz (DS1).K10p1_clk1OProgrammable Synthesizer1 - Output Clock 1 (LVCMOS). This is aprogrammable clock output configurable as a multiple or division of the p1_clk0 frequency within the range of 2kHz to 77.76MHz. The default frequency for this output is 3.088MHz (2x DS1).H10fb_clk OFeedback Clock (LVCMOS). This output is a buffered copy of the feedback clock for DPLL1. The frequency of this output always equals the frequency of the selected reference.E1dpll2_ref ODPLL2 Selected Output Reference (LVCMOS). This is a buffered copy of the output of the reference selector for DPLL2. Switching between input reference clocks at this output is not hitless.A9B10diff0_p diff0_n ODifferential Output Clock 0 (LVPECL). This output can be configured to provide any one of the available SDH clocks. The default frequency for this clock output is 155.52MHz.A10B9diff1_p diff1_nODifferential Output Clock 1 (LVPECL). This output can be configured to provide any one of the available SDH clocks. The default frequency for this clock output is 622.08MHz clock.Control H5rst_b IReset (LVCMOS, Schmitt Trigger). A logic low at this input resets the device. To ensure proper operation, the device must be reset after power-up. Reset should be asserted for a minimum of 300ns.J5dpll1_hs_enI uDPLL1 Hitless Switching Enable (LVCMOS, Schmitt Trigger). A logic high at this input enables hitless reference switching. A logic low disables hitless reference switching and re-aligns DPLL1’s output phase to the phase of the selected reference input. This feature can also be controlled through software registers. This pin is internally pull up to Vdd.C2D2dpll1_mod_sel0dpll1_mod_sel1I uDPLL1 Mode Select 1:0 (LVCMOS, Schmitt Trigger). During reset, the levels on these pins determine the default mode of operation for DPLL1 (Automatic, Normal, Holdover or Freerun). After reset, the mode of operation can becontrolled directly with these pins, or by accessing the dpll1_modesel register through the serial interface. This pin is internally pull up to Vdd.K1diff0_enI uDifferential Output 0 Enable (LVCMOS, Schmitt Trigger). When set high, the differential LVPECL output 0 driver is enabled. When set low, the differential driver is tristated reducing power consumption. This pin is internally pull up to Vdd.D3diff1_enI uDifferential Output 1 Enable (LVCMOS, Schmitt Trigger). When set high, the differential LVPECL output 1 driver is enabled. When set low, the differential driver is tristated reducing power consumption.This pin is internally pull up to Vdd.Pin # Name I/O Type DescriptionZL30119Data SheetStatus H1dpll1_lockOLock Indicator (LVCMOS). This is the lock indicator pin for DPLL1. This output goes high when DPLL1’s output is frequency and phase locked to the input reference.J1dpll1_holdover OHoldover Indicator (LVCMOS). This pin goes high when DPLL1 enters the holdover mode.Serial Interface E2sck I Clock for Serial Interface (LVCMOS). Serial interface clock.F1si I Serial Interface Input (LVCMOS). Serial interface data input pin.G1so O Serial Interface Output (LVCMOS). Serial interface data output pin.E3cs_b I u Chip Select for Serial Interface (LVCMOS). Serial interface chip select. This pin is internally pull up to Vdd.G2int_bOInterrupt Pin (LVCMOS). Indicates a change of device status prompting the processor to read the enabled interrupt service registers (ISR). This pin is an open drain, active low and requires an external pull up to VDD.APLL Loop Filter A6sdh_filter A External Analog PLL Loop Filter terminal.B6filter_ref0A Analog PLL External Loop Filter Reference.C6filter_ref1AAnalog PLL External Loop Filter Reference.JTAG and Test J4tdoOTest Serial Data Out (Output). JTAG serial data is output on this pin on the falling edge of tck. This pin is held in high impedance state when JTAG scan is not enabled.K2tdiI uTest Serial Data In (Input). JTAG serial test instructions and data are shifted in on this pin. This pin is internally pull up to Vdd. If this pin is not used then it should be left unconnected.H4trst_bI uTest Reset (LVCMOS). Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin should be pulsed low on power-up to ensure that the device is in the normal functional state. This pin is internally pulled up to Vdd. If this pin is not used then it should be connected to GND.K3tck I Test Clock (LVCMOS): Provides the clock to the JTAG test logic. If this pin is not used then it should be pulled down to GND.J3tmsI uTest Mode Select (LVCMOS). JTAG signal that controls the state transitions of the TAP controller. This pin is internally pulled up to V DD . If this pin is not used then it should be left unconnected.Pin # NameI/O TypeDescriptionZL30119Data SheetMaster ClockK4osci I Oscillator Master Clock Input (LVCMOS). This input accepts a 20MHzreference from a clock oscillator (TCXO, OCXO). The stability and accuracy ofthe clock at this input determines the free-run accuracy and the long termholdover stability of the output clocks.K5osco O Oscillator Master Clock Output (LVCMOS). This pin must be left unconnectedwhen the osci pin is connected to a clock oscillator.MiscellaneousB5C5G3NC No Connection. Leave unconnected.J2J6H7IC Internal Connection. Connect to ground.D1K6F2F3IC Internal Connection. Leave unconnected.Power and GroundD9 E4 G8 G9 J8 J9 H6 H8V DD PPPPPPPPPositive Supply Voltage. +3.3V DC nominal.E8 F4V CORE PPPositive Supply Voltage. +1.8V DC nominal.A5 A8 C10AV DD PPPPositive Analog Supply Voltage. +3.3V DC nominal.B7 B8 H2AV CORE PPPPositive Analog Supply Voltage. +1.8V DC nominal.Pin # Name I/OType DescriptionZL30119Data SheetI - InputI d -Input, Internally pulled down I u -Input, Internally pulled up O -Output A -Analog P -Power G -GroundD4D5D6D7E5E6E7F5F6F7G4G5G6G7E9F8F9H9V SSG G G G G G G G G G G G G G G G G G Ground. 0 Volts.A7C7C8C9D8H3AV SSG G G G G GAnalog Ground. 0 Volts.Pin # Name I/O Type DescriptionZL30119Data Sheet1.0 Functional DescriptionThe ZL30119 SONET/SDH Line Card Synchronizer is a highly integrated device that provides timing and synchronization for network interface cards. It incorporates two independent DPLLs, each capable of locking to one of eight input references and provides a wide variety of synchronized output clocks and frame pulses.1.1 DPLL FeaturesThe ZL30119 provides two independently controlled Digital Phase-Locked Loops (DPLL1, DPLL2) for clock and/or frame pulse synchronization. Table 1 lists the feature summary for both DPLLs.FeatureDPLL1DPLL2Modes of Operation Free-run, Normal (locked), Holdover Free-run, Normal (locked), Holdover.Loop Bandwidth User selectable: 14Hz, 28Hz, or wideband 1 (890Hz / 56Hz / 14Hz)1. In the wideband mode, the loop bandwidth depends on the frequency of the reference input. For reference frequencies equal to or greater than 64kHz, the loop bandwidth = 890 Hz. For reference frequencies equal to or greater than 8kHz and less than 64 kHz, the loop bandwidth = 56 Hz. For reference frequencies equal to 2kHz, the loop bandwidth is equal to 14Hz.Fixed: 14HzPhase Slope Limiting User selectable: 885ns/s, 7.5µs/s, 61µs/s, or unlimited User selectable: 61µs/s, or unlimited Pull-in Range Fixed: 130ppm Fixed: 130ppm Reference Inputs Ref0 to Ref7Ref0 to Ref7Sync InputsSync0, Sync1, Sync2Sync inputs are not supported.Input Ref Frequencies 2kHz, N * 8kHz up to 77.76 MHz 2kHz, N * 8kHz up to 77.76 MHz Supported Sync Input Frequencies 166.67Hz, 400Hz, 1kHz, 2kHz, 8kHz, 64kHz.Sync inputs are not supported.Input Reference Selection/Switching Automatic (based on programmable priority and revertiveness), or manual Automatic (based on programmable priority and revertiveness), or manual Hitless Ref Switching Can be enabled or disabledCan be enabled or disabled Output Clocksdiff0_p/n, diff1_p/n, sdh_clk0, sdh_clk1, p0_clk0, p0_clk1, p1_clk0, p1_clk1, fb_clk.p0_clk0, p0_clk1, p1_clk0, p1_clk1.Output Frame Pulses sdh_fp0, sdh_fp1, p0_fp0, p0_fp1 synchronized to active sync reference.p0_fp0, p0_fp1 not aligned to sync reference.Supported Output Clock Frequencies As listed in Table 4As listed in Table 4 for p0_clk0, p0_clk1, p1_clk0, p1_clk1Supported Output Frame Pulse Frequencies As listed in Table 4As listed in Table 4 for p0_fp0, p0_fp not aligned to sync reference.External Pins Status IndicatorsLock, HoldoverNoneTable 1 - DPLL1 and DPLL2 FeaturesZL30119Data Sheet1.2 DPLL Mode ControlBoth DPLL1 and DPLL2 independently support three modes of operation - free-run, normal and holdover. The mode of operation can be manually set or controlled by an automatic state machine as shown in Figure 2.Figure 2 - Automatic Mode State MachineFree-runThe free-run mode occurs immediately after a reset cycle or when the DPLL has never been synchronized to areference input. In this mode, the frequency accuracy of the output clocks is equal to the frequency accuracy of the external master oscillator. Lock AcquisitionThe input references are continuously monitored for frequency accuracy and phase regularity. If at least one of the input references is qualified by the reference monitors, then the DPLL will begin lock acquisition on that input. Given a stable reference input, the ZL30119 will enter in the Normal (locked) mode.Normal (locked)The usual mode of operation for the DPLL is the normal mode where the DPLL phase locks to a selected qualified reference input and generates output clocks and frame pulses with a frequency accuracy equal to the frequency accuracy of the reference input. While in the normal mode, the DPLL’s clock and frame pulse outputs comply with the MTIE and TDEV wander generation specifications as described in Telcordia and ITU-T telecommunication standards.HoldoverWhen the DPLL operating in the normal mode loses its reference input, and no other qualified references are available, it will enter the holdover mode and continue to generate output clocks based on historical frequency data collected while the DPLL was synchronized.ResetAnother reference is qualified and availablefor selectionPhase lock on the selected reference is achievedLock AcquisitionNormal (Locked)No references are qualified and available for selectionFree-RunHoldoverSelected referencefailsAll references are monitored for frequency accuracy and phase regularity, and at least one reference is qualified.Normal (Locked)ZL30119Data Sheet1.3 Ref and Sync InputsThere are eight reference clock inputs (ref0 to ref7) available to both DPLL1 and DPLL2. The selected reference input is used to synchronize the output clocks. Each of the DPLLs have independent reference selectors which can be controlled using a built-in state machine or set in a manual mode.Figure 3 - Reference and Sync InputsIn addition to the reference inputs, DPLL1 has three optional frame pulse synchronization inputs (sync0 to sync2)used to align the output frame pulses. The sync n input is selected with its corresponding ref n input, where n = 0, 1,or 2. Note that the sync input cannot be used to synchronize the DPLL, it only determines the alignment of the frame pulse outputs. An example of output frame pulse alignment is shown in Figure 4.Figure 4 - Output Frame Pulse Alignmentref7:0sync2:0DPLL2DPLL1ref nsdh/p0/p1_clk xsdh/p0_fp xWithout a frame pulse signal at the sync input, the output frame pulses will align to any arbitrary cycle of its associated output clock.sync n - no frame pulse signal presentWhen a frame pulse signal is present at the sync input, the DPLL will align the output frame pulses to the output clock edge that is aligned to the input frame pulse.ref n sdh/p0/p1_clk xsdh/p0_fp xsync nn = 0, 1, 2x = 0, 1n = 0, 1, 2x = 0, 1ZL30119Data Sheet Each of the ref inputs accept a single-ended LVCMOS clock with a frequency ranging from 2kHz to 77.76MHz. Built-in frequency detection circuitry automatically determines the frequency of the reference if its frequency is within the set of pre-defined frequencies as shown in Table 2. Custom frequencies definable in multiples of 8kHz are also available.2 kHz8 kHz64 kHz1.544 MHz2.048 MHz6.48 MHz8.192 MHz16.384 MHz19.44 MHz38.88 MHz77.76 MHzCustom ACustom BTable 2 - Set of Pre-Defined Auto-Detect Clock FrequenciesEach of the sync inputs accept a single-ended LVCMOS frame pulse. Since alignment is determined from the rising edge of the frame pulse, there is no duty cycle restriction on this input, but there is a minimum pulse width requirement of 5 ns. Frequency detection for the sync inputs is automatic for the supported frame pulse frequencies shown in Table 3.166.67 Hz(48x 125 µs frames)400 Hz1 kHz2 kHz8 kHz64 kHzTable 3 - Set of Pre-Defined Auto-Detect Sync Frequencies1.4 Ref and Sync MonitoringAll input references (ref0 to ref7) are monitored for frequency accuracy and phase regularity. New references are qualified before they can be selected as a synchronization source, and qualified references are continuously monitored to ensure that they are suitable for synchronization. The process of qualifying a reference depends on four levels of monitoring.Single Cycle Monitor (SCM)The SCM block measures the period of each reference clock cycle to detect phase irregularities or a missing clock edge. In general, if the measured period deviates by more than 50% from the nominal period, then an SCM failure (scm_fail) is declared.ZL30119Data SheetCoarse Frequency Monitor (CFM)The CFM block monitors the reference frequency over a measurement period of 30 µs so that it can quickly detect large changes in frequency. A CFM failure (cfm_fail) is triggered when the frequency has changed by more than 3%or approximately 30000ppm.Precise Frequency Monitor (PFM)The PFM block measures the frequency accuracy of the reference over a 10 second interval. To ensure an accurate frequency measurement, the PFM measurement interval is re-initiated if phase or frequency irregularities are detected by the SCM or CFM. The PFM provides a level of hysteresis between the acceptance range and the rejection range to prevent a failure indication from toggling between valid and invalid for references that are on the edge of the acceptance range.When determining the frequency accuracy of the reference input, the PFM uses the external oscillator’s output frequency (f ocsi ) as its point of reference. Guard Soak Timer (GST)The GST block mimics the operation of an analog integrator by accumulating failure events from the CFM and the SCM blocks and applying a selectable rate of decay when no failures are detected.As shown in Figure 5, a GST failure (gst_fail) is triggered when the accumulated failures have reached the upper threshold during the disqualification observation window. When there are no CFM or SCM failures, the accumulator decrements until it reaches its lower threshold during the qualification window.Figure 5 - Behaviour of the Guard Soak Timer during CFM or SCM FailuresAll sync inputs (sync0 to sync2) are continuously monitored to ensure that there is a correct number of reference clock cycles within the frame pulse period.1.5 Output Clocks and Frame PulsesThe ZL30119 offers a wide variety of outputs including two low-jitter differential LVPECL clocks (diff0_p/n,diff1_p/n ), two SONET/SDH LVCMOS (sdh_clk0, sdh_clk1) output clocks and four programmable LVCMOS (p0_clk0, p0_clk1, p1_clk0, p1_clk1) output clocks. In addition to the clock outputs, two LVCMOS SONET/SDH frame pulse outputs (sdh_fp0, sdh_fp1) and two LVCMOS programmable frame pulses (p0_fp0, p0_fp1) are also available.refCFM or SCM failuresupper thresholdlower thresholdt d - disqualification timet q - qualification time = n * t dt dt qgst_failZL30119Data SheetThe feedback clock (fb_clk ) of DPLL1 is available as an output clock. Its output frequency is always equal to DPLL1’s selected input frequency.The output clocks and frame pulses derived from the SONET/SDH APLL are always synchronous with DPLL1, and the clocks and frame pulses generated from the programmable synthesizers can be synchronized to either DPLL1or DPLL2. This allows the ZL30119 to have two independent timing paths.Figure 6 - Output Clock ConfigurationThe supported frequencies for the output clocks and frame pulses are shown in Table 4.diff0_p/n, diff1_p/n (LVPECL)sdh_clk0, sdh_clk1(LVCMOS)p0_clk0, p1_clk0(LVCMOS)p0_clk1, p1_clk1(LVCMOS)sdh_fp0, shd_fp1, p0_fp0, p0_fp1(LVCMOS)6.48 MHz 6.48 MHz 2 kHz p x _clk0 p x _clk1 =2M166.67 Hz (48x 125 µs frames)19.44 MHz 9.72 MHz N * 8 kHz (up to 77.76 MHz)400 Hz 38.88 MHz 12.96 MHz 1 kHz 51.84 MHz 19.44 MHz 2 kHz 77.76 MHz 25.92 MHz 4 kHz 155.52 MHz 38.88 MHz 8 kHz 311.04 MHz 51.84 MHz 32 kHz 622.08 MHz77.76 MHz64 kHzTable 4 - Output Clock and Frame Pulse FrequenciesDPLL2p0_clk0p0_fp0p0_clk1p0_fp1 P0 SynthesizerDPLL1p1_clk0p1_clk1P1 Synthesizersdh_clk0sdh_fp0sdh_clk1sdh_fp1SONET/SDHAPLLdiff0diff1Feedback Synthesizerfb_clkZL30119Data Sheet1.6 Configurable Input-to-Output and Output-to-Output DelaysThe ZL30119 allows programmable static delay compensation for controlling input-to-output and output-to-output delays of its clocks and frame pulses.All of the output synthesizers (SONET/SDH, P0, P1, Feedback) locked to DPLL1 can be configured to lead or lag the selected input reference clock using the DPLL1 Fine Delay . The delay is programmed in steps of 119.2ps with a range of -128 to +127 steps giving a total delay adjustment in the range of -15.26ns to +15.14ns. Negative values delay the output clock, positive values advance the output clock. Synthesizers that are locked to DPLL2 are unaffected by this delay adjustment.In addition to the fine delay introduced in the DPLL1 path, the SONET/SDH, P0, and P1 synthesizers have the ability to add their own fine delay adjustments using the P0 Fine Delay , P1 Fine Delay , and SDH Fine Delay .These delays are also programmable in steps of 119.2ps with a range of -128 to +127 steps.In addition to these delays, the single-ended output clocks of the SONET/SDH, P0, and P1 synthesizers can be independently offset by 90, 180 and 270 degrees using the Coarse Delay , and the SONET/SDH differential outputs can be independently delayed by -1.6ns, 0ns, +1.6ns or +3.2ns using the Diff Delay . The output frame pulses (SONET/SDH, P0) can be independently offset with respect to each other using the FP Delay .Figure 7 - Phase Delay AdjustmentsDPLL1DPLL2P0 Fine Delayp0_clk0p0_clk1p0_fp0p0_fp1 P0 SynthesizerCoarse DelayCoarse Delay FP Delay FP Delay fb_clkp1_clk0p1_clk1 P1 Fine DelayDiff Delay Diff Delaydiff0diff1 SONET/SDHAPLLsdh_clk0sdh_clk1sdh_fp0sdh_fp1 SDH Fine DelayFeedback SynthesizerDPLL1 Fine DelayCoarse Delay Coarse Delay FP Delay FP DelayCoarse Delay Coarse DelayP1 Synthesizer。

ZY1730芯片说明书

ZY1730芯片说明书


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EG3014全中文资料

EG3014全中文资料

ELECTRONIC GIANT EG3014芯片数据手册大功率MOS管、IGBT管栅极驱动芯片版本变更记录目录1. 特点 (4)2. 描述 (4)3. 应用领域 (4)4. 引脚 (4)4.1. 引脚定义 (4)4.2. 引脚描述 (4)5. 结构框图 (5)6. 典型应用电路 (5)7. 电气特性 (7)7.1 极限参数 (7)7.2 典型参数 (8)7.3 开关时间特性及死区时间波形图 (9)8. 应用设计 (10)8.1Vcc端电源电压 (10)8.2输入逻辑信号要求和输出驱动器特性 (10)8.3自举电路 (11)9. 封装尺寸 (12)9.1 SO8封装尺寸 (12)EG3014芯片数据手册V1.01. 特点⏹高端悬浮自举电源设计，耐压可达100V⏹内建死区控制电路⏹自带闭锁功能，彻底杜绝上、下管输出同时导通⏹采用半桥达林顿管输出结构具有大电流栅极驱动能力⏹专用于无刷电机N沟道MOS管、IGBT管栅极驱动⏹HIN输入通道高电平有效，控制高端HO输出⏹LIN输入通道高电平有效，控制低端LO输出⏹外围器件少⏹静态电流小：4.5mA⏹封装形式：SOP-82. 描述EG3014是一款高性价比的大功率MOS管、IGBT管栅极驱动专用芯片，内部集成了逻辑信号输入处理电路、死区时控制电路、闭锁电路、电平位移电路、脉冲滤波电路及输出驱动电路，专用于无刷电机控制器中的驱动电路。

EG3014高端的工作电压可达100V，Vcc的电源电压范围宽可达30V，静态功耗低仅4.5mA。

该芯片具有闭锁功能防止输出功率管同时导通，输入通道H IN和L IN内建了一个10K下拉电阻，在输入悬空时使上、下功率MOS管处于关闭状态，输出结构采用半桥式达林顿管结构,采用SOP8封装。

3. 应用领域⏹电动摩托车控制器⏹电动自行车控制器⏹100V降压型开关电源⏹变频水泵控制器⏹无刷电机驱动器⏹高压Class-D类功放4. 引脚4.1. 引脚定义IN IN图4-1. EG3014管脚定义4.2. 引脚描述5. 结构框图H LOGNDVccHOVS VBL图5-1. EG3014结构框图6. 典型应用电路+15V+VinH L OUT图6-1. EG3014典型应用电路图——中、小功率半桥驱动应用+15V+VinH L OUT图6-2. EG3014典型应用电路图——大功率电机场合应用+15V+VinH L OUT图6-3. EG3014典型应用电路图——外接自举二极管应用7. 电气特性7.1 极限参数注：超出所列的极限参数可能导致芯片内部永久性损坏，在极限的条件长时间运行会影响芯片的可靠性。

zl38003中文资料_数据手册_IC数据表

zl38003中文资料_数据手册_IC数据表

Features
• Handles up to -6 dB acoustic echo return loss
• 127 ms acoustic echo canceller
• Provides up to 12 dB of Noise Reduction
• Operate in two modes, Dual Analog mode and single Analog mode (other port is digital PCM)
The AEC uses an advanced adaptive filter algorithm that is double-talk stable, allowing convergence even while both parties are talking. This algorithm continually tracks changes in the echo path, regardless of double-talk, as long as a reference signal is available for the echo canceller.
• PCM Data Formats in single Port mode- 16-bit Linear, companded ITU-T A-law or U-law
• Advanced NLP design - full duplex speech with no switched loss on audio paths
MT93L16
ZL38001
ZL38002
ZL38003
Description AEC for analog hands- AEC for analog hands- AEC with noise reduction for digital