Rockchip Pin-Ctrl 开发指南 V1.0-20160725

SP601 Hardware User GuideUG518 (v1.7) September 26, 2012© Copyright 2009–2012 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. DISCLAIMERThe information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. 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Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical Applications:/warranty.htm#critapps.Revision HistoryThe following table shows the revision history for this document.Date Version Revision07/15/09 1.0Initial Xilinx release.08/19/09 1.1•Added Appendix B, VITA 57.1 FMC LPC Connector Pinout.•Updated Figure1-17.•Updated Table1-4, Table1-19, and Table1-22.•Added introductory paragraph to Appendix C, SP601 Master UCF.•Miscellaneous typographical edits and new user guide template.05/17/10 1.2•Updated Figure1-1, Figure1-2, Figure1-14, Figure1-18, Table1-9, Table1-1,Table1-11, and Table1-16.•Added Figure1-7, Figure1-8, and Table1-13.•Updated 9. VITA 57.1 FMC-LPC Connector, page25, Appendix B, VITA 57.1 FMCLPC Connector Pinout, and Appendix C, SP601 Master UCF.06/16/10 1.3Reversed order of 15. Configuration Options and 16. Power Management. Updated 1.Spartan-6 XC6SLX16-2CSG324 FPGA and 2. 128 MB DDR2 Component Memory. AddedTable1-26. Added UG394, Spartan-6 FPGA Power Management User Guide to Appendix D,References.09/24/10 1.4Added Power System Test Points, including Table1-25.02/16/11 1.5Added note and revised header description to indicate the I/Os support LVCMOS25signaling on page34. Revised oscillator manufacturer information from Epson to SiTimeon page page23 and page51.07/18/11 1.6Corrected wording from “PPM frequency jitter” to “PPM frequency stability” in sectionOscillator (Differential), page23. Added Table1-15, page27.09/26/12 1.7Added Regulatory and Compliance Information, page53.SP601 Hardware User Guide UG518 (v1.7) September 26, 2012SP601 Hardware User Guide 3UG518 (v1.7) September 26, 2012Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Preface: About This GuideGuide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Additional Support Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Chapter 1: SP601 Evaluation BoardOverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Additional Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Related Xilinx Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101. Spartan-6 XC6SLX16-2CSG324 FPGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11I/O Voltage Rails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122. 128 MB DDR2 Component Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123. SPI x4 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154. Linear Flash BPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175. 10/100/1000 Tri-Speed Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196. USB-to-UART Bridge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217. IIC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228-Kb NV Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228. Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Oscillator (Differential). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Oscillator Socket (Single-Ended, 2.5V or 3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24SMA Connectors (Differential). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249. VITA 57.1 FMC-LPC Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2510. Status LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2811. FPGA Awake LED and Suspend Jumper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2912. FPGA INIT and DONE LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3013. User I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3114. FPGA_PROG_B Pushbutton Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3515. Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36JTAG Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3616. Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37AC Adapter and 5V Input Power Jack/Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Onboard Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Power System Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Table of ContentsAppendix A: Default Jumper and Switch SettingsAppendix B: VITA 57.1 FMC LPC Connector PinoutAppendix C: SP601 Master UCFAppendix D: ReferencesAppendix E: Regulatory and Compliance InformationDirectives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Standards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Electromagnetic Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 SP601 Hardware User GuideUG518 (v1.7) September 26, 2012SP601 Hardware User Guide 5UG518 (v1.7) September 26, 2012PrefaceAbout This GuideThis manual accompanies the Spartan®-6 FPGA SP601 Evaluation Board and contains information about the SP601 hardware and software tools.Guide ContentsThis manual contains the following chapters:•Chapter 1, SP601 Evaluation Board , provides an overview of the SP601 evaluation board and details the components and features of the SP601 board.•Appendix A, Default Jumper and Switch Settings .•Appendix B, VITA 57.1 FMC LPC Connector Pinout .•Appendix C, SP601 Master UCF .•Appendix D, References .Additional DocumentationThe following documents are available for download at /products/spartan6.•Spartan-6 Family OverviewThis overview outlines the features and product selection of the Spartan-6 family.•Spartan-6 FPGA Data Sheet: DC and Switching CharacteristicsThis data sheet contains the DC and switching characteristic specifications for the Spartan-6 family.•Spartan-6 FPGA Packaging and Pinout SpecificationsThis specification includes the tables for device/package combinations and maximum I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications.•Spartan-6 FPGA Configuration User GuideThis all-encompassing configuration guide includes chapters on configuration interfaces (serial and parallel), multi-bitstream management, bitstream encryption, boundary-scan and JTAG configuration, and reconfiguration techniques.•Spartan-6 FPGA SelectIO Resources User GuideThis guide describes the SelectIO™ resources available in all Spartan-6 devices.•Spartan-6 FPG A Clocking Resources User GuidePreface:About This GuideThis guide describes the clocking resources available in all Spartan-6 devices,including the DCMs and PLLs.•Spartan-6 FPGA Block RAM Resources User GuideThis guide describes the Spartan-6 device block RAM capabilities.•Spartan-6 FPGA DSP48A1 Slice User GuideThis guide describes the architecture of the DSP48A1 slice in Spartan-6FPGAs andprovides configuration examples.•Spartan-6 FPGA Memory Controller User GuideThis guide describes the Spartan-6 FPGA memory controller block, a dedicatedembedded multi-port memory controller that greatly simplifies interfacingSpartan-6FPGAs to the most popular memory standards.•Spartan-6 FPGA PCB Designer’s GuideThis guide provides information on PCB design for Spartan-6 devices, with a focus onstrategies for making design decisions at the PCB and interface level.Additional Support ResourcesTo search the database of silicon and software questions and answers or to create atechnical support case in WebCase, see the Xilinx website at:/support. SP601 Hardware User GuideUG518 (v1.7) September 26, 2012Chapter1 SP601 Evaluation BoardOverviewThe SP601 board enables hardware and software developers to create or evaluate designstargeting the Spartan®-6 XC6SLX16-2CSG324 FPGA.The SP601 provides board features for evaluating the Spartan-6 family that are common tomost entry-level development environments. Some commonly used features include aDDR2 memory controller, a parallel linear flash, a tri-mode Ethernet PHY, general-purposeI/O (GPIO), and a UART. Additional functionality can be added through the VITA 57.1.1expansion connector. Features, page8 provides a general listing of the board features withdetails provided in Detailed Description, page10.Additional InformationAdditional information and support material is located at:•/sp601This information includes:•Current version of this user guide in PDF format•Example design files for demonstration of Spartan-6 FPGA features and technology•Demonstration hardware and software configuration files for the SP601 linear and SPImemory devices•Reference Design Files•Schematics in PDF format and DxDesigner schematic format•Bill of materials (BOM)•Printed-circuit board (PCB) layout in Allegro PCB format•Gerber files for the PCB (Many free or shareware Gerber file viewers are available onthe internet for viewing and printing these files.)•Additional documentation, errata, frequently asked questions, and the latest newsFor information about the Spartan-6 family of FPGA devices, including product highlights,data sheets, user guides, and application notes, see the Spartan-6 FPGA website at/support/documentation/spartan-6.htm.SP601 Hardware User Guide 7 UG518 (v1.7) September 26, 2012Chapter 1:SP601 Evaluation BoardFeaturesThe SP601 board provides the following features (see Figure1-2 and Table1-1):• 1. Spartan-6 XC6SLX16-2CSG324 FPGA• 2. 128 MB DDR2 Component Memory• 3. SPI x4 Flash• 4. Linear Flash BPI• 5. 10/100/1000 Tri-Speed Ethernet PHY•7. IIC Bus•8Kb NV memory•External access 2-pin header•VITA 57.1 FMC-LPC connector•8. Clock Generation•Oscillator (Differential)•Oscillator Socket (Single-Ended, 2.5V or 3.3V)•SMA Connectors (Differential)•9. VITA 57.1 FMC-LPC Connector•10. Status LEDs•FPGA_AWAKE•INIT•DONE•13. User I/O•User LEDs•User DIP switch•User pushbuttons•GPIO male pin header•14. FPGA_PROG_B Pushbutton Switch•15. Configuration Options• 3. SPI x4 Flash (both onboard and off-board)• 4. Linear Flash BPI•JTAG Configuration•16. Power Management•AC Adapter and 5V Input Power Jack/Switch•Onboard Power Supplies SP601 Hardware User GuideUG518 (v1.7) September 26, 2012Related Xilinx DocumentsBlock DiagramFigure1-1 shows a high-level block diagram of the SP601 and its peripherals.Figure 1-1:SP601 Features and BankingRelated Xilinx DocumentsPrior to using the SP601 Evaluation Board, users should be familiar with Xilinx resources.See the following locations for additional documentation on Xilinx tools and solutions:•ISE: /ise•Answer Browser: /support•Intellectual Property: /ipcenterSP601 Hardware User Guide 9 UG518 (v1.7) September 26, 2012SP601 Hardware User GuideUG518 (v1.7) September 26, 2012Chapter 1:SP601 Evaluation BoardDetailed DescriptionFigure 1-2 shows a board photo with numbered features corresponding to Table 1-1 and the section headings in this document.The numbered features in Figure 1-2 correlate to the features and notes listed in Table 1-1.Figure 1-2:SP601 Board PhotoUG518_02_09100912843126137115109141581316Table 1-1:SP601 FeaturesNumberFeatureNotesSchematic Page1 Spartan-6 FP G A XC6SLX16-2CS G 3242DDR2 Component Elpida EDE1116ACBG 1Gb DDR2SDRAM53SPI x4 Flash and Headers SPI select and External Headers 84Linear Flash BPIStrataFlash 8-bit (J3 device), 3 pins shared w/ SPI x481. Spartan-6 XC6SLX16-2CSG 324 FPGAA Xilinx Spartan-6 XC6SLX16-2CSG324 FPGA is installed on the SP601 Evaluation Board.ReferencesSee the Spartan-6 FPGA Data Sheet . [Ref 1]ConfigurationThe SP601 supports configuration in the following modes:•Master SPI x4•Master SPI x4 with off-board device •BPI•JTAG (using the included USB-A to Mini-B cable)For details on configuring the FPGA, see 15. Configuration Options .The Mode DIP switch SW2 is set to M[1:0] = 01 Master SPI default.ReferencesSee the Spartan-6 FPGA Configuration User Guide for more information. [Ref 2]510/100/1000 Ethernet PHY GMII Marvell Alaska PHY76RS232 UART (USB Bridge)Uses CP2103 Serial-to-USB connection 107IICGoes to Header and VITA 57.1 FMC 108Clock, socket, SMA Differential, Single-Ended, Differential 99VITA 57.1 FMC-LPC connector LVDS signals, clocks, PRSNT 610LEDs Ethernet PHY Status711LED, Header FPGA Awake LED, Suspend Header 812LEDs FPGA INIT, DONE 913LED User I/O (active-High)9DIP SwitchUser I/O (active-High)9PushbuttonUser I/O, CPU_RESET (active-High)912-pin (8 I/O) Header6 pins x 2 male header with 8 I/Os (active-High)1014Pushbutton FPGA_PROG_B915USB JTAG Cypress USB to JTAG download cable logic14, 1516Onboard PowerPower Management11,12,13Table 1-1:SP601 Features (Cont’d)NumberFeatureNotesSchematic PageSP601 Hardware User Guide I/O Voltage RailsThere are four available banks on the LX16-CSG324 device. Banks 0, 1, and 2 are connected for 2.5V I/O. Bank 3 is used for the 1.8V DDR2 component memory interface of Spartan-6 FPGA’s hard memory controller. The voltage applied to the FPGA I/O banks used by the SP601 board is summarized in Table 1-2.ReferencesSee the Spartan-6 FPGA documentation for more information at /support/documentation/spartan-6.htm .2. 128 MB DDR2 Component MemoryThere are 128MB of DDR2 memory available on the SP601 board. A 1-Gb ElpidaEDE1116ACBG (84-ball) DDR2 memory component is accessible through Bank 3 of the LX16 device. The Spartan-6 FPGA hard memory controller is used for data transfer across the DDR2 memory interface’s 16-bit data path using SSTL18 signaling. The SP601 board supports the “standard” VCCINT setting of 1.20V ± 5%. This setting provides the standard memory controller block (MCB) performance of 625Mb/s for DDR2 memory in a -2 speed grade device. Signal integrity is maintained through DDR2 resistor terminations and memory on-die terminations (ODT), as shown in Table 1-3 and Table 1-4.Table 1-2:I/O Voltage Rail of FPGA BanksFPGA BankI/O Voltage Rail0 2.5V 1 2.5V 2 2.5V 31.8VTable 1-3:Termination Resistor RequirementsSignal NameBoard TerminationOn-Die TerminationDDR2_A[14:0]49.9Ω to V TT DDR2_BA[2:0]49.9Ω to V TT DDR2_RAS_N 49.9Ω to V TT DDR2_CAS_N 49.9Ω to V TT DDR2_WE_N 49.9Ω to V TT DDR2_CS_N 100Ω to GND DDR2_CKE 4.7K Ω to GND DDR2_ODT 4.7K Ω to GNDDDR2_DQ[15:0]ODT DDR2_UDQS[P ,N], DDR2_LDQS[P ,N]ODT DDR2_UDM, DDR2_LDMODTTable 1-5 shows the connections and pin numbers for the DDR2 Component Memory.DDR2_CK[P ,N]100Ω differential at memorycomponentNotes:1.Nominal value of V TT for DDR2 interface is 0.9V .Table 1-4:FPGA On-Chip (OCT) Termination External Resistor Requirements FPGA U1 PinFPGA Pin NumberBoard Connection for OCTZIO L6No Connect RZQC2100Ω to GROUNDTable 1-5:DDR2 Component Memory ConnectionsFPGA U1 PinSchematic Net Name Memory U2Pin NumberPin NameJ7DDR2_A0M8A0J6DDR2_A1M3A1H5DDR2_A2M7A2L7DDR2_A3N2A3F3DDR2_A4N8A4H4DDR2_A5N3A5H3DDR2_A6N7A6H6DDR2_A7P2A7D2DDR2_A8P8A8D1DDR2_A9P3A9F4DDR2_A10M2A10D3DDR2_A11P7A11G6DDR2_A12R2A12L2DDR2_DQ0G8DQ0L1DDR2_DQ1G2DQ1K2DDR2_DQ2H7DQ2K1DDR2_DQ3H3DQ3H2DDR2_DQ4H1DQ4H1DDR2_DQ5H9DQ5J3DDR2_DQ6F1DQ6Table 1-3:Termination Resistor Requirements (Cont’d)Signal NameBoard Termination On-Die TerminationSP601 Hardware User Guide ReferencesSee the Elpida DDR2 SDRAM Specifications for more information. [Ref 11]Also, see the Spartan-6 FPGA Memory Controller User Guide . [Ref 3]J1DDR2_DQ7F9DQ7M3DDR2_DQ8C8DQ8M1DDR2_DQ9C2DQ9N2DDR2_DQ10D7DQ10N1DDR2_DQ11D3DQ11T2DDR2_DQ12D1DQ12T1DDR2_DQ13D9DQ13U2DDR2_DQ14B1DQ14U1DDR2_DQ15B9DQ15F2DDR2_BA0L2BA0F1DDR2_BA1L3BA1E1DDR2_BA2L1BA2E3DDR2_WE_B K3WE L5DDR2_RAS_B K7RAS K5DDR2_CAS_B L7CAS K6DDR2_ODT K9ODT G3DDR2_CLK_P J8CK G1DDR2_CLK_N K8CK H7DDR2_CKE K2CKE L4DDR2_LDQS_P F7LDQS L3DDR2_LDQS_N E8LDQS P2DDR2_UDQS_P B7UDQS P1DDR2_UDQS_N A8UDQS K3DDR2_LDM F3LDM K4DDR2_UDMB3UDMTable 1-5:DDR2 Component Memory Connections (Cont’d)FPGA U1 PinSchematic Net Name Memory U2Pin NumberPin Name3. SPI x4 FlashThe Xilinx Spartan-6 FPGA hosts a SPI interface which is accessible to the Xilinx iMPACTconfiguration tool. The SPI memory device operates at 3.0V; the Spartan-6 FPGA I/Os are3.3V tolerant and provide electrically compatible logic levels to directly access the SPI flashthrough a 2.5V bank. The XC6SLX16-2CSG324 is a master device when accessing anexternal SPI flash memory device.The SP601 SPI interface has two parallel connected configuration options (see Figure1-4):an SPI X4 (Winbond W25Q64VSFIG) 64-Mb flash memory device and a flashprogramming header (J12). J12 supports a user-defined SPI mezzanine board. The SPIconfiguration source is selected via SPI select jumper J15. For details on configuring theFPGA, see 15. Configuration Options.Figure 1-3:J12 SPI Flash Programming HeaderSP601 Hardware User Guide ReferencesSee the Winbond Serial Flash Memory Data Sheet for more information. [Ref 12]See the XPS Serial Peripheral Interface Data Sheet for more information. [Ref 4]Figure 1-4:SPI Flash Interface TopologyTable 1-6:SPI x4 Memory ConnectionsFPGA U1 PinSchematic Net Name SPI MEM U17SPI HDR J12Pin #Pin NamePinNumberPin NameV2FPGA_PROG_B 1V14FPGA_D2_MISO31IO3_HOLD_B 2T14FPGA_D1_MISO2_R 9IO2_WP_B3V3SPI_CS_B4TMS T13FPGA_MOSI_CSI_B_MISO015DIN 5TDI R13FPGA_D0_DIN_MISO_MISO18IO1_DOUT6TDO R15FPGA_CCLK16CLK7TCK 8GND 9VCC3V3J15.2SPIX4_CS_B 7CS_B4. Linear Flash BPIAn 8-bit (16MB) Numonyx linear flash memory (TE28F128J3D-75) (J3D type) is used toprovide non-volatile bitstream, code, and data storage. The J3D devices operate at 3.0V; theSpartan-6 FPGA I/Os are 3.3V tolerant and provide electrically compatible logic levels todirectly access the linear flash BPI through a 2.5V bank. For details on configuring theFPGA, see 15. Configuration Options.Figure 1-5:Linear Flash BPI InterfaceTable 1-7:BPI Memory ConnectionsFPGA U1 Pin Schematic Net Name BPI Memory U10Pin Number Pin Name K18FLASH_A032A0K17FLASH_A128A1J18FLASH_A227A2J16FLASH_A326A3G18FLASH_A425A4G16FLASH_A524A5H16FLASH_A623A6H15FLASH_A722A7H14FLASH_A820A8H13FLASH_A919A9F18FLASH_A1018A10F17FLASH_A1117A11K13FLASH_A1213A12K12FLASH_A1312A13E18FLASH_A1411A14E16FLASH_A1510A15G13FLASH_A168A16SP601 Hardware User Guide Note:Memory U10 pin 56 address A24 is not connected on the 16 MB device. It is made availablefor larger density devices.ReferencesSee the Numonyx Embedded Flash Memory Data Sheet for more information. [Ref 13]In addition, see the Spartan-6 FPGA Configuration User Guide for more information. [Ref 2]H12FLASH_A177A17D18FLASH_A186A18D17FLASH_A195A19G14FLASH_A204A20F14FLASH_A213A21C18FLASH_A221A22C17FLASH_A2330A23F16FLASH_A2456A24R13FPGA_D0_DIN_MISO_MISO133DQ0T14FPGA_D1_MISO235DQ1V14FPGA_D2_MISO338DQ2U5FLASH_D340DQ3V5FLASH_D444DQ4R3FLASH_D546DQ5T3FLASH_D649DQ6R5FLASH_D751DQ7M16FLASH_WE_B 55WE_B L18FLASH_OE_B 54OE_B L17FLASH_CE_B14CE0B3FMC_PWR_GOOD_FLASH_RST_B16RP_BTable 1-7:BPI Memory Connections (Cont’d)FPGA U1 PinSchematic Net NameBPI Memory U10Pin NumberPin Name5. 10/100/1000 T ri-Speed Ethernet PHYThe SP601 uses the onboard Marvell Alaska PHY device (88E1111) for Ethernetcommunications at 10, 100, or 1000 Mb/s. The board supports a GMII/MII interface fromthe FPGA to the PHY. The PHY connection to a user-provided Ethernet cable is through aHalo HFJ11-1G01E RJ-45 connector with built-in magnetics.On power-up, or on reset, the PHY is configured to operate in GMII mode with PHYaddress 0b00111 using the settings shown in Table1-8. These settings can be overwrittenvia software commands passed over the MDIO interface.Table 1-8:PHY Configuration PinsPin Connection onBoardBit[2]Definition and ValueBit[1]Definition and ValueBit[0]Definition and ValueCFG0V CC 2.5V PHYADR[2] = 1PHYADR[1] = 1PHYADR[0] = 1 CFG1Ground ENA_PAUSE = 0PHYADR[4] = 0PHYADR[3] = 0 CFG2V CC 2.5V ANEG[3] = 1ANEG[2] = 1ANEG[1] = 1 CFG3V CC 2.5V ANEG[0] = 1ENA_XC = 1DIS_125 = 1 CFG4V CC 2.5V HWCFG_MD[2] = 1HWCFG_MD[1] = 1HWCFG_MD[0] = 1 CFG5V CC 2.5V DIS_FC = 1DIS_SLEEP = 1HWCFG_MD[3] = 1 CFG6PHY_LED_RX SEL_BDT = 0INT_POL = 175/50Ω = 0 Table 1-9:Ethernet PHY ConnectionsFPGA U1 Pin Schematic Net NameU3 M88E111Pin Number Pin NameP16PHY_MDIO33MDIO N14PHY_MDC35MDC J13PHY_INT32INT_B L13PHY_RESET36RESET_B M13PHY_CRS115CRS L14PHY_COL114COL L16PHY_RXCLK7RXCLK P17PHY_RXER8RXER N18PHY_RXCTL_RXDV4RXDV M14PHY_RXD03RXD0 U18PHY_RXD1128RXD1 U17PHY_RXD2126RXD2 T18PHY_RXD3125RXD3 T17PHY_RXD4124RXD4 N16PHY_RXD5123RXD5SP601 Hardware User GuideReferencesSee the Marvell Alaska Gigabit Ethernet Transceivers product page for more information.[Ref 16]Also, see the LogiCORE™ IP Tri-Mode Ethernet MAC User Guide . [Ref 5]N15PHY_RXD6121RXD6P18PHY_RXD7120RXD7A9 PHY_TXC_G TPCLK 14G TXCLKB9 PHY_TXCLK 10TXCLK A8 PHY_TXER 13TXER B8 PHY_TXCTL_TXEN 16TXEN F8 PHY_TXD018TXD0G 8 PHY_TXD119TXD1A6 PHY_TXD220TXD2B6 PHY_TXD324TXD3E6 PHY_TXD425TXD4F7 PHY_TXD526TXD5A5 PHY_TXD628TXD6C5 PHY_TXD729TXD7Table 1-9:Ethernet PHY Connections (Cont’d)FPGA U1 PinSchematic Net NameU3 M88E111Pin NumberPin Name6. USB-to-UART BridgeThe SP601 contains a Silicon Labs CP2103GM USB-to-UART bridge device (U4) which allows connection to a host computer with a USB cable. The USB cable is supplied in this evaluation kit (Type A end to host computer, Type Mini-B end to SP601 connector J9). Table 1-10 details the SP601 J9 pinout.Xilinx UART IP is expected to be implemented in the FPGA fabric. The FPGA supports the USB-to-UART bridge using four signal pins, transmit (TX), receive (RX), Request to Send (RTS), and Clear to Send (CTS).Silicon Labs provides royalty-free Virtual COM Port (VCP) drivers which permit the CP2103GM USB-to-UART bridge to appear as a COM port to host computercommunications application software (for example, HyperTerm or TeraTerm). The VCP device driver must be installed on the host PC prior to establishing communications with the SP601. Refer to the SP601 Getting Started Guide for driver installation instructions.ReferencesRefer to the Silicon Labs website for technical information on the CP2103GM and the VCP drivers.In addition, see some of the Xilinx UART IP specifications at:•/support/documentation/ip_documentation/xps_uartlite.pdf •/support/documentation/ip_documentation/xps_uart16550.pdfTable 1-10:USB Type B Pin Assignments and Signal DefinitionsUSB ConnectorPinSignal NameDescription1VBUS +5V from host system (not used)2USB_DATA_N Bidirectional differential serial data (N-side)3USB_DATA_P Bidirectional differential serial data (P-side)4GROUNDSignal groundTable 1-11:CP2103GM ConnectionsFPGA U1 PinUART Functionin FPGA Schematic Net Name U4 CP2103GMPinUART Function in CP2103GM U10RTS, output USB_1_CTS 22CTS, input T5CTS, input USB_1_RTS 23RTS, output L12TX, data out USB_1_RX 24RXD, data in K14RX, data inUSB_1_TX25TXD, data out。

ESP32硬件设计指南版本3.3乐鑫信息科技版权©2022关于本文档《ESP32硬件设计指南》主要提供了在使用ESP32系列产品进行电路设计和PCB布局时需注意的事项。

本文还简要介绍了ESP32系列产品的硬件信息，包括ESP32芯片、模组、开发板以及典型应用方案等。

文档版本请至乐鑫官网https:///zh-hans/support/download/documents下载最新版本文档。

修订历史请至文档最后页查看修订历史。

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证书下载用户可以通过乐鑫官网证书下载页面/zh-hans/certificates下载产品证书。

目录1产品概述12原理图设计2 2.1电源32.1.1数字电源32.1.2模拟电源52.1.3RTC电源5 2.2上电时序与复位62.2.1上电时序62.2.2复位6 2.3Flash（必选）及SRAM（可选）72.3.1SiP Flash及SiP PSRAM72.3.2外部Flash及片外RAM7 2.4时钟源72.4.1外部时钟参考（必选）82.4.2RTC时钟（可选）8 2.5射频(RF)9 2.6ADC9 2.7外置阻容10 2.8UART10 2.9SDIO11 2.10触摸传感器113版图布局12 3.1独立的ESP32模组的版图设计123.1.1版图设计通用要点123.1.2模组在底板上的位置摆放133.1.3电源143.1.4晶振163.1.5射频173.1.6Flash及PSRAM183.1.7外置阻容183.1.8UART183.1.9触摸传感器18 3.2ESP32作为从设备的版图设计20 3.3版图设计常见问题213.3.1为什么电源纹波并不大，但射频的TX性能很差？213.3.2为什么芯片发包时，电源纹波很小，但射频的TX性能不好？213.3.3为什么ESP32发包时，仪器测试到的power值比target power值要高很多或者低很多，且EVM比较差？213.3.4为什么芯片的TX性能没有问题，但RX的灵敏度不好？224开发硬件介绍235典型应用案例24 5.1ESP32智能音频平台245.1.1ESP32-LyraT音频开发板245.1.2ESP32-LyraTD-MSC音频开发板25 5.2ESP32触摸传感器方案—ESP32-Sense Kit26 5.3ESP-Mesh应用—ESP32-MeshKit27修订历史28插图1ESP32系列芯片参考设计原理图2 2四线3.3V内部flash核心电路图3 3VDD_SDIO电源管脚电路(1.8V)4 4VDD_SDIO电源管脚电路(3.3V)4 5VDD_SDIO电源管脚电路（外部电源供电）4 6ESP32系列芯片模拟电源5 7ESP32系列芯片RTC电源5 8ESP32芯片上电、复位时序图6 9ESP32晶振电路图8 10外置晶振电路图8 11外部激励信号电路图9 12ESP32射频匹配电路图9 13ESP32外置电容10 14ESP32串口11 15ESP32版图设计12 16ESP32模组在底板上的位置示意图13 17ESP32天线区域净空示意图14 18ESP32四层板电源设计15 19九宫格设计15 20ESP32两层板电源设计16 21ESP32晶振设计16 22ESP32四层板射频部分版图设计17 23ESP32两层板射频部分版图设计17 24ESP32Flash及PSRAM版图设计18 25ESP32UART设计18 26典型的触摸传感器应用19 27电极图形要求19 28传感器布局布线20 29PAD/TV Box平面位置规划框架20 30ESP32-LyraT俯视图24 31ESP32-LyraT仰视图25 32ESP32-LyraTD-MSC外观图26 33ESP32-Sense Kit开发套件26 34ESP32-MeshKit-Light灯27 35ESP32-MeshKit-Sense开发板271.产品概述ESP32是集成2.4GHz Wi-Fi和蓝牙双模的单芯片方案，采用台积电(TSMC)低功耗40纳米工艺，具有超高的射频性能、稳定性、通用性和可靠性，以及超低的功耗，满足不同的功耗需求，适用于各种应用场景。

龙芯2K1000处理器数据手册V1.22020年4月龙芯中科技术有限公司版权声明本文档版权归龙芯中科技术有限公司所有，并保留一切权利。

未经书面许可，任何公司和个人不得将此文档中的任何部分公开、转载或以其他方式散发给第三方。

否则，必将追究其法律责任。

免责声明本文档仅提供阶段性信息，所含内容可根据产品的实际情况随时更新，恕不另行通知。

如因文档使用不当造成的直接或间接损失，本公司不承担任何责任。

龙芯中科技术有限公司Loongson Technology Corporation Limited地址：北京市海淀区中关村环保科技示范园龙芯产业园2号楼Building No.2, Loongson Industrial Park, Zhongguancun Environmental Protection Park电话(Tel)：************传真(Fax)：************阅读指南《龙芯2K1000处理器数据手册》主要介绍龙芯2K1000处理器接口结构，特性，电气规范，以及硬件设计指导。

修订历史文档更新记录文档名: 龙芯2K1000处理器数据手册版本号：V1.2创建人: 芯片研发部创建日期: 2020-4更新历史序号. 更新日期版本号更新内容1 2017-7 V1.0 第一版2 2018-8 V1.1 1.增加CAMERA和VPU相关内容2.修改DVO0和UART2的复用关系3.更新LIO读写时序4.增加芯片分级信息3 2020-4 V1.2 1. 1.2.3节将DVO解释为通用并行显示接口2. 1.2.4节内存控制器功能描述修改3. 1.2.21节增加CAN总线描述内容4. 1.3节芯片工作温度更新5. 2.3节更正DVO0_CLKP/N与LIO_RDn/WRn的复用关系6. 2.6节USB接口功能描述修改7. 2.14节更正SDIO_DATA[3:0]与GPIO[39:36]复用关系8. 3.4节增加LIO波形图的说明9. 3.14节增加GMAC接口说明10.5.22节增加SATA/PCIE时钟特性11.第8章封装图改为矢量图，增加DIE位置信息12.增加第9章订货信息13.更新TBD相关内容手册信息反馈: *******************也可通过问题反馈网站/向我司提交芯片产品使用过程中的问题，并获取技术支持。

文档版本控制目录文档版本控制 (2)一、开发板简介 (6)二、AC7Z020核心板 (8)(一)简介 (8)(二)ZYNQ芯片 (9)(三)DDR3 DRAM (11)(四)QSPI Flash (14)(五)时钟配置 (16)(六)电源 (17)(七)结构图 (18)(八)连接器管脚定义 (19)三、扩展板 (23)(一)简介 (23)(二)CAN通信接口 (24)(三)485通信接口 (24)(四)千兆以太网接口 (25)(五)USB2.0 Host接口 (27)(六)USB转串口 (28)(七)AD输入接口 (29)(八)HDMI输出接口 (30)(九)MIPI摄像头接口(仅AX7Z020使用) (32)(十)SD卡槽 (33)(十一)EEPROM (34)(十二)实时时钟 (34)(十三)温度传感器 (35)(十四)JTAG接口 (36)(十五)用户LED灯 (36)(十六)用户按键 (37)(十七)扩展口 (38)(十八)供电电源 (40)(十九)底板结构图 (41)芯驿电子科技（上海）有限公司 基于XILINX ZYNQ7000开发平台的开发板（型号： AX7Z020B ）2022款正式发布了，为了让您对此开发平台可以快速了解，我们编写了此用户手册。

这款ZYNQ7000 FPGA 开发平台采用核心板加扩展板的模式，方便用户对核心板的二次开发利用。

核心板使用XILINX 的Zynq7000 SOC 芯片的解决方案，它采用ARM+FPGA SOC 技术将双核ARM Cortex-A9 和FPGA 可编程逻辑集成在一颗芯片上。

另外核心板上含有2片共512MB 高速DDR3 SDRAM 芯片和1片256Mb 的QSPI FLASH 芯片。

在底板设计上我们为用户扩展了丰富的外围接口，比如2路CAN 通信接口，2路485通信接口，2路XADC 输入接口， 1路千兆以太网接口，1路USB2.0 HOST 接口，1路HDMI输出接口，Uart 通信接口，SD 卡座，40针扩展接口等等。

简介ROC-RK3566-PC开发板采用HYM8563作为RTC(Real Time Clock)，HYM8563是一款低功耗CMOS实时时钟/日历芯片,它提供一个可编程的时钟输出,一个中断输出和一个掉电检测器,所有的地址和数据都通过I2C总线接口串行传递。

最大总线速度为400Kbits/s,每次读写数据后,内嵌的字地址寄存器会自动递增可计时基于32.768kHz晶体的秒,分,小时,星期,天,月和年宽工作电压范围:1.0~5.5V低休眠电流:典型值为0.25μA(VDD=3.0V,TA=25°C)内部集成振荡电容漏极开路中断引脚RTC驱动Android SDK中的DTS配置参考:kernel/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dtsi&i2c2{status="okay";hym8563:hym8563@51{status="okay";compatible="haoyu,hym8563";reg=<0x51>;#clock-cells=<0>;rtc-irq-gpio=<&gpio0RK_PC1IRQ_TYPE_EDGE_FALLING>;clock-frequency=<32768>;//clock-output-names="xin32k";/*rtc_int is not connected*/};};接口使用Linux提供了三种用户空间调用接口。

在ROC-RK3566-PC开发板中对应的路径为：SYSFS接口：/sys/class/rtc/rtc0/PROCFS接口：/proc/driver/rtcIOCTL接口：/dev/rtc0SYSFS接口可以直接使用cat和echo操作/sys/class/rtc/rtc0/下面的接口。

龙芯2K1000处理器用户手册V1.22020年4月龙芯中科技术有限公司版权声明本文档版权归龙芯中科技术有限公司所有，并保留一切权利。

未经书面许可，任何公司和个人不得将此文档中的任何部分公开、转载或以其他方式散发给第三方。

否则，必将追究其法律责任。

免责声明本文档仅提供阶段性信息，所含内容可根据产品的实际情况随时更新，恕不另行通知。

如因文档使用不当造成的直接或间接损失，本公司不承担任何责任。

龙芯中科技术有限公司Loongson Technology Corporation Limited地址：北京市海淀区中关村环保科技示范园龙芯产业园2号楼Building No.2, Loongson Industrial Park, Zhongguancun Environmental Protection Park电话(Tel)：************传真(Fax)：************阅读指南《龙芯2K1000处理器用户手册》主要介绍龙芯2K1000架构与寄存器描述，对芯片系统架构、主要模块的功能与配置、寄存器列表及位域进行详细说明。

关于龙芯2K1000处理器所集成的LS264高性能处理器核的相关资料，请参阅《龙芯GS264处理器核用户手册》。

修订历史文档更新记录文档名：龙芯2K1000处理器用户手册版本号：V1.2创建人：芯片研发部创建日期：2020-4更新历史序号. 更新日期版本号更新内容1 2017-7 V1.0 第一版2 2018-8 V1.1 1.修改DVO09-12引脚与UART2的复用关系2.增加hpet_int_mode寄存器，LIO iopf_en寄存器设置为保留3.增加温度传感器的章节4.增加hpet1_int、hpet2_int、vpu_int和cam_int5.增加intpol相关内容，增加intpol和intedge可读属性6.更新LIO读写时序7.列举已验证NAND型号8.列举已验证SDIO型号进行说明9.增加VPU解码器10.增加CAMERA接口控制器11.其他细节的改动3 2020-4 V1.2 1.第一章概述增加温度传感器说明2. 1.2.5节将DVO解释为通用并行显示接口3. 1.2.22节增加CAN总线描述内容4.表2-28中SDIO_DATA与GPIO复用关系修复5.修改5.2节关于uart0/1/2_enable的说明6.修复表9-2中Intpol_0/1关于中断极性描述手册信息反馈: *******************也可通过问题反馈网站/向我司提交芯片产品使用过程中的问题，并获取技术支持。

RK3288 HardwareDesign Guide作者：瑞芯硬件组文档版本：V1.0发布日期：2014-06-25免责声明您购买的产品、服务或特性等应受瑞芯微公司商业合同和条款的约束，本文档中描述的全部或部分产品、服务或特性可能不在您的购买或使用范围之内。

除非合同另有约定，瑞芯微公司对本文档内容不做任何明示或默示的声明或保证。

由于产品版本升级或其他原因，本文档内容会不定期进行更新。

除非另有约定，本文档仅作为使用指导，本文档中的所有陈述、信息和建议不构成任何明示或暗示的担保。

商标声明Rockchip、Rockchip TM图标、瑞芯微和其他瑞芯微商标均为福州瑞芯微电子有限公司的商标，并归瑞芯微电子有限公司所有。

本文档提及的其他所有商标或注册商标，由各自的所有人拥有。

版权所有? 福州市瑞芯微电子有限公司2014非经本公司书面许可，任何单位和个人不得擅自摘抄、复制本文档内容的部分或全部，并不得以任何形式传播。

福州市瑞芯微电子有限公司Fuzhou Rockchips Semiconductor Co . , Ltd地址：福建省福州市铜盘路软件园A区18号网址：客户服务电话：+86-591-83991906客户服务传真：+86-591-83951833客户服务邮箱：ForewordOverview本文档主要介绍RK3288硬件设计的要点及注意点，旨在帮助RK客户缩短产品的设计周期、保证产品的设计稳定性及降低故障率。

请客户严格按照本指南的要求进行硬件设计，同时尽量使用RK发布的相关核心模板。

如因模具原因确实需要修改核心模板的，设计需取得RK工程师的确认。

Product Version本文档对应的产品版本如下：产品名称产品版本RK3288Product Object本文档主要适用于以下工程师：单板硬件开发工程师技术支持工程师测试工程师Revision History修订记录累积了每次文档更新的说明。

最新版本的文档包含以前说有文档版本的更新内容。

JettaTechnical Reference ManualBriefRevision 1.0February 2011Fuzhou Rockchip Electronics Co.LtdRevision History Date Revision Description 2011-12-29 0.0 Initial Release2012-02-06 1.0 Update the description mistakeTABLE OF CONTENTRevision History (2)TABLE OF CONTENT (3)Chapter 1 Introduction (4)1.1 Overview (4)1.2 Features (4)1.2.1 Display interface (4)1.2.2 HDMI (4)1.2.3 LVDS (4)1.2.4 TV-ENCODER (4)1.2.5 TV-ENCODER (5)1.2.6 Audio CODEC (5)1.2.7 I2C register controller (5)1.2.8 temperature,voltage,package (5)1.3 Block Diagram (6)Chapter 2 Package Description (7)2.1 PIN Placement (7)2.2.1 BGA 144 Ball Map (7)2.2.2 LQFP Ball Map (7)2.2 PIN Description (9)2.3 Package Information (13)2.3.1 LQFP 128 (13)Chapter 1Introduction1.1 OverviewJetta is a partner chip for Rockchip mobile application processor. It can minimize the external chipset in Rockchip’s Table and TV BOX solution; reduce the total cost and PCB size.Jetta include dual RGB display interface. With the internal MUX function, it can output 1080P HDMI signal or CVBS/YPbPr to TV and output RGB/LVDS signal to TFT panel. In this case, Jetta can support dual panel (TV and TFT)display.Jetta also include a audio codec.1.2 Features1.2.1 Display interface●Dual 24bit RGB display interface for LVDS and HDMI●With internal MUX function, LVDS and HDMI/CVBS have independent displayinterface or share one interface.●LCDC1 interface support RGB panel output from scaler, this function can supportdual panel display in HDMI and RGB interface panel1.2.2 HDMI●Very low power operation, less than 60mW during 1080P HD display●HDMI 1.4/1.3/1.2/1.1, HDCP 1.2 and DVI 1.0 standard compliant transmitter●Supports data rate from 25MHz, 1.65bps up to 3.4Gbps over a Single channelHDMI Support 3D function defined in HDMI 1.4 spec●TMDS Tx Drivers with programmable output swing, resister values andpre-emphasis Supports all DTV resolutions including 480i/576i/480p/576p/720p/1080i/1080p/4Kx2K●Digital video interface supports a pixel size of 24 bits color depth in RGB, YCbCr4:4:4 or YCbCr 4:2:2 (ITU.656)●S/PDIF output supports PCM, Dolby Digital, DTS digital audio transmission(32-192kHz Fs) using IEC60958 and IEC 61937●Multiphase 4MHz fixed bandwidth PLL with low jitter●DDC Bus I2C master interface at 3.3V●HDCP encryption and decryption engine contains all the necessary logic to encryptthe incoming audio and video data●Support HDMI LipSync●Lower power operation with optimal power management feature1.2.3 LVDS●85MHz clock support●28:4 data channel compression at data rates up to 595 Mbps per channel●Support VGA,SVGA,XGA and single pixel SXGA●Comply with the Standard TIA/EIA-644-A LVDS stand●Scaler function for 1080P/720P video input to TFT display, (For RK29 Tablet TFTand HDMI dual panel display )●Support 8bit format-1, format-2, format-3 display mode, Support 6bit displaymode.●Display mode can be select by input MUX●Low power mode1.2.4 TV-ENCODER●PAL/NTSC-CVBS/YPbPr traditional TV encoder◆Support ITU-BT656/ ITU-BT601 standard◆Support progressive RGB interface●576p/480p-YPbPr SDTV encoder●720P/1080i/1080P-YPbPr HDTV encoder●3channel 10bit Video-DACs●Support CVBS and YPbPr TV output.1.2.5 TV-ENCODER●Display interface◆Parallel RGB LCD Interface: 24-bit(RGB888), 18-bit(RGB666),15-bit(RGB565)◆Asynchronous output pixel clock (PLL required)◆Flexible display timing setting◆Configurable border black area●Image scaler◆Scaling down- Max input resolution: 1920x1080- Arbitrary non-integer scaling ratio- Max 1/4 scaling ratio◆Scaling up- Max output resolution: 2048x2048- Arbitrary non-integer scaling ratio- Max 4 scaling ratio1.2.6 Audio CODEC●Complete Stero/Mon Microphone interface●ADC SNR 95dB(‘A’ Weighted), THD -85dB at 48kHz, 3.3V●DAC and On-chip Headphone Driver◆>20mW output power on 32Ω/3.3v◆THD+N at 20mW, SNR>95dB with 32Ω load●Seperately mixed mono output●256 x Fs/384 x Fs Master clock rates, up to 24MHz●Audio sample rates: 8 to 96kS/s●Less than -80dBc out-of-band Noise1.2.7 I2C register controller●One I2C slave interface, cotroll four modules: regitercontroller/TV-encoder/HDMI/audio-CODEC.I2C module addressregister controller 7'h40Tvencoder 7'h42HDMI 7'h46Audio-CODEC 7'h60●External clock input for Chip working, this clock can share with MCLK (12M)●Interrupt output for HDMI in and other function1.2.8 temperature,voltage,package●Operation Temperature Range-40~125°C●Operation Voltage RangeCore : 1.2VI/O : 3.3V●Package TypeLQFP128/BGA1441.3 Block DiagramFig 1 Jetta DiagramLCD0 interfaceV-DACHDMI rgb2ccir601TVELVDSLCD1 interfaceSCALERAudio_CODEC PLL0 I2SI2S/SPDIFCODECPLL1SCALERI2C Controlregister JettaChapter 2 Package Description2.1 PIN Placement2.2.1 BGA 144 Ball Map2.2.2 LQFP Ball Map128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112I O _H D M I _E X T RI O _H D M I _V S S A B GI O _H D M I _V C C A B GI O _H D M I _T X 2PI O _H D M I _T X 2NI O _H D M I _V S SI O _H D M I _T X 1PI O _H D M I _T X 1NI O _H D M I _V S S AI O _H D M I _T X 0PI O _H D M I _T X 0NI O _H D M I _V S S A 1I O _H D M I _T X 3PI O _H D M I _T X 3NI O _H D M I _V C C D 1P 2I O _H D M I _V C C A P L L 3P 3I O _H D M I _V S S P L L1 IO_HDMI_CEC LQFP1282 IO_HDMI_HPD3 IO_HDMI_SDA4 IO_HDMI_SCL5 IO_I2SSDO6 IO_I2SBSCLK7 IO_DACFRM8 IO_ADCFRM9 IO_I2SSDI[0] 10 IO_I2SSDI[1] 11 IO_I2SSDI[2] 12 IO_I2SSDI[3] 13 IO_CLKIN 14 IO_SPDIF 15 IO_I2C_SCL 16 IO_I2C_SDA 17IO_INTERUPT18 IO_NPOR 19 IO_LCDC0_DATA[23] 20 IO_LCDC0_DATA[22]21 IO_VDD1 22 IO_VSS1 23 IO_VCC1 24 IO_LCDC0_DATA[21] 25 IO_LCDC0_DATA[20] 26 IO_LCDC0_DATA[19] 27 IO_LCDC0_DATA[18] 28 IO_LCDC0_DATA[17] 29 IO_LCDC0_DATA[16] 30 IO_LCDC0_DATA[15] 31 IO_LCDC0_DATA[14]32IO_LCDC0_DATA[13]I O _L C D C 0_D A T A [12]I O _L C D C 0_D A T A [11]I O _L C D C 0_D A T A [10]I O _L C D C 0_D A T A [9]I O _L C D C 0_D A T A [8]I O _L C D C 0_D A T A [7]I O _L C D C 0_D A T A [6]I O _L C D C 0_D A T A [5]I O _L C D C 0_D A T A [4]I O _L C D C 0_D A T A [3]I O _L C D C 0_D A T A [2]I O _L C D C 0_D A T A [1]I O _L C D C 0_D A T A [0]I O _L C D C 0_D E NI O _L C D C 0_D C L KI O _L C D C 0_H S Y N CI O _L C D C 0_V S Y N C33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49111 110 109 108 107 106 105 104 103 102101 100 99 98 97I O _C O D E C _A O LI O _C O D E C _V D D A OI O _C O D E C _V S S A OI O _C O D E C _A O RI O _C O D E C _V D D AI O _C O D E C _V S S AI O _C O D E C _V M I DI O _C O D E C __R E FI O _C O D E C _T P _M I C B I A SI O _C O D E C _M I C _I NI O _C O D E C _A I RI O _C O D E C _A I LI O _L V D S _P V D D P L V D 1I O _L V D S _P V S S D L V D 1I O _L V D S _V D D P L L 0/1IO_LVDS_PVDDD1 96 IO_LVDS_VSS 95 IO_LVDS_VDD 94 IO_LVDS_PADN4 93 IO_LVDS_PADP4 92 IO_LVDS_PADN391 IO_LVDS_PADP3 90 IO_LVDS_CLKN 89 IO_LVDS_CLK 88 IO_LVDS_PADN2 87 IO_LVDS_PADP2 86 IO_LVDS_PADN1 85 IO_LVDS_PADP1 84 IO_LVDS_XRES 83 IO_LVDS_PVDDPLVD 82 IO_LVDS_PVSSDLVD 81 IO_LVDS_VSSPLL180IO_LVDS_VSSPLL0 79 IO_LVDS_PVDDD78 IO_VSS3 77 NC 76 IO_VDD3 75 NC74 IO_VDAC_REXT 73 IO_VDAC_COMP 72 IO_VDAC_DACR0 71 IO_VDAC_AVDD0 70 IO_VDAC_AVDD1 69 IO_VDAC_DACG0 68 IO_VDAC_AVSS0 67 IO_VDAC_AVSS166 IO_VDAC_DACB065I O _V C C 2I O _V C C 2_DI O _V S S 2I O _V S S 2_DI O _V D D 2I O _V D D 2_DI O _P L L 1_V D D 12I O _P L L 1_V S S 12I O _P L L 0_V D D 12I O _P L L 0_V S S 12S u b s t r a t eS u b s t r a t eS u b s t r a t eS u b s t r a t eS u b s t r a t e50 51 52 53 54 55 56 57 58 59 60 61 62 63 642.2 PIN DescriptionNotes I --- input pinsO --- output pinsB --- bidirectional pinsP --- power supply pins (digital and analog)G --- ground supply pins (digital and analog)A --- Analog IO pinsOSC --- oscillator IO pinsTable 1 Jetta Pin DescriptionPIN#BGA144 PIN#LQFP128 PIN namePIN typePin DescriptionE7 1 IO_HDMI_CECB HDMI CEC control line. E62IO_HDMI_HPDB HDMI HPDHot plug detect D43IO_HDMI_SDAB DDC channel SDA in.For tri‐state gate use E5 4IO_HDMI_SCLB DDC channel SCL in. For tri‐state gate use B2 5 IO_I2SSDO O i2s sdo A1 6 IO_I2SBSCLK B I2S SCLKB1 7 IO_DACFRM B I2S LRCK for DAC C28IO_ADCFRMB I2S LRCK for ADCC1 9 IO_I2SSDI[0] I I2S sdi[0]D3 10 IO_I2SSDI[1] I I2S sdi[1]E4 11 IO_I2SSDI[2] I I2S sdi[2]E3 12 IO_I2SSDI[3] I I2S sdi[3]D2 13 IO_CLKIN I jetta clock inputF4 14 IO_SPDIF I SPDIF inputD1 15 IO_I2C_SCL I I2C SCLE2 16 IO_I2C_SDA B I2C SDAE1 17 IO_INTERUPT O HDMI interrupt outputF2 18 IO_NPOR I power on resetF3 IO_TEST I test inputF1 19 IO_LCDC0_DATA[23] I LCD interface 0 data 23G1 20 IO_LCDC0_DATA[22] I LCD interface 0 data 22F5 21 IO_VDD1P 1.2V core powerF5 21 IO_VDD1_DF6 22 IO_VSS1G groundF6 22 IO_VSS1_DG5 23 IO_VCC1P 3.3V IO powerG5 23 IO_VCC1_DG2 24 IO_LCDC0_DATA[21] I LCD interface 0 data 21G3 25 IO_LCDC0_DATA[20] I LCD interface 0 data 20G4 26 IO_LCDC0_DATA[19] I LCD interface 0 data 19H1 27 IO_LCDC0_DATA[18] I LCD interface 0 data 18H2 28 IO_LCDC0_DATA[17] I LCD interface 0 data 17H3 29 IO_LCDC0_DATA[16] I LCD interface 0 data 16H4 30 IO_LCDC0_DATA[15] I LCD interface 0 data 15J1 31 IO_LCDC0_DATA[14] I LCD interface 0 data 14J2 32 IO_LCDC0_DATA[13] I LCD interface 0 data 13J3 33 IO_LCDC0_DATA[12] I LCD interface 0 data 12J4 34 IO_LCDC0_DATA[11] I LCD interface 0 data 11K1 35 IO_LCDC0_DATA[10] I LCD interface 0 data 10K2 36 IO_LCDC0_DATA[9] I LCD interface 0 data 9K3 37 IO_LCDC0_DATA[8] I LCD interface 0 data 8K4 38 IO_LCDC0_DATA[7] I LCD interface 0 data 7L1 39 IO_LCDC0_DATA[6] I LCD interface 0 data 6L2 40 IO_LCDC0_DATA[5] I LCD interface 0 data 5M1 41 IO_LCDC0_DATA[4] I LCD interface 0 data 4M2 42 IO_LCDC0_DATA[3] I LCD interface 0 data 3L3 43 IO_LCDC0_DATA[2] I LCD interface 0 data 2M3 44 IO_LCDC0_DATA[1] I LCD interface 0 data 1M4 45 IO_LCDC0_DATA[0] I LCD interface 0 data 0L4 46 IO_LCDC0_DEN I lcdc0 data enable signalM5 47 IO_LCDC0_DCLK I lcdc0 clock outL5 48 IO_LCDC0_HSYNC I lcdc0 horizontal sync signal K5 49 IO_LCDC0_VSYNC I lcdc0 vertical sync signalJ5 IO_LCDC1_DATA[23] B LCD interface 1 data 23H5 IO_LCDC1_DATA[22] B LCD interface 1 data 22M6 IO_LCDC1_DATA[21] B LCD interface 1 data 21L6 IO_LCDC1_DATA[20] B LCD interface 1 data 20K6 IO_LCDC1_DATA[19] B LCD interface 1 data 19H6 IO_LCDC1_DATA[18] B LCD interface 1 data 18G6 IO_LCDC1_DATA[17] B LCD interface 1 data 17M7 IO_LCDC1_DATA[16] B LCD interface 1 data 16L7 IO_LCDC1_DATA[15] B LCD interface 1 data 15K7 IO_LCDC1_DATA[14] B LCD interface 1 data 14J7 IO_LCDC1_DATA[13] B LCD interface 1 data 13M8 IO_LCDC1_DATA[12] B LCD interface 1 data 12L8 IO_LCDC1_DATA[11] B LCD interface 1 data 11K8 IO_LCDC1_DATA[10] B LCD interface 1 data 10J6 50 IO_VCC2P 3.3V IO powerJ6 51 IO_VCC2_DG7 52 IO_VSS2G groundG7 53 IO_VSS2_DH7 54 IO_VDD2P 1.2V core powerH7 55 IO_VDD2_DJ8 IO_LCDC1_DATA[9] B LCD interface 1 data 9H8 IO_LCDC1_DATA[8] B LCD interface 1 data 8G8 IO_LCDC1_DATA[7] B LCD interface 1 data 7M9 IO_LCDC1_DATA[6] B LCD interface 1 data 6L9 IO_LCDC1_DATA[5] B LCD interface 1 data 5K9 IO_LCDC1_DATA[4] B LCD interface 1 data 4J9 IO_LCDC1_DATA[3] B LCD interface 1 data 3H9 IO_LCDC1_DATA[2] B LCD interface 1 data 2G9 IO_LCDC1_DATA[1] B LCD interface 1 data 1M10 IO_LCDC1_DATA[0] B LCD interface 1 data 0M11 IO_LCDC1_DEN B lcdc1 data enable signalL11 IO_LCDC1_DCLK B lcdc1 clock outM12 IO_LCDC1_HSYNC B lcdc1 horizontal sync signalL12 IO_LCDC1_VSYNC B lcdc1 vertical sync signalK10 56 IO_PLL1_VDD12 P 1.2V PLL powerL10 57 IO_PLL1_VSS12 G PLL groundJ10 58 IO_PLL0_VDD12 P 1.2V PLL powerK11 59 IO_PLL0_VSS12 G PLL groundK12 65 IO_VDAC_DACB1A Vedio DACB channel outputK12 65 IO_VDAC_DACB0J11 66 IO_VDAC_AVSS1G Analog groundJ11 67 IO_VDAC_AVSS0J12 68 IO_VDAC_DACG1A Vedio DAC G channel outputJ12 68 IO_VDAC_DACG0H10 69 IO_VDAC_AVDD1P Analog power supply (+3.3)H10 70 IO_VDAC_AVDD0H12 71 IO_VDAC_DACR1A Vedio DAC G channel outputH12 71 IO_VDAC_DACR0G10 72 IO_VDAC_COMP A Vedio DAC Compensation pin.H11 73 IO_VDAC_REXT A DAC external resistor pin.F8 75 IO_VDD3 P 3.3 IO POWERF7 77 IO_VSS3 G groundF10 78 IO_LVDS_PVDDD P LVDS analog power pad (3.3V) F9 79 IO_LVDS_VSSPLL0G PLL ground padF9 80 IO_LVDS_VSSPLL1E8 81 IO_LVDS_PVSSDLVD G LVDS analog ground pad for VSSDLVDE10 82 IO_LVDS_PVDDPLVD P LVDS analog power pad (3.3V) for VDDDLVD E9 83 IO_LVDS_XRES A LVDS current biasing generationG12 84 IO_LVDS_PADP1 A Transmit serial data out, n=1~4G11 85 IO_LVDS_PADN1 A Transmit serial data out (Negative), n=1~4F12 86 IO_LVDS_PADP2 A Transmit serial data out, n=1~4F11 87 IO_LVDS_PADN2 A Transmit serial data out (Negative), n=1~4E12 88 IO_LVDS_CLK A Output clockE11 89 IO_LVDS_CLKN A Output clock (Negative)D12 90 IO_LVDS_PADP3 A Transmit serial data out, n=1~4D11 91 IO_LVDS_PADN3 A Transmit serial data out (Negative), n=1~4C12 92 IO_LVDS_PADP4 A Transmit serial data out, n=1~4C11 93 IO_LVDS_PADN4 A Transmit serial data out (Negative), n=1~4D10 94 IO_LVDS_VDD P LVDS digital power 1.2VB12 95 IO_LVDS_VSS G LVDS digital groundA12 96 IO_LVDS_PVDDD1 P LVDS analog power (3.3V)B11 97 IO_LVDS_VDDPLL0P PLL power pad (3.3V)B11 97 IO_LVDS_VDDPLL1C10 98 IO_LVDS_PVSSDLVD1 G LVDS analog groundA11 99 IO_LVDS_PVDDPLVD1 P LVDS digital power (3.3V)B10 100 IO_CODEC_AIL A Left line input.A10 101 IO_CODEC_AIR A Right line input.C9 102 IO_CODEC_MIC_IN A Micphone input.D9 103 IO_CODEC_TP_MICBIAS A Micphone BIASB9 104IO_CODEC__REF A DAC reference decoupling node(value=vdd)D8 105IO_CODEC_VMID A VMID reference decoupling node (value=vdd/2)C8 106IO_CODEC_VSSA G The power ground for the CODEC analog part. B8 107IO_CODEC_VDDA P The power for the CODEC analog part.A9 108 IO_CODEC_AOR A Right Earphone amplifier outputD7 109IO_CODEC_VSSAO G The power ground for Earphone amplifierIO_CODEC_AOM A MONO Earphone amplifier outputA7 110IO_CODEC_VDDAO P The power for Earphone amplifierA8 111 IO_CODEC_AO L A Left Earphone amplifier outputB7 112 IO_HDMI_VSSPLL G Ground of PLL.C7 113 IO_HDMI_VCCAPLL3P3 P 3.3V supply of PLL.D6 114 IO_HDMI_VCCD1P2 P 1.2V supply.A6 115 IO_HDMI_TX3N A TMDS negative clock line.B6 116 IO_HDMI_TX3P A TMDS positive clock line.C6 117 IO_HDMI_VSSA1 G Ground of TMDS driver.A5 118 IO_HDMI_TX0N A TMDS channel 0 negative data line.B5 119 IO_HDMI_TX0P A TMDS channel 0 positive data line.D5 120 IO_HDMI_VSSA G Ground of TMDS driver.A4 121 IO_HDMI_TX1N A TMDS channel 1 negative data line.B4 122 IO_HDMI_TX1P A TMDS channel 1 positive data line. C5 123 IO_HDMI_VSS G Ground.A3 124 IO_HDMI_TX2N A TMDS channel 2 negative data line. B3 125 IO_HDMI_TX2P A TMDS channel 2 positive data line. C4 126 IO_HDMI_VCCABG P 3.3V supply of bandgap.C3 127 IO_HDMI_VSSABG G Ground of bandgap.A2 128IO_HDMI_EXTR A Connect 1.9Kohm resistor to ground to generate reference current.2.3 Package Information 2.3.1 LQFP 1282.3.1 BGA144。

福州瑞芯微电子股份有限公司密级状态：绝密()秘密()内部()公开(√)Rockchip DRM Panel Porting Guide（第二系统产品部）文件状态：[√]正在修改[]正式发布当前版本：V1.0作者：闭伟勇完成日期：2017-4-15审核：完成日期：福州瑞芯微电子股份有限公司Fuzhou Rockchips Semiconductor Co.,Ltd(版本所有,翻版必究)版本历史版本号作者修改日期修改说明备注V1.0闭伟勇2017-4-15初始版本V1.1黄家钗2017-4-17加入LVDS屏配置说明目录1基本结构 (1)1.1文件清单 (1)1.1.1Kernel (1)1.1.2U-boot (2)1.2整体流程 (4)1.2.1Kernel (4)2MIPI (5)2.1Kernel (5)2.1.1MIPI Host (5)2.1.2MIPI PHY (5)2.1.3LOGO (5)2.1.4Panel (6)2.1.5Command (8)2.1.6常见问题 (13)3eDP (14)3.1配置方式1 (14)3.1.1Kernel (14)3.2配置方式2 (16)3.2.1Kernel (16)3.2.2U-boot (19)3.3配置方式3 (19)3.3.1Kernel (20)4LVDS (21)4.1LVDS节点配置 (21)4.2属性说明 (22)4.3Data mapping (23)1基本结构本文档基于以下平台进行说明，不同平台相关驱动以及DTS配置方式可能存在细微差异。

Platform：RK3368HBoard：rk3368-sheep1.1文件清单1.1.1Kernel驱动路径：drivers/gpu/drm/rockchip/drivers/gpu/drm/bridge/drivers/gpu/drm/panel/drivers/phy/文档路径：Documentation/devicetree/bindings/display/rockchip/Documentation/devicetree/bindings/display/bridge/Documentation/devicetree/bindings/display/panel/Documentation/devicetree/bindings/phy/下表只列出具体文件：Driver File DocCore rockchip_drm_drv.c rockchip-drm.txt Framebuffer rockchip_drm_fb.cGEM rockchip_drm_gem.crockchip-vop.txtVOP rockchip_drm_vop.crockchip_vop_reg.cLVDS rockchip_lvds.c rockchip-lvds.txtRGA rockchip_drm_rga.c rockchip-rga.txtMIPI dw-mipi-dsi.cphy-rockchip-inno-mipi-dphy.c dw_mipi_dsi_rockchip.txt phy-rockchip-inno-mipi-dphy.tx tHDMI dw_hdmi-rockchip.cdw-hdmi.c dw_hdmi-rockchip.txt dw_hdmi.txtINNO HDMI inno_hdmi.c inno_hdmi-rockchip.txteDP analogix_dp-rockchip.canalogix_dp_core.canalogix_dp_reg.cphy-rockchip-dp.c analogix_dp-rockchip.txt analogix_dp.txt rockchip-dp-phy.txtDP cdn-dp-core.ccdn-dp-reg.ccdn-dp-rockchip.txt Panel panel-simple.c simple-panel.txt 1.1.2U-boot驱动路径：drivers/video/下表只列出具体文件：Driver FileCore rockchip_display.crockchip_crtc.crockchip_connector.crockchip_phy.crockchip_panel.cVOP rockchip_vop.crockchip_vop_reg.ceDP rockchip_analogix_dp.crockchip_analogix_dp_reg.cMIPI rockchip_mipi_dsi.crockchip-dw-mipi-dsi.crockchip-inno-mipi-dphy.c Panel panel_simple.crockchip_dsi_panel.c LVDS rockchip_lvds.c1.2整体流程1.2.1Kernel2MIPIPlatform：RK33668HBoard：SheepPanel：KingDisplay KD080D24-40NI-B62.1Kernel2.1.1MIPI Host$vim arch/arm64/boot/dts/rockchip/rk3368-sheep.dts2.1.2MIPI PHY$vim arch/arm64/boot/dts/rockchip/rk3368-sheep.dts①属性说明Property Value Commentrockchip,dsi-panel&dsi_panel PHY驱动通过该phandle，可以获取屏相关参数，根据屏的timing计算出所需bit-rate，同时对PHY进行正确配置，并将该参数传递给HOST，使HOST能正确初始化。

密级状态：绝密()秘密()内部()公开(√)CIF_ISP10_Driver_User_Manual（技术部，图形显示中心）文件状态：[√]正在修改[]正式发布当前版本：V1.0作者：邓达龙完成日期：2017-11-23审核：完成日期：2017-11-24福州瑞芯微电子股份有限公司Fuzhou Rockchips Electronics Co.,Ltd(版本所有,翻版必究)版本历史版本号作者修改日期修改说明审核备注V1.0邓达龙2017-11-23发布初版目录1.文档适用平台 (1)2.CAMERA文件目录说明 (1)3.CAMERA设备注册(DTS) (1)3.1MIPI S ENSOR注册 (1)3.2DVP S ENSOR注册 (4)4.CAMERA设备驱动 (5)4.1数据类型简要说明 (6)STRUCT I2C_DRIVER (6)struct v4l2_subdev_core_ops (7)struct v4l2_subdev_video_ops (9)struct v4l2_subdev_pad_ops (10)struct ov_camera_module_custom_config (11)struct ov_camera_module_config (14)PLTFRM_CAM_ITF_MIPI_CFG (16)PLTFRM_CAM_ITF_DVP_CFG (17)4.2API简要说明 (18)sensorxxx_g_VTS (18)sensorxxx_auto_adjust_fps (18)sensorxxx_write_aec (19)sensorxxx_filltimings (19)sensorxxx_g_timings (20)sensorxxx_set_flip (21)sensorxxx_start_streaming (21)sensorxxx_stop_streaming (22)sensorxxx_check_camera_id (22)5.驱动移植简单步骤说明 (23)1.文档适用平台芯片平台软件系统支持情况RK3399Linux(Kernel-4.4)YRK3288Linux(Kernel-4.4)Y此类平台的isp driver按照isp硬件版本来区分，具体命名如下：RK3288/RK3399平台ISP Driver名称：cif_isp102.Camera文件目录说明RK3288/RK3399Linux kernel：||arch/arm/boot/dts DTS配置文件|drivers/media||platform/rk-isp10ISP Host驱动|i2c/soc_camera/rockchip/Camera Sensor驱动3.Camera设备注册(DTS)3.1MIPI Sensor注册camera0:camera-module@36{status="okay";//是否加载模块，默认开启compatible="omnivision,ov2710-v4l2-i2c-subdev";//omnivision sensor类型//ov2710-v4l2-i2c-subdev中ov2710为sensor型号//需要与驱动名字一致reg=<0x36>;//Sensor I2C设备地址device_type="v4l2-i2c-subdev";//设备类型clocks=<&clk_cif_out>;//sensor clickin配置clock-names="clk_cif_out";pinctrl-names="rockchip,camera_default","rockchip,camera_sleep";pinctrl-0=<&cif_dvp_clk_out>;pinctrl-1=<&cif_dvp_clk_out_sleep>;rockchip,pd-gpio=<&gpio3GPIO_B0GPIO_ACTIVE_HIGH>;//powerdown管脚分配及有效电平rockchip,pwr-gpio=<&gpio3GPIO_B5GPIO_ACTIVE_HIGH>;//power管脚分配及有效电平rockchip,rst-gpio=<&gpio3GPIO_D1GPIO_ACTIVE_LOW>;//reset管脚分配及有效电平rockchip,camera-module-mclk-name="clk_cif_out";//mclk时钟源配置rockchip,camera-module-facing="back";//前后置配置rockchip,camera-module-name="LA6110PA";//Camera模组名称rockchip,camera-module-len-name="YM6011P";//Camera模组镜头rockchip,camera-module-fov-h="128";//模组水平可视角度配置rockchip,camera-module-fov-v="55.7";//模组垂直可视角度配置rockchip,camera-module-orientation=<0>;//模组角度设置rockchip,camera-module-flip=<0>;rockchip,camera-module-mirror=<0>;//以上2个属性控制摄像头驱动中的镜像配置，如果图像旋转180度，可以将这2个属性修改成相反的值即可旋转180；/*resolution.w,resolution.h,defrect.left,defrect.top,defrect.w,defrect.h*/ rockchip,camera-module-defrect0=<192010800019201080>;//resolution.w:sensor输出列数,//resolution.h:sensor输出行数,//defrect.left:输出偏移列数,//defrect.top:输出偏移行数,//defrect.w:输出列数,defrect.left+defrect.w<=resolution.w,//defrect.h:输出行数,defrect.h+defrect.top<=resolution.h,//具体如下图所示：resolution.wdefrect.topdefrect.w resolution.h defrect.h defrect.leftrockchip,camera-module-flash-support=<0>;//flash控制开关rockchip,camera-module-mipi-dphy-index=<0>;//sensor实际使用的phy,要与硬件实际连接对应};&i2c1{//配置Camera设备连接到哪个I2C模块上，一般为I2C1status="okay";//是否加载i2c模块，默认开启#include"rv1108-camb-xx.dtsi"};&cif_isp0{rockchip,camera-modules-attached=<&camera0&camera1&camera2>;//配置需要使用的camera列表,连接到ISP设备节点status="okay";};3.2DVP Sensor注册camera2:camera-module@1a{status="okay";compatible="sony,imx323-v4l2-i2c-subdev";reg=<0x1a>;device_type="v4l2-i2c-subdev";clocks=<&clk_cif_out>;clock-names="clk_cif_out";pinctrl-names="rockchip,camera_default","rockchip,camera_sleep";pinctrl-0=<&cif_dvp_d0d1&cif_dvp_d2d9&cif_dvp_d10d11&cif_dvp_clk_in&cif_dvp_clk_out&cif_dvp_sync>;pinctrl-1=<&cif_dvp_d0d1_sleep&cif_dvp_d2d9_sleep&cif_dvp_d10d11_sleep&cif_dvp_clk_in_sleep&cif_dvp_clk_out_sleep&cif_dvp_sync_sleep>;//DVP pin引脚配置，具体定义在文件rv1108.dtsi中其它配置和MIPI Sensor相同rockchip,pd-gpio=<&gpio3GPIO_D1GPIO_ACTIVE_LOW>;rockchip,pwr-gpio=<&gpio3GPIO_B5GPIO_ACTIVE_HIGH>;rockchip,rst-gpio=<&gpio3GPIO_B0GPIO_ACTIVE_LOW>;rockchip,camera-module-mclk-name="clk_cif_out";rockchip,camera-module-facing="back";rockchip,camera-module-name="LA6114PA";rockchip,camera-module-len-name="YM6011P";rockchip,camera-module-fov-h="122";rockchip,camera-module-fov-v="63";rockchip,camera-module-orientation=<0>;rockchip,camera-module-iq-flip=<0>;rockchip,camera-module-iq-mirror=<0>;rockchip,camera-module-flip=<0>;rockchip,camera-module-mirror=<0>;/*resolution.w,resolution.h,defrect.left,defrect.top,defrect.w,defrect.h*/ rockchip,camera-module-defrect0=<22001125481319201080>;rockchip,camera-module-flash-support=<0>;};4.Camera设备驱动Camera Sensor采用I2C与主控进行交互，目前Sensor driver按照I2C设备驱动方式实现，sensor driver同时采用v4l2subdev的方式实现与host driver之间的交互。