Chapter4--Buses and timing in PC
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This information must be latched, then pins AD0–AD7 are used to carry data.
– When data is to be sent out or in, ALE is low, which indicates that AD0–AD7 will be used as data buses (D0–D7). – The process of separating address and data from pins AD0–AD7 is called demultiplexing.
In read timing, ALE latches the address in the first clock cycle. In the second and third cycles, the control signals are provided. In the third cycles, the data is validated on data bus. By the end of the fourth, data must be at the CPU pins.
4.2.2 address bus in 8088
In any system, all addresses must be latched to provide a stable, high-drivecapability address bus.
Fig. 9-5 Address,Data,and Control Buses in 8088-based System
Microcomputer Principle and Application
School of Mechanical Engineering Nanjing University of Science & Technology
Chapter 4 Buses and timing in PC
4.1 4.2 4.3 4.4 4.5 4.6 Basic concepts of timing 8088/8086 microprocessor Two modes of 8088 microprocessor 8284/8288 supporting chips 8-bit section of ISA bus 16-bit ISA bus
RD, WR, and IO/M.
RD & WR pins are both active-low. IO/M is low for memory, high for I/O devices.
Fig. 9-4 Control signal generation
4.2 8088/8086 microprocessor
– Pins 9-16 (AD0–AD7) are used for both data and addresses in 8088.
• AD stands for "address/data.‖
– The ALE (address latch enable) pin signals whether the information on pins AD0–AD7 is address or data.
Chapter 4 8088/8086 MICROPROCESSORS AND ISA BUS
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4.2.1 data bus in 8088
Due to chip packaging limitations in the 1970s, there was great effort to use the minimum number of pins for external connections. Intel multiplexed address & data buses, using the same pins to carry two sets of information: address & data.
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4.2.3 control bus in 8088
Use of simple logic gates (inverters and ORs) to generate control signals. CPLD (complex programmable logic devices) are used in today’s PC chipsets.
Clock Cycle
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Bus Cycle
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Instruction Cycle
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Chapter 4 8088/8086 MICROPROCESSORS AND ISA BUS
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4.2
8088/8086 microprocessor
8088 is a 40-pin microprocessor chip that can work in two modes: minimum mode and maximum mode.
Maximum mode is used to connect to 8087 coprocessor and/or 8089.
If a coprocessor is not needed, 8088 is used usually in minimum mode.
Every microprocessor-based system have three sets of separate buses: the address bus, the data bus, and the control bus.
OBJECTIVES
Introduce the basic concepts of timing State the function of the pins of the 8088. List the functions of the 8088 data, address, and control buses. State the differences in the 8088 microprocessor in maximum mode versus minimum mode. Describe the function of the pins of the 8284 clock generator chip. Describe the function of the pins of the 8288 bus controller chip. Explain the role of the 8088, 8284A, and 8288.
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4.2.3 control bus in 8088
Four control signals are generated: IOR; IOW; MEMR; MEMW. All of these signals must be active-low.
4.2 8088/8086 microprocessor
4.2 8088/8086 microprocessor
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4.2.3 control bus in 8088
8088 can access both memory and I/O devices for read and write operations, four operations, which need four control signals:
– The last 4 bits of the address come from A16–A19, pin numbers 35–38.
4.2 8088/8086 microprocessor
Fig. 9-1a 8088 in minimum mode
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4.2.2 address bus in 8088
Fig. 9-5 Address,Data,and Control Buses in 8088-based System
4.2 8088/8086 microprocessor
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4.2.4 bus timing of the 8088
8088 uses 4 clocks for memory & I/O bus activities.
Chapter 4 8088/8086 MICROPROCESSORS AND ISA asic concepts of timing
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Timing
There is a need of clock that used to synchronize activities of all peripheral chips in microcomputer.
The entire read or write cycle time is only 4 clock cycles.
To demultiplex address signals, a latch must be used to grab the addresses.
– Widely used is the 74LS373 IC, also 74LS573, a 74LS373 variation.
• AD0 to AD7 go to the 74LS373 latch, providing the 8-bit address A0–A7. • A8–A15 come directly from the microprocessor (pins 2–8 & pin 39).
The most widely used latch is the 74LS373 IC.
