Wafer-Cell-Panel Introduction(Rev[1]

Table of ContentsINFORMATION (1)1 CONTACT2 INTRODUCTION (3)2.1Overview (3)2.2History (3)3 CHOOSING A BUMPING PROCESS (5)3.1Standard Flip Chip – Bump on I/O (5)3.1.1Standard Flip Chip-Bump on I/O Process Summary (6)3.1.2I/O requirements for the SFC-Bump on I/O process (7)3.2Standard Flip Chip--Repassivation (8)3.2.1SFC-Repassivation Process Summary (9)3.3Standard Flip Chip--Redistribution (10)3.3.1SFC-Redistribution Process Summary (10)3.4Spheron TM WLCSP (12)3.4.1Spheron WLP™ Redistribution Process Flow (12)3.5Ultra CSP® (14)3.5.1Ultra CSP Process Summary (14)3.6Elite UBM™, Elite FC™, and Elite CSP™ – Electroless Ni/Au (17)3.6.1Elite UBM™ – Process Flow (17)3.6.2Elite FC™ – Process Flow (18)3.6.3Elite CSP™ – Process Flow (19)3.7Available Solder Alloys (21)3.7.1Basic Physical Properties of Solder Paste Alloys (21)3.7.2Basic Physical Properties of Pre-Formed Solder Ball Alloys (21)3.8Other Services (22)3.8.1Laser Mark (22)3.8.2“In Process” Backgrind (22)3.8.3“Post Process” Backgrind (22)3.8.4Electronic Wafer Yield Maps (23)3.8.5Post Bump Electrical Testing (23)3.8.6Dicing and Packaging (23)4 DESIGN RULES AND GUIDELINES (24)4.1Overview (24)4.2Incoming Wafer Requirements (24)4.2.1Types of Wafers (24)4.2.2SEMI Material Requirements (24)4.2.3Wafer Scribe Requirements (24)4.2.4Wafer Backside Requirements (24)4.2.5Acceptable Wafer Size (24)4.2.6Wafer Edge Exclusion Requirements (25)4.2.7Incoming Wafer Thickness (25)4.3Device Requirements (25)4.3.1Die Size (25)4.3.2Number of Sites Bumped Per Die (25)4.3.3Die Layout (25)4.3.4Unique Die on Wafer (25)4.3.5Types of Passivation (26)4.3.6Types of Final Metal (26)4.3.7Probing (26)4.3.8Ink Dots (26)4.3.9Fuse Links (27)4.3.10Nitride Passivation Openings Not Bumped (27)4.3.11Street Width (27)4.3.12Special Elite UBM, Elite FC, and Elite CSP Device Requirements (27)4.3.13Passivation Opening Sidewalls (28)4.4Alignment Feature Requirements (28)4.5What Information Does FlipChip Need For New Mask Designs? (29)CONSIDERATIONS (30)5 DESIGN5.1Pitch, UBM Size, and Bump Height Relationships (30)5.2Packaging Relationships (31)5.2.1SFC, Repassivation, and Redistribution Package Stand-Off Height (31)5.2.2UltraCSP, Spheron WLP, and EliteCSP Package Dimensions (31)5.2.3WLP Package Stand-Off Heights (32)5.3Printed-Circuit Board Layout (33)5.3.1WL-CSP Stencil and Board Design Parameters (34)5.4Reliability Testing (34)PROPERTIES (35)6 MATERIAL6.1Benzocyclobutene (BCB) (35)6.2Spheron WLP Polymer (36)6.3Solder Alloy Material Properties (37)6.4UBM Metal Properties (37)6.5SFC-Redistribution Trace Electrical Properties (38)6.6Ultra CSP Redistribution Trace Electrical Properties (38)7 GLOSSARY (39)1Contact InformationTo start your relationship with FlipChip, contact the appropriate Sales Representative. Each is an expert at learning the particular needs of your device. In addition, your FlipChip Sales Representative can discuss all aspects of pricing, logistics, cycle time, and answer any other question you may have.Worldwide Sales RepresentativesFred Hickman IIIVice President -- Sales and MarketingFlipChip International, LLCPhoenix, AZ, USA 85034Phone: 602-431-4749E-mail: fred.hickman@AsiaJay HayesSr. Director of Strategic AccountsFlipChip International, LLCMonument, CO, USAPhone: 719-481-6444E-mail: jay.hayes@California and Northwest U.S.A.Jim GrahamRegional Account ManagerFlipChip International, LLCSanta Clara, CA, USAPhone: 408-395-4765Cell: 408-761-0808E-mail: jim.graham@Southwestern U.S.A., Eastern U.S.A., Canada andGeneral Technical InquiresBret TrimmerSr. Account ManagerFlipChip International, LLCPhoenix, AZ, USAPhone: 602-431-4760Cell: 480-643-9034E-mail: bret.trimmer@Central U.S.A.Bruce BowersVice President -- Business Development FlipChip International, LLCPhoenix, AZ, USAPhone: 602-431-6634E-mail: bruce.bowers@EuropeDave McCombDirector of European Business and Sales FlipChip International, LLCHawick, Scotland, UKPhone: +44 1450 373 919E-mail: david.mccomb@EuropeDavid ClarkEuropean Sales EngineerFlipChip International, LLCIpswich, Suffolk, UKPhone: +44 7875 307 633 E-mail: david.ckark@2 Introduction2.1 OverviewThank you for your interest in FlipChip International, LLC for your wafer bumping needs. This guide will take you through the process of deciding which bumping flow is right for you. In addition, the guide will give you the basics of each process flow, incoming wafer requirements, device requirements, material properties, and a glossary, so you may have a better understanding of the bumping process.2.2 HistoryFlipChip International, LLC started out in 1996 as Flip Chip Technologies (FCT), a joint venture between Delco Electronics Systems and Kulicke & Soffa Industries (K&S). Delco brought the patented Flex-On-Cap (or FoC) flip chip process and over 30 years of experience from the automotive industry. K&S added its knowledge and leadership position as the world's largest supplier of semiconductor assembly equipment. By any measure, the company was a huge success. The company’s Flex-on-Cap (FoC) standard flip chip bumping technology quickly became the industry standard for flip chip bumping.In 1998, FCT developed and patented the Ultra CSP® Wafer Level Chip Scale Package (WL-CSP), which quickly became the industry standard for WL-CSP. FlipChip began an aggressive licensing program to bring its unique bumping technology to a broader worldwide market. Today, the semiconductor industry’s packaging heavyweights, including Amkor Technology, Advanced Semiconductor Engineering (ASE), Siliconware (SPIL), and STATS ChipPAK license and use FlipChip’s bumping technology.In 2001, K&S acquired Delco’s remaininginterest in FCT and we became the Flip ChipDivision of Kulicke & Soffa. In 2004,RoseStreet Labs, LLC, a private research anddevelopment company based in Phoenix,completed the acquisition of the assets of theFlip Chip Division from Kulicke & Soffa, throughits newly formed subsidiary -- FlipChipInternational, LLC. In early 2005, FCI acquiredIC Services, which became the Die SalesDivision of FCI (or FCI-DSD). The Die SalesDivision continues its long tradition of providingwafer thinning, dicing, Automated OpticalInspection (AOI), Waffle Pack, and Tape & Reelservices.In 2005 FlipChip acquired a license to produce Electroless Ni/Au from the Fraunhofer/IZM Institute of Berlin. The initial target applications of E-less Ni/Au are high temperature power devices and low cost RFID applications. The new process was in commercial production in 2006.In 2006, FlipChip announced that it had entered into a joint venture with Millennium Microtech to form FlipChip Millennium Shanghai (FCMS). FCMS opened in March of 2007 and provides “Turn-Key” wafer bumping and die packaging services, focusing on the Asian market.In 2007, FlipChip entered into strategic partnerships with several domestic testing houses to provide Electrical Testing as part of Turn-Key wafer processing.In addition to bumping services, FlipChip has an aggressive program to develop and generate intellectual property for future implementation at FlipChip and for our licensee’s. Our commitment to leadership and quality in wafer bumping solutions continues, ensuring that FlipChip remains the leader in developing, and bringing to market, the latest bumping technology.The main bumping facility for FlipChip is located in the World Headquarters building in Phoenix, Arizona, USA. We have a state of the art, 16,000-ft2 (4700 m2) class 1000 clean room. FlipChip is ISO9001:2000 and ISO14001 certified.FCI World Headquarters –- Phoenix, AZ Die Sales Division -– Tempe, AZFCMS Bumping Facility -- Shanghai, China RoseStreet Labs Facility -- Phoenix, AZ3 Choosing a Bumping ProcessHere we look at the different bumping services offered by FlipChip. To make it easy, we have broken our services into the different processes. Each one is perfect for a different bumping situation, from the simplest to the most complex. Look these over and decide which process will meet your needs. If you still can’t decide, give us a call! We’ll be glad let you know which process will work best for you. We are experts at matching up a standard process flow to your device. Keep in mind that we are a development driven engineering organization. For unusual devices, we can often design a custom process flow that will completely meet your needs.3.1 Standard Flip Chip – Bump on I/OOur Standard Flip Chip (SFC) process, formerly known as the Flex-on-Cap (or FoC) process, was created in the mid-1960’s by Delco for use in the automotive industry. Today, the process has 40 years and over a million bumped wafers behind it. This is the process to use when you need to place small bumps (less than 135µm in height) directly on the die I/O. Pitch capabilities in this process are 150µm or greater for a full array I/O design and 120µm or greater for a peripheral I/O design. Typically, the number of bumps per die ranges from 4 to 6000. The SFC process uses premixed solder paste for the solder bumps. This provides for outstanding control of the alloy composition across the entire wafer. Since the process is not limited to the bi-metal restraints of an electroplating process, tri-metal alloys (such as Sn/Ag/Cu) require nothing more than the selection of the proper tube of pre-mixed solder paste. As with all die processed with small bumps, these die will require the use of underfill during packaging.To take advantage of this process flow, the device must meet some minimum I/O pad requirements (described below in section 3.1.2). If the device does not meet these minimum I/O pad requirements, take a look at section 3.2, which describes the SFC Repassivation flow. If you are looking for bump heights greater than 135µm, take a look at section 3.4, which covers the UltraCSP flow – the industry standard Wafer Level Package (WLP) process flow.3.1.1 Standard Flip Chip-Bump on I/O Process SummaryThe SFC-Bump on I/O process requires the fewest process steps of any flow that FlipChip offers. Below is an outline of the flow:UBM3.1.2 I/O requirements for the SFC-Bump on I/O processSince the SFC-Bump on I/O process forms a bump directly on the device I/O, certain criteria must be followed to ensure a proper bump structure. The basic rule is what we call “The Golden Rule of Flip Chip”, which is:•The UBM must overlap the I/O passivation opening by at least 7µm and the I/O final metal pad must extend at least 5µm past the end of the UBM.Figure 1 shows the “Golden Rule” requirements for the UBM in relation to the passivation opening and the I/O metal bond pad. This rule requirement accomplishes several reliability requirements. The overlap of the UBM to the passivation opening provides a seal to the underlying I/O aluminum bond pad. The overlap of the UBM inside the I/O metal bond pad eliminates stresses that can cause silicon cratering.Figure 1. The Golden Rule of Flip ChipThe allowable size of the UBM is directly related to I/O Pitch. The bump height is strongly influenced by UBM size. Please see the section 5.1 “Pitch, UBM Size, and Bump Height Relationships” as a guide as to what size your UBM will be.If your device does not meet the requirements of the Golden Rule, your device may be a candidate for the SFC-Repassivation process, which is described in the next section.3.2 Standard Flip Chip--RepassivationThe SFC-Repassivation process is similar to the SFC-Bump on I/O process, but it is designed for die that do not meet all of the I/O final metal pad and passivation opening requirements of SFC-Bump on I/O. In this process, a layer of Benzocyclobutene (or BCB) repassivation is deposited on the die before bumping. The BCB passivation corrects for the issue of the I/O passivation opening being too large for a standard flip chip bump. It also corrects for the issue of the I/O final metal pad being too small for a standard flip chip bump. The BCB layer planarizes the device surface and gives the bump structure additional strength and robustness.As with SFC-Bump on I/O, SFC-Repassivation is designed for small bumps (less than 135µm) placed directly on the die I/O. Pitch capabilities in this process are 150µm or greater for a full array I/O design and 140µm or greater for a peripheral I/O design. The number of bumps per die typically ranges from 4 to 600. The SFC-Repassivation process uses premixed solder paste for the solder bumps. This provides for outstanding control of the alloy composition across the entire wafer. Since the process is not limited to the bi-metal restraints of an electroplating bath, tri-metal alloys (such as Sn/Ag/Cu) require nothing more than the selection of the proper tube of pre-mixed solder paste. As with all die processed with small bumps, die bumped with the SFC-Repassivation process will require the use of underfill during packaging.If your device contains bumps that will not be placed directly on the I/O, take a look at the next section (3.3), which describes the SFC-Redistribution flow. If you are looking for bump heights greater than 140µm, take a look at section 3.4, which covers the UltraCSP flow – the industry standard Wafer Level Chip Scale Package (WL-CSP) process flow.3.2.1 SFC-Repassivation Process SummaryThe SFC-Repassivation process requires relatively few process steps to complete the flow. Below is an outline of the process flow (none of the drawings are to scale):Deposit and pattern a layer of BCB passivation.Deposit three layer (Al/NiV/Cu) Under Bump Metalization (or UBM) stack.Pattern UBM pads.Deposit pre-mixed solder paste.Reflow solder.- PIQ3.3 Standard Flip Chip--RedistributionOn some die, the I/O are not located where you need to have the bumps. This is especially true when you take an existing die that is wire bonded and would like to convert it to flip chip. The SFC-Redistribution Line (or RDL) process adds “redistribution metallization” (often called “runners’ or “traces”) that let you re-route the signal path from the die peripheral I/O to the new desired bump locations. This process is usually seen as a transitional solution between a die that is designed for wire bonding and a die that is designed for flip chip. Redistribution is designed to produce bumps of less than 135µm in height, although the typical bump height is 100µm. Pitch capabilities in this process are 70µm or greater. Standard Redistribution line widths are 38µm with 38µm space between lines. For fine pitch designs, FlipChip will go down to 25µm lines and 12µm space between lines. Since the process is not limited to the bi-metal restraints of an electroplating bath, tri-metal alloys (such as Sn/Ag/Cu) require nothing more than the selection of the proper tube of pre-mixed solder paste. As with all die processed with small bumps, these die will require the use of underfill during packaging.3.3.1 SFC-Redistribution Process SummaryThe SFC-Redistribution process requires more process steps than the SFC-Bump on I/O or the SFC-Repassivation flows. Below is an outline of the SFC-Redistribution process flow (none of the drawings are to scale):Deposit and pattern first layer of BCB passivation (BCB1).Deposit four layer (Al/NiV/Cu/Ti) UBM stack.I/O Final Metal Bond padEtch UBM stack to form redistribution runners and bump pads.Deposit, pattern, and cross-link second layer of BCB passivation (BCB2).Deposit solder paste (Proprietary Process).Reflow solder.Cu UBM3.4 Spheron TM WLCSPFlipChip offers a new type of Wafer Level Chip Scale Packaging (WLCSP) that utilizes a unique dielectric material, which offers improved capacitance decoupling and reliability. In addition to the advanced polymer, Spheron WLP TM incorporates a new metal structure, which offers improved strength and electrical performance. Benefits of Spheron WLP include: improved electrical performance, reduced capacitive coupling between UBM/Solder and the underlying IC circuitry, improved solder joint reliability, significant improvement in TC performance due to die planarization/polymer film characteristics, and elimination of incoming wafer topology issues. In addition, the planarized polymer film ensures proper UBM step coverage, even over non-planarized devices. Spheron is compatible with nitrides and oxides.As with Ultra CSP, pre-formed solder balls of 250µm to 500µm are placed on the wafer and reflowed for final bump heights of 200µm to 400µm. In this process, the bumps can be placed directly on the device I/O’s or the signal may be redistributed to a more desirable die location. Typically, the number of bumps per die is 4 – 100. Die bumped with Spheron WLP typically do not require underfill. Spheron WLCSP, as well as all FlipChip packages, is classified as JEDEC Level 1 compliant.3.4.1 Spheron WLP™ Redistribution Process FlowThe Spheron WLP process may be used to bump directly on I/O or may be used to redistribute bumps to a more desirable die location. An example of the redistributed process is shown (none of the drawings are to scale).I/O Final Metal Bond Wafer Silicon Device PassivationCoat first dielectric layer (Spheron1), expose, develop, and cure.Sputter metal redistribution layer. Pattern and etch to form redistribution runners.Coat second dielectric layer (Spheron2), expose, develop, and cross-link.Deposit and pattern three layer UBM (Al/NiV/Cu).Attach pre-formed solder ball.Reflow Solder3.5 Ultra CSP®Ultra CSP® is our patented Wafer Level Chip Scale Package (or WLCSP) process. Since its introduction in 1998, Ultra CSP has become the industry standard for WLCSP. Bump heights for the process range from 200µm to 450µm. In this process, pre-formed solder balls of 250µm to 500µm are placed on the wafer and reflowed. The bumps can be placed directly on the device I/O’s or the signal may be redistributed to a more desirable die location. Typically, the number of bumps per die is 4 – 100. Die bumped with Ultra CSP do not require underfill until the bump array reaches the 6x6 to 7x7 size. Then underfill may be needed. The lack of underfill makes it easy to migrate TSOP or QFP to Ultra CSP. Ultra CSP, as well as all FlipChip packages, is classified as JEDEC Level 1 compliant.3.5.1 Ultra CSP Process SummaryThe UltraCSP process may be used to bump directly on I/O or may be used to redistribute bumps to a more desirable die location. Both processes are summarized below (none of the drawings are to scale).3.5.1.1 Ultra CSP Bump on I/O -- Process FlowDeposit and pattern a layer of BCB passivation.Deposit three layer (Al/NiV/Cu) Under Bump Metalization (or UBM) stack.Pattern UBM pads.Attach pre-formed solder ballReflow solder.3.5.1.2 UltraCSP Redistributed -- Process FlowDeposit and pattern first layer of BCB passivation (BCB1).Deposit three layer (Al/NiV/Cu) UBM stack.I/O Final Metal Bond padPattern UBM Pads and Runners.Deposit, pattern, and cross-link second layer of BCB passivation (BCB2).Attach Pre-formed Solder Ball.Reflow solder.3.6 Elite UBM™, Elite FC™, and Elite CSP™ – Electroless Ni/AuIn 2005 FlipChip acquired a license to produce Electroless Ni/Au (E-less Ni/Au) from the Fraunhofer/IZM Institute of Berlin. E-less Ni/Au is available in three configurations: EliteUBM, EliteFC, and EliteCSP. EliteUBM is simply a Ni/Au pad ranging in height from 5µm to 30µm. Typical applications for EliteUBM are low cost RFID tags. Elite packages, as well as all FlipChip packages, are classified as JEDEC Level 1 compliant.EliteFC is a Flip Chip size bump that uses the low cost E-less Ni/Au UBM. Typical bump heights are 70µm - 160µm. EliteFC can often be used as a lower cost alternative to traditional Standard Flip Chip.EliteCSP is a Wafer Level-Chip Scale Package (WL-CSP) that uses the E-less UMB structure. As with Ultra CSP, pre-formed solder balls of 250µm to 500µm are placed on the wafer and reflowed for final bump heights of 200µm to 400µm. Typical applications for EliteCSP are high power / high temperature devices.Devices that are to be bumped using any of the Elite processes need to have some special requirements met. These requirements are described in Section 4.3.12.3.6.1 Elite UBM™ – Process FlowClean Aluminum/Cu Final Metal Pad.ZincApply a thin layer of Zinc to the AlCu PadSubstitute NiP for the ZincCoat UBM with a thin layer of Gold (oxidation protection).3.6.2 Elite FC™ – Process FlowDevice PassivationClean Aluminum/Cu Final Metal Pad.ZincApply a thin layer of Zinc to the AlCu PadSubstitute NiP for the ZincCoat UBM with a thin layer of Gold (oxidation protection).Deposit pre-mixed solder paste.Reflow Solder3.6.3 Elite CSP ™ – Process FlowClean Aluminum/Cu Final Metal Pad.Apply a thin layer of Zinc to the AlCu PadSubstitute NiP for the ZincDevice Passivation ZincCoat UBM with a thin layer of Gold (oxidation protection).Attach pre-formed solder ball.Reflow Solder3.7 Available Solder AlloysFlipChip offers several different solder alloys to mach your needs. By using pre-mixed solder paste and pre-formed solder balls, alloy composition is very tightly controlled. This means that your solder balls have predictable and reliable reflow characteristics.3.7.1 Basic Physical Properties of Solder Paste AlloysThe SFC-Ball on I/O, SFC-Repassivation, and SFC-Redistribution processes use pre-mixed solder paste to form the final solder bumps. The table below gives the basic properties of the paste alloys (for complete physical properties of solder alloys, see section 6.3).Table 1. Physical Proprieties of Paste AlloysAlloy / Property Sn/Ag/Cu Lead Free (SAC 351) 63Sn37Pb Standard EutecticAlloy Composition Sn 95.5%Ag 3.5%Cu 1.0%Sn 63%Pb 37%Melting 217°C Eutectic 183°C EutecticReflow Temperature 235°C to 255°C 215°C to 225°CAlpha Emissions(counts/cm2/hr)<0.002 N/A3.7.2 Basic Physical Properties of Pre-Formed Solder Ball AlloysThe Ultra CSP, Spheron, and Polymer Collar WLP processes use pre-formed solder balls. Thestandard solder ball sizes are 0.25mm (250µm), 0.3mm (300µm), 0.35mm (350µm), 0.4mm(400µm), and 0.5mm (500µm). The basic physical properties of the pre-formed solder balls arelisted on the table below (for complete physical properties of solder alloys, see section 6.3).Table 2. Physical Proprieties of Pre-Formed Solder Ball AlloysAlloy / Property Sn/Ag/Cu LeadFree (SAC 266) Enhanced Lead FreeSn/Ag/Cu (SAC 105)Eutectic63Sn37PbHigh Lead95Pb5SnAlloy Composition Sn 96.8%Ag 2.6%Cu 0.6%Sn 98.5%Ag 1.0%Cu 0.5%DopantSn 63%Pb 37%Sn 5%Pb 95%Melting Point 218°C – 220°C 218°C – 220°C 183°CEutectic 308°C - 314°CReflow Temperature 235°C to 255°C 235°C to 255°C 215°C to225°C 325°C to 335°CAlpha Emissions (counts/cm2/hr) <0.002 <0.002 N/AN/A3.8 Other Services3.8.1 Laser MarkFor die identification and traceability, FlipChip gives you theoption of using a Laser to mark the backside of each die.FlipChip can mark any alphanumeric character down to aminimum character size of 0.20 mm square with a characterdepth of approximately 4 - 6µm. Simple graphics includingcircles, squares, triangles, etc. can be used for the optionalpin 1 indicator. We can even mark simplified graphicsconsisting of basic shapes including circles, squares,triangles, etc. for company logos. FlipChip has thecapability to mark accurately any die to a minimum diedimension of 0.8 mm. If you need custom designs, giveFlipChip a call. We can custom match a laser program foryour needs.3.8.2 “In Process” BackgrindMany times, wafers need to be thinned to meet final packaging requirements. For Ultra CSP, Spheron WLP, EliteCSP, and Polymer Collar WLP, FlipChip has the ability to backgrind wafers, during processing, just before the solder balls are applied. Wafers are course ground with a wheel of 320 – 360 grit and polished ground with a wheel of 2000 grit. Below are our backgrinding/processing capabilities. (For thickness requirements on incoming wafers, please see section 4.2.7 “Incoming Wafer Thickness.”) Please contact FlipChip if you have thinner backgrinding requirements.Table 3. Wafer Thickness After “In Process WL-CSP” BackgrindingWafer Size 6 inch (150mm) 8 inch (200mm)Minimum Wafer Thickness After Backgrind 14 mil(356µm)14 mil (456µm)3.8.3 “Post Process” BackgrindFor Standard Flip Chip (SFC), Repassivated Standard Flip Chip (RP-SFC) and Redistributed Standard Flip Chip (RP-SFC), FlipChip has the ability to backgrind wafers, after the bumping process is completed Wafers are course ground with a wheel of 320 – 360 grit and polished ground with a wheel of 2000 grit. Below are our backgrinding/processing capabilities. Please contact FlipChip if you have thinner backgrinding requirements.Table 4. Wafer Thickness After “Post Process SFC” BackgrindingWafer Size 6 inch (150mm) 8 inch (200mm)Minimum Wafer Thickness After Backgrind 12 mil(305µm)12 mil (305µm)3.8.4 Electronic Wafer Yield MapsWafer yield mapping data is either presented on paper (shipped with the wafers) or by electronic wafer maps (transmitted over secure FTP sites). FlipChip uses Simplified INF (SINF), the industry standard file format, for all electronic wafer maps. FTP sites can be easily and quickly set up for secure data transfer. Contact FlipChip for details.3.8.5 Post Bump Electrical TestingAfter bumping, FlipChip can have the dice electrically tested on a variety of test platforms including:•Advantest•Agilent / HP•Credence•Eagle•Credence•Nextest•LTX•TeradyneContact FlipChip for a complete description of electrical testing capabilities.3.8.6 Dicing and PackagingIf desired, FlipChip will have your finished wafers diced, to your specifications. After dicing, visual inspection, either by sampling or 100% will be performed. The die will then be packaged in tape-and-reel or waffle pack configurations. For complete dicing and packaging descriptions and capabilities, contact FlipChip.4 Design Rules and Guidelines4.1 OverviewFlipChip has developed a set of design rules and guidelines to ensure that your wafers will be processed successfully. These rules allow for FlipChip to use standardized process flows using industry standard process equipment. FlipChip has extensive data that shows the reliability of devices processed under these design rules. The rules presented below represent a generalization of the actual FlipChip Design Specifications, which are subject to revisions and may not apply to all devices. If you have wafers that do not meet these guidelines or if you have any questions, give FlipChip a call. Since we are a development driven engineering organization, we can often create a custom solution to for even the most unusual bumping situation. We will always work with you to ensure your total satisfaction.4.2 Incoming Wafer Requirements4.2.1 Types of WafersFlipChip can process Silicon (all types) and Silicon/Germanium wafers. Contact FlipChip if you have other types of wafers (Quartz, Sapphire, etc.), we will discuss our capabilities on non-standard wafer types. FlipChip cannot currently process GaAs wafers.4.2.2 SEMI Material RequirementsAll wafers must meet current SEMI material requirements. These specifications cover major areas such as: wafer diameter (dimension and tolerance), polish, edge profile, notches, and major and minor flat sizes, locations, and orientations. It is highly recommend that 8-inch (200 mm) wafers have a notch rather than a flat.4.2.3 Wafer Scribe RequirementsIt is highly recommended that each wafer have a unique scribe number. Typically, the device lot number and the wafer number (within the lot) are scribed on each wafer.4.2.4 Wafer Backside RequirementsFor proper processing, the backside must be smooth, without ridges, bumps, or protrusions. The backsides of incoming wafers ideally should be exposed Silicon or Silicon/Germanium. Some types of backside coatings are acceptable. Call FlipChip if your wafers are backside coated.4.2.5 Acceptable Wafer SizeFlipChip accepts wafers of the following sizes: 6 inch (150mm), and 8 inch (200mm). If you have other wafer sizes, contact FlipChip and we will discuss our capabilities on non-standard wafer sizes.。

MFG 常用英文单字Semiconductor半导体导体、绝缘体和半导体主要依据导电系数的大小，决定了电子的移动速度。

导体：金、银、铜、铁、人、水……导电系数大，传导容易绝缘体：塑料、木头、皮革、纸……导电系数小、传导不容易半导体：硅中加锗、砷、镓、磷……平时不导电加特定电压后导电Wafer 芯片或晶圆：原意为法国的松饼，饼干上有格子状的饰纹，与FAB内生产的芯片图形类似。

Lot 批；一批芯片中最多可以有25片，最少可以只有一片。

ID Identification的缩写。

用以辨识各个独立的个体，就像公司内每一个人有自己的识别证。

Wafer ID 每一片芯片有自己的芯片刻号，叫Wafer ID。

Lot ID 每一批芯片有自己的批号，叫Lot ID。

Part ID 各个独立的批号可以共享一个型号，叫Part ID。

WIP Work In Process，在制品。

从芯片投入到芯片产品，FAB内各站积存了相当数量的芯片，统称为FAB内的WIP 。

一整个制程又可细分为数百个Stage和Step，每一个Stage所堆积的芯片，称为Stage WIP。

Lot Priority 每一批产品在加工的过程中在WIP中被选择进机台的优先级。

Super Hot Run的优先级为1，视为等级最高，必要时，当Lot在上一站加工时，本站便要空着机台等待Super Hot Run。

Hot Run的优先级为2，紧急程度比Super Hot Run次一级。

Normal的优先级为3，视为正常的等级，按正常的派货原则，或视常班向生产指令而定。

Cycle time 生产周期，FAB Cycle Time 定义为：从芯片投入到芯片产生的这一段时间。

Stage Cycle Time：Lot从进站等候开始到当站加工后出货时间点截止。

Spec. 规格Specification的缩写。

产品在机台加工过程中，每一站均设定规格。

机台加工后，产品或控片经由量测机台量测，该产品加工后，是否在规格内。

VDX-6372RD/VDX-6372RD-Plus DM&P Vortex86DX 600MHzPC/104 CPU Modulewith 2S/2USB/VGA/LCD/GPIO/PWMx16128MB DDR2 OnboardUser’s Manual(Revision 1.1A)CopyrightThe information in this manual is subject to change without notice for continuous improvement in the product. All rights are reserved. The manufacturer assumes no responsibility for any inaccuracies that may be contained in this document and makes no commitment to update or to keep current the information contained in this manual.No part of this manual may be reproduced, copied, translated or transmitted, in whole or in part, in any form or by any means without the prior written permission of the ICOP Technology Inc..Copyright 2008 ICOP Technology Inc.Manual No. IUM6372D000-01 Ver.1.0ATrademarks AcknowledgmentVortex86DX is the registered trademark of ICOP Technology Inc.Other brand names or product names appearing in this document are the properties and registered trademarks of their respective owners. All names mentioned herewith are served for identification purpose only.T a b l e o f C o n t e n t sT a b l e o f C o n t e n t s ............................................................. i iiC h a p t e r 1 Introduction (1)1.1 Packing List (1)1.2 Product Description (1)1.3 Specifications (3)1.4 Board Dimension (5)C h a p t e r 2 Installation (6)2.1 Board Outline (6)2.2 Connectors & Jumpers Location .................... .. (7)2.3 Connectors & Jumpers Summary (9)2.4 Pin Assignments & Jumper Settings (10)2.5 System Mapping (19)2.6 Watchdog Timer (23)2.7 GPIO (24)2.8 SPI flash (25)2.9 PWM (26)3.0 IDE to SD (27)C h a p t e r 3 Driver Installation (28)Appendix (29)A. TFT Flat Panel Data Output (29)B. TFT Flat Panel Support List (30)C. LVDS Flat Panel Support List (32)D. Flat Panel Hardware Setting (33)E. Flat Panel Wiring and Lighting (34)F. TCP/IP library for DOS real mode (35)G. BIOS Default Setting (36)Warranty (37)This page is blankC h a p t e r 1 Introduction1.1 Packing ListProduct NamePackageVDX-6372RD&VDX-6372RD-PlusEmbedded Vortex86DX CPU All-in-One Board Manual & Drivers CD x 1 RS232 cable x 2 PRINT cable x1 IDE cable x 1USB cable x 1 (USB port x 2) VGA cable x 1 GPIO cable x 1PS/2 Keyboard cable x 1 Screw Kit x 11.2 Product DescriptionThe VDX-6372RD family of low-power x86 embedded controller is designed to meet PC/104 specification, and integrated with the following features.600 MHz Vortex86DX SoCVGA, TFT/ LVDS LCD support up to 1280x1024 resolution128MB DDR2 system memoryEnhanced IDE (UltraDMA-100/66/33) 2 USB 2.0 (host)Up to 2 serial portsParallel port16-bit GPIOs PC/104-Plus expansion busMeet PC/104 stacking spec.2 watchdog timerPWM 16~24 channelsJTAG interfaceAMI BIOSSingle voltage +5V DCSupport extended operatingtemperature range of -20°C to +70°CThe VDX-6372D PC/104 family of embedded controller is designed with backward compatibility in mind, to provide migration path for projects facing end-of-life challenges with their existing x86 based PC/104 controller. The VDX-6372D family of controller is designed as a plug in replacement, with backward compatibility to support legacy software to help extend existing product life cycle without heavy re-engineering.VDX-6372D is suitable for broad range of data-acquisition, Industrial automation, Process control, Automotive controller, AVL, Intelligent Vehicle management devic,Medical device, Human machine interface, Robotics, machinery control And more…application that required small footprint, low-power and low-cost hardware with open industry standard such as PC/104.1.3 SpecificationsFeatures VDX-6372RD CPU DM&P SoC CPU Vortex86DX- 600MHzReal Time Clock with Lithium Battery Backup Cache L1:16K I-Cache, 16K D-Cache, L2 Cache 128KBBIOS AMI BIOSBus Interface PC/104 Standard Compliant (Optional: PCI-104)System Memory 128MB DDR2 OnboardWatchdog Timer Software programmable from 30.5 us to 512 seconds x2sets(Watchdog 1 fully compatible with M6117D) VGA XGI Volari Z9s ChipsetVGA and TFT Flat Panel Interface SupportLVDS Flat Panel Interface Support (Optional)Onboard 32MB VGA MemorySupport resolution up to 1280 x 1024,16MB colorsI /O Interface Enhanced IDE port (UltraDMA-100/66/33) x1 RS-232 port x1RS-232/422/485 port x1 (RS485: Auto Direction)Parallel port x116-bit GPIO port x1Connectors 2.00 mm ∅ 44-pin box header for IDE x12.00 mm ∅ 44-pin box header for LCD x 12.00 mm ∅ 10-pin box header for VGA x12.00 mm ∅ 10-pin box header for USB x12.00 mm ∅ 26-pin box header for Print x12.00 mm ∅ 20-pin box header for 16-bit GPIO x12.00 mm ∅ 10-pin box header for RS-232 x22.54 mm ∅ 5-pin box header for Keyboard x12.54 mm ∅ 5-pin header for Mouse x12.54 mm ∅ 4-pin header for DC-in x12.54 mm ∅ 3-pin header for RS-485 x12.54 mm ∅ 2-pin header for Reset x12.54 mm ∅ 7-pin header for Redundancy x1(Opt)2.54 mm ∅ 2-pin header for SYS-Fail-SW- x1(Opt)1.25 mm ∅ 6-pin Wafer for JTAG x1Flash Disk Support44-pin IDE to Micro SD (Optional)PWM 16~24 channelsPower Requirement Single Voltage +5V@ 600mA Dimension 90 X 96mm (3.54 x 3.77 inches) Weight 80gOperating Temperature -20o C ~ +70o C-40°C ~ +85°C (Optional)1.4 Board DimensionC h a p t e r 2Installation2.1 Board Outline(Note1: COM2 RS232/422/485 is selected by BIOS setting) (Note2: PCI-104 connector is optional)(Note3: VI/O Default setting of PCI-104 connector is +5V) (Note4: Redundancy Signal and System-Fail-SW are optional)2.2 Connectors & Jumpers Location ConnectorsJumpers & LEDs2.3 Connectors & Jumpers SummarySummary TableNbr Description Type of Connections Pin nbrs.J1 IDE Box Header, 2.0∅ ,22x2 44-pinJ2 USB Box Header,2.0∅ , 5x2 10-pinJ5 JTAG Wafer, 1.25∅ , 6x16-pinJ6 Reset Pin Header, 2,54∅,1x2 2-pinJ7 Redundancy (Optional) Pin Header, 2.54∅, 7x1 7-pinJ8 System –Fail-Switch (Optional) Pin Header, 2.54∅ , 2x1 2-pinJ9 PS/2 Keyboard Box Header, 2,54∅,1x5 5-pinJ10 PS/2 Mouse Pin Header, 2,54∅,1x5 5-pinJ11 COM1(TTL/GPIO-P4 / PWMx8) Box Header, 2.0∅ 5x2 10-pinJ12 COM2(RS232/422/485) Box Header, 2.0∅ 5x2 10-pinJ13 GPIO ( Port 0 / 1 /PWMx16) Box Header, 2.0∅ ,10x220-pinJ15 RS-485 (Auto direction) Molex Header,2.54∅, 3x1 3-pinJ16 Power Connector Terminal Block 5.0∅,2x1 2-pinJ18 PRINT Box Header, 2.0∅ , 13x2 26-pinJ20 PC104 Connector – 64 pin Box Header, 2.54∅ 32x2 64-pinJ21 PC104 Connector – 40 pin Box Header, 2.54∅ 20x2 40-pinJ23 PC/104 + (Optional) Box Header, 2.0∅ , 30x4 120-pinJ24 VGA Box Header, 2.0∅ ,5x2 10-pinJ25 LCD Connector Box Header,2.0∅ ,22x2 44-pinPWR-Power Active LED (Red) LED-SMDLEDIDE-IDE Active LED (Green ) LED-SMDLEDMTBF-MTBF-Out (Orange) LED-SMDLED2.4 Pin Assignments & Jumper SettingsJ1: IDE (44 Pins)J2: USBPin # Signal Name Pin # Signal Name 1 VCC 2 VCC 3 LUSBD3- 4 LUSBD2- 5 LUSBD3+ 6 LUSBD2+ 7 GND 8 GND 9 GGND 10 GGNDPin # Signal Name Pin # Signal Name 1 IDERST 2 GND 3 IDED7 4 IDED8 5 IDED6 6 IDED9 7 IDED5 8 IDED10 9 IDED4 10 IDED11 11 IDED3 12 IDED12 13 IDED2 14 IDED13 15 IDED1 16 IDED14 17 IDED0 18 IDED15 19 GND 20 NC 21 IDEREQ 22 GND 23 IDEIOW 24 GND 25 IDEIOR 26 GND 27 ICHRDY 28 GND 29 IDEACK 30 GND 31 IDEINT 32 NC 33 IDESA1 34 IDECBLID 35 IDESA0 36 IDESA2 37 IDECS-0 38 IDECS1 39 IDELED 40 GND 41 VCC 42 VCC 43 GND 44 NCJ5: JTAGPin # Signal Name Pin # Signal Name1 VCC2 GND3 TCK4 TDO5 TDI6 TMSJ6: RESETPin # Signal Name Pin # Signal Name1 RST_SW2 GNDJ7: Redundancy (Optional)Pin # Signal Name Pin # Signal Name1 GND2 SYS-FAIL-OUT3 SYS-FAIL-IN4 GPCS05 SYS-GPCS-IN6 TXD9\7 RXD9\J8: System-Fail-Switch (Optional) Pin # Signal Name1 SYS-SW-IN2 GNDJ9: PS/2 KeyboardPin # Signal Name Pin # Signal Name1 KBCLK2 KBDAT3 NC4 GND5 VCCJ10: PS/2 MousePin # Signal Name Pin # Signal Name1 MSCLK2 MSDATA3 NC4 GND5 VCCJ11: COM 1 (Optional: TTL/ GPIO-P4 / PWMx8)Pin # SignalNamePin #SignalName1 DCD12 RXD13 TXD14 DTR15 GND6 DSR17 RTS1 8 CTS19 RI1 10 NCJ12: COM2 RS232 / 422 / 485 (Optional: TTL)Pin # Signal Name Pin # Signal Name1 DCD2/ 422TX- / RS485-2 RXD2 / 422TX+ / RS485+3 TXD2 / 422RX+4 DTR2 / 422RX-5 GND6 DSR27 RTS2 8 CTS29 RI2 10 NCJ13: GPIO (Port 0 / 1/ PWMx16)Pin # Signal Name Pin # Signal Name1 GND2 VCC3 GP004 GP105 GP016 GP117 GP02 8 GP129 GP03 10 GP1311 GP04 12 GP1413 GP05 14 GP1515 GP06 16 GP1617 GP07 18 GP1719 VCC 20 GNDJ15: RS485 (Auto direction)Pin # Signal Name1 RS485＋2 RS485－3 GNDJ16: Power Connector (Terminal Block 5.0mm) Pin # Signal Name1 +5V2 GNDJ18: PRINTPin # Signal Name Pin # Signal Name1 STB- 14 AFD-2 PD0 15 ERR-3 PD1 16 INIT-4 PD2 17 SLIN-5 PD3 18 GND6 PD4 19 GND7 PD5 20 GND8 PD6 21 GND9 PD7 22 GND10 ACK- 23 GND11 BUSY 24 GND12 PE 25 GND13 SLCT 26 NCJ20: PC104 Connector – 64pin Pin # Signal Name Pin # Signal Name1 IOCHCHK *2 GND3 SD74 RESETDRV5 SD6 6 VCC7 SD5 8 IRQ99 SD4 10 -5V11 SD3 12 DRQ2 13 SD2 14 -12V15 SD1 16 OWS 17 SD0 18 +12V 19 IOCHRDY 20 GND21 AEN 22 SMEMW * 23 SA19 24 SMEMR * 25 SA18 26 IOW * 27 SA17 28 IOR * 29 SA16 30 DACK3 * 31 SA15 32 DRQ3 33 SA14 34 DACK1 * 35 SA13 36 DRQ1 37 SA12 38 REFRESH * 39 SA11 40 SYSCLK 41 SA10 42 IRQ7 43 SA9 44 IRQ6 45 SA8 46 IRQ5 47 SA7 48 IRQ4 49 SA6 50 IRQ3 51 SA5 52 DACK2 * 53 SA4 54 TC55 SA3 56 BALE 57 SA2 58 VCC59 SA1 60 OSC 61 SA0 62 GND 63 GND 64 GNDJ21: PC104 Connector – 40pin Pin # Signal Name Pin # Signal Name1 GND2 GND3 MEMCS16 *4 SBHE *5 IOCS16 * 6 SA237 IRQ10 8 SA229 IRQ11 10 SA21 11 IRQ12 12 SA20 13 IRQ15 14 SA19 15 IRQ14 16 SA18 17 DACK0 * 18 SA17 19 DRQ0 20 MEMR * 21 DACK5 * 22 MEMW * 23 DRQ5 24 SD8 25 DACK6 * 26 SD9 27 DRQ6 28 SD10 29 DACK7 * 30 SD11 31 DRQ7 32 SD12 33 VCC 34 SD13 35 MASTER * 36 SD14 37 GND 38 SD15 39 GND 40 NCJ23: PC/104 + (Optional)VI/O Default setting: +5VIf you need to use VI/O as +3.3V, please see the page 19. Pin # A B C D1 GND NC +5V AD002 VI/O(+5V) AD02 AD01 +5V3 AD05 GND AD04 AD034 C/BE0# AD07 GND AD065 GND AD09 AD08 GND6 AD11 VI/O(+5V) AD10 GND7 AD14 AD13 GND AD128 +3.3V C/BE1# AD15 +3.3V9 SERR# GND NC PAR10 GND PERR# +3.3V NC11 STOP# +3.3V LOCK# GND12 +3.3V TRDY# GND DEVSEL#13 FRAME# GND IRDY# +3.3V14 GND AD16 +3.3V C/BE2#15 AD18 +3.3V AD17 GND16 AD21 AD20 GND AD1917 +3.3V AD23 AD22 +3.3V18 IDSEL0 GND IDSEL1 IDSEL219 AD24 C/BE3# VI/O(+5V) IDSEL320 GND AD26 AD25 GND21 AD29 +5V AD28 AD2722 +5V AD30 GND AD3123 REQ0# GND REQ1# VI/O(+5V)24 GND REQ2# +5V GNT0#25 GNT1# VI/O(+5V) GNT2# GND26 +5V CLK0 GND CLK127 CLK2 +5V CLK3 GND28 GND INTD# +5V RST#29 +12V INTA# INTB# INTC#30 -12V NC NC GNDPlease remove the 0 ohm (1206 type) of R212 and add 0 ohm (1206 type) on R213J24: VGAPin # SignalNamePin #SignalName1 R OUT2 GND3 G OUT4 GND5 B OUT6 GND7 HSYNC 8 GND9 VSYNCD 10 GNDJ25: LCD (DVO) ConnectorPin # Signal Name Pin # Signal Name1 +3.3V2 +3.3V3 LG24 LG35 LG46 LG57 NC 8 NC9 LR0 10 LR111 LR2 12 LR313 LR4 14 LR515 GND 16 NC17 NC 18 NC19 NC 20 GND21 NC 22 NC23 LB0 24 LB125 LB2 26 LB327 LB4 28 LB529 NC 30 NC31 LG0 32 LG133 GND 34 GND35 NC 36 LCLK37 NC 38 LDE39 NC 40 LHSYNC41 NC 42 LVSYNC43 LBACKL 44 LVDDEN(Please refer to Appendix A, for TFT Flat Panel Data Output)2.5 System Mapping2.6 Watchdog TimerThere are two watchdog timers in Vortex86SX/DX CPU. One is compatible with M6117D watchdog timer and the other is new. The M6117D compatible watchdog timer is called WDT0 and new one is called WDT1.We also provide DOS, Linux and WinCE example for your reference. For more technical support, please visit: /tech or download the PDF file:/tech/vortex86dx/2.7 GPIO (General Purpose Input / Output)40 GPIO pins are provided by the Vortex86SX/DX for general usage in the system. All GPIO pins are independent and can be configured as inputs or outputs, with or without pull-up/pull-down resistors.We also offer DOS, Linux and WinCE example for your reference. For more technical support, please visit: /tech or download the PDF file:/tech/vortex86dx/2.8 SPI flash (Serial Peripheral Interface)As SPI Flash (Serial Peripheral Interface) offers many benefits including: reduced controller pin count, smaller and simpler PCBs, reduced switching noise, less power consumption, and lower system costMany of users may consider using a formatted SPI flash to boot for the system or emulate SPI flash as Floppy (A: Driver or B: Driver). Then you must know how to set for this condition in CMOS Setup and boot up under DOS 6.22, X-DOS, DR-DOS and Free DOS.For more technical support, please visit: /tech or download the PDF file: /tech/vortex86dx/2.9 PWM (Pulse-width modulation)Pulse-width modulation (PWM) of a signal or power source involves the modulation of its duty cycle, to either convey information over a communications channel or control the amount of power sent to a load.The popular applications of pulse width modulation are in speed control of electric motors, volume control of Class D audio amplifiers or brightness control of light sources and many other power electronics applications.The Vortex86DX SoC integrated 32 channels of PWM interface enabling the Automation, robotic industry to a New Age x86 SoC platform and we also offer the sample code of PWM which will guide the engineer to control the PWM functionality smoothly.For more inquire of this sample code that please contact our sales team or mail to:*************.tw3.0 IDE to SD (Micro-SD)Vortex86DX SoC also built-in simulation circuit to adapt SD to IDE in order to allow your system to recognize Micro-SD card as C: or D: DriverSD-1917: 44 pins IDE to SD Adapter is an ideal solution for industrial PC or embedded system and 44 pins IDE to SD Adapter can be easily installed on all Vortex86DX-63xx CPU boards. You or your customers just do the BIOS setting and use SD-1917 to connect IDE connector of Vortex86DX-63xx directly.For further inquiries of SD-1917, please contact ICOP sales team or mail to: *************.tw for your request.<BIOS setting>Get into the BIOS setup UtilityChoose Primary IDE Pin Select: SD cardPress “F10” to Save configuration changes and exit setupSD-1917SD-1917: /pddetail.aspx?id=125&pid=4C h a p t e r 3Driver InstallationVGAThe Vortex86DX processor also use external Display chip ““Volari™ Z9s” which is an ultra low powered graphics chipset with total power consumption at around 1-1.5 W. It is capable in providing VGA display output upto 1600x1200. With DVO interface, developers could easily connect flat Panel to support TFT and LVDS output.Operating system supportThe Vortex86DX-6372RD PC/104 CPU board supports Embedded software: Free DOS, DOS 6.22, PCDOS 7.1, DR-DOS, x-DOS, OS/2, Windows CE 6.0, Windows 98, Windows XP Professional, Windows Embedded standard (XPE) and Windows 2000 (SP4).Please get the drivers from the Driver CD which attached with the standard packing of Vortex86DX-6372RD board or please get it from DMP official website:/tech/vortex86dx/Vortex86DX-6372RD also supports most of the popular Linux distributions, for more detail information, please visit DMP official website: /tech/vortex86dx/Appendix A. TFT Flat Panel Data OutputB. TFT Flat Panel Support ListSize Brand Resolution Model No.5.7” Data image 320x240 FG050701DSSWBG015.7” Optrex 320x240 55264GD057J-FW-ABN5.7” TOSHIBA 320x240 LTA057A343F5.7” Sharp 320x240 (QVGA / VGA) LQ057Q3DC025.7” Kyocera 320x240 (QVGA / VGA) TCG057QV1AC-G105.7” PVI 320x240 (QVGA / VGA) PD057VU4 /U55.7” Data image 640x480 FG050710DSSWJG01/DG015.7” Ampire 640x480 AM-640480GTMQW-T00H5.7” URT 640x480 UMSH-8004MD-T5.7” Sharp 640x480 LQ057V3DG015.7” CPT 640x480 CLAA057VA016.4” PVI 640x480 V16C6448AC6.4” LG-PHILIPS 640x480 LB064V026.4” PVI 640x480 PD064VT2 /VT4 /VT56.4” Sharp 640x480 LQ064V3DG017” AUO 800x480 C070VW02V07” Data image 800x480 FG0700A0DSSWBG01 7” LG-PHILIPS 800x480 (TFT 24 bits) LB070WV17” HITACHI 800x480 TX18D57VM2BAA7” Samsung 800x480 LMS700KF057” PVI 800x480 PM070WL47” URT 800x480 UMSH-8173MD-1T7” CHI HSIN 800x480 LW700AT93098” Sharp 640x480 LQ080V3DG01Size Brand Resolution Model No. 8” AUO 800x600 (TFT 24bits) A080SN01 V0 8.4” Sharp 800x600 LQ084S3DG01 10.4” PVI 640x480 PD104VT1/VT2 10.4” NEC 640x480 NL6448AC33-18 10.4” NEC 640x480 NL6448AC33-29 10.4” NEC 640x480 NL6448BC33-59 10.4” Sharp 640x480 LQ104V1DG51/DG61 10.4” Sharp 640x480 LQ10d368 11” Sharp 800x480 LQ110Y3DG01 12.1” NEC 800x600 NL8060BC31-01C. LVDS Flat Panel Support ListIf you would like to use LVDS Flat Panel with Vortex86SX / Vortex86DX series, please contact our regional sales to get ICOP-0096 information or visit ICOP website:/pddetail.aspx?id=65&pid=4ICOP–0096: 18-bit TFT to LVDS converter and Cable-LVDS-30: LVDS Cable 30cmApproved LVDS Flat Panel ListSize Brand Resolution Model No.3.5” PVI 640x480 PD035VL15” PVI 640x480 PD050VL16.5” AUO 640x480 G065VN018.4” AUO 800x600 G084SN038.9” AUO 1024x600 A089SW018.9” CPT 1024x600 CLAA089NA0ACW10.4” AUO 800x600 G104SN0212.1” AUO 800x600 G121SN0115” AUO 1024x768 G150XG01D. Flat Panel Wiring and LightingHardwareBefore you connect the TFT LCD Flat Panel with Vortex86DX-6372RD, please make sure the input Voltage of LCD is +3.3V or NotBIOSPlease contact or e-mail our regional sales to get the special BIOS for the any TFT LCD Flat Panels.Wiring LCD CablePlease refer to Page 19 (J25: LCD connector) and Page 29~34. For more LCD lightingand integration service, please contact our regional sales or mail to *************.tw if you have any questions.E. TCP/IP library for DOS real modeDSock is a TCP/IP library for DOS real mode, which is used by RSIP. It provides simple C functions for programmer to write Internet applications. ICOP also provide Internet examples using DSock: BOOTP/DHCP, FTP server, SMTP client/server, HTTP server, TELNET server, Talk client/server, etc.DSock provides a lot of example source code. Programmer can add Internet functions to their project easily and save development time. With a utility "MakeROM”, programmer also can make a ROM image to fit their application, those examples can be seen in the following Application systems: Mity-Mite Serial Server,Web Camera Tiny Server and RSIP Serial Server.DSock is free for All ICOP products using M6117D/Vortex86/Vortex86SX/Vortex86DX CPU and ICOP also provide the business version of DSock for those customers who are using other x86 CPUs.If you would like to use DSock or business version of DSock, Please mail to *************.tw or contact your regional sales.Please download the trial DSock software and Utilities from our website:/tech/dmp-lib/dsock/F. BIOS Default settingIf the system cannot be booted after BIOS changes are made, Please follow below procedures in order to restore the CMOS as default setting.Press “End” Key, when the power onPress <Del> to enter the AMI BIOS setupPress “F9” to Load Optimized DefaultsPress “F10” to Save configuration changes and exit setupWarrantyThis product is warranted to be in good working order for a period of one year from the date of purchase. Should this product fail to be in good working order at any time during this period, we will, at our option, replace or repair it at no additional charge except as set forth in the following terms. This warranty does not apply to products damaged by misuse, modifications, accident or disaster. Vendor assumes no liability for any damages, lost profits, lost savings or any other incidental or consequential damage resulting from the use, misuse of, originality to use this product. Vendor will not be liable for any claim made by any other related party. Return authorization must be obtained from the vendor before returned merchandise will be accepted. Authorization can be obtained by calling or faxing the vendor and requesting a Return Merchandise Authorization (RMA) number. Returned goods should always be accompanied by a clear problem description.。

球栅阵列舞厅式布局，超净间的布局 圆桶型反应室 阻挡层金属势垒电压backing film 背膜baffle vt ・ 困惑，阻碍，为难（挡片）baffle assembly n. 集合，装配，集会，集结，汇 编 （挡片块）丨 基极，基区 batch 批 bay and chase beam blow-up离子束膨胀 beam deceleration 束流减速分类代码号双极双极技术(工艺) bird ' s beak effect 鸟嘴效应blanket deposition 均厚淀积blower增压泵boat 舟BOE 氧化层刻蚀缓冲剂Bon voyage ［法］再见，一路顺风［平安］bonding pads 压点bonding wire 焊线，引线boron(B) 硼boron trichloride(BCL3) 三氯化硼boron trifluoride (B F3)三氟化硼borophosphosilicate glass(BPSG)硼磷硅玻璃borosilicate glass(BSG) 硼硅玻璃bottom antireflective coating(BARC)下减反射涂层boule单晶锭bracket n.墙上凸出的托架，括弧，支架v.括在一起breakthrough step 突破步骤，起始的干法刻蚀步骤brightfield detection 亮场检查brush scrubbing 涮洗bubbler 带鼓泡槽buffered oxide etch(BOE) 氧化层腐蚀缓冲液bulk chemical distribution 批量化学材料配送bulk gases 大批气体bulkhead equipment layout 穿壁式设备布局bumped chip 凸点式芯片buried layer 埋层burn-box 燃烧室(或盒) burn-in 老化CCA 化学放大(胶) cantilever n. 建］悬臂cantilever paddle 悬臂桨cap oxide 掩蔽氧化层capacitance 电容capacitance-voltage test(C-Vtest) 电容-电压测试capacitive coupled plasma 电容偶合等离子体capacitor 电容器carbon tetrafluoride(CF4) 四氟化碳caro ' s acid3 号液carrier 载流子carrier-depletion region 载流子耗尽层carrier gas 携带气体cassette (承)片架cation 阳离子caustic 腐蚀性的cavitation 超声波能CD 关键尺寸CD- SEM 线宽扫描电镜Celsius adj.摄氏的center of focus(COF) 焦点焦平面center slow 中心慢速central processing unit(CPU) 中央处理器ceramic substrate 陶瓷圭寸装CERDIP 陶瓷双列直插封装Channel 沟道channel length 沟道长度channeling 沟道效应charge carrier 载流子chase技术夹层chelating agent 螯合齐ijchemical amplification(CA) 化学放大胶chemical etch mechanism 化学刻蚀机理chemical mechanical planarization(CMP) 化学机械平坦化chemical solution 化学溶液chemical vapor deposition(CVD) 化学气相淀积chip 芯片chip on board(COB)板上芯片chip scale package(CSP)芯片尺寸圭寸装circuit geometries 电路几何尺寸class number 净化级另卩cleanroom 净化间cleanroom protocol 净化间操作规程Clearfield mask 亮场掩膜板Cluster tool 多腔集成设备CMOS 互补金属氧化物半导体CMP 化学机械平坦化Coater/developer track 涂胶/显影轨道Cobalt silicide 钻硅化合物coefficient n. ［数］系数Coefficient of thermal expansion（CTE）热涨系数Coherence probe microscope 相干探测显微镜Coherent light 相干光coil v. 盘绕，卷Cold wall 冷壁Collector 集电极Collimated light 平行光Collimated sputtering 准直溅射Compensate v.偿还，补偿，付报酬Compound semiconductor 化合物半导体Concentration 浓度Condensation 浓缩Conductor 导体constantly adv・不变地，经常地，坚持不懈地Confocal microscope 共聚焦显微镜Conformal step coverage 共型台阶覆盖Contact 接触（孔）Contact alignment 接触式对准（光刻）Contact angle meter 接触角度仪Contamination 沾污、污染conti boat 连柱舟conticaster ［冶］连铸机Continuous spray develop 连续喷雾显影Contour maps 包络图、等位图、等值图Contrast 对比度、反差contribution n.捐献，贡献，投稿Conventional-line photoresist 常规I 线光刻胶Cook' s theory库克理论Copper CVD 铜CVD Copper interconnect 铜互连Cost of ownership(COO) 业主总成本Covalent bond 共价键Critical dimension 关键尺寸Cryogenic aerosol cleaning 冷凝浮质清洗Cryogenic pump(cryopump) 冷凝泵Crystal 晶体Crystal activation 晶体激活Crystal defect 晶体缺陷Crystal growth 晶体生长Crystal lattice 晶格Crystal orientation 晶向CTE 热涨系数Current-driven current amplifier 电流驱动电流放大器CVD 化学气相淀积Cycle time 周期CZ crystal puller CZ 拉单晶设备Czochralski(CZ) method 切克劳斯基法Ddamascene 大马士革工艺darkfiled detection 暗场检测darkfiled mask 暗场掩膜版DC bias 直流偏压decompose v. 分解,(使)腐烂deep UV(DUV) 深紫外光default n.默认(值)，缺省(值),食言，不履行责任，［律］缺席v.疏怠职责，缺席，拖欠，默认defects density 缺陷密度defect 缺陷deglaze 漂氧化层degree of planarity(DP) 平整度dehydration bake 去湿烘培，脱水烘培density 密度deplention mode 耗尽型degree of focus 焦深deposit n.堆积物，沉淀物，存款，押金，保证金，存放物vt ・存放,堆积vi.沉淀deposition 淀积deposited oxide layer 淀积氧化层depth of focus 焦深descum 扫底膜design for test(DFT)可测试设计desorption 解吸附作用develop inspect 显影检查development 显影developer 显影液deviation n.背离device isolation 器件隔离device technology 器件工艺DI water 去离子水Diameter n.直径diameter grinding 磨边diborane ( B2H6 )乙硼烷dichlorosilane(H2SiCL2) 二氯甲硅烷die 芯片die array 芯片阵列die attach 粘片die-by-die alignment 逐个芯片对准dielectric 介质dielectric constant 介电常数die matrix 芯片阵列die separation 分片diffraction 衍射diffraction-limited optics 限制衍射镜片diffusion 扩散diffusion controlled 受控扩散digital/analog数字/模拟digital circuit diluent direct chip attach( DCA) directionality discrete dishing dislocation dissolution ratedissolution rate monitor(DRM) 溶解率监测DNQ-novolak 重氮柰醌一酚醛树脂Donor 施主dopant profile 掺杂刨面) doped虚拟的， region 掺杂区 doping 掺杂 dose monitor剂量检测仪 dose,Q 剂量 downstream reactor 顺流法反应 drain 漏 drive-in推进 dry etch 干法刻蚀 dry mechanical pump干式机械泵 dry oxidation 干法氧化dummy n.哑巴，傀儡，假人，假货 adj. 假的，虚构的 n.［计］哑元 dynamic adj. 动力的，动力学的，动态的 E economies of scale 规模经济 edge bead removal 边缘去胶 edge die 边缘芯片edge exclusion 无效边缘区域 electrically erasable PROM 电可擦除 EPROM electrode 电极 electromigration 电迁徙 electron beam lithography 电子束光刻electron cyclotron resonance 电子共振回旋加速器 electron shower 电子簇射，电子喷淋 electron stopping 电子阻止 electronic wafer map 硅片上电性能分布图 electroplating 电镀 electropolishing 电解拋光electrostatic chuck 静电吸盘 electrostatic discharge(ESD)静电放电 ellipsometry 椭圆偏振仪，椭偏仪emitter 发射极 endpoint detection 终点检测 engineering n.工程(学) electrostatic discharge(EDX)能量弥散谱仪 enhancement mode 增强型 epi 夕卜延epitaxial layer 夕卜延层epoxy underfill 环氧树脂填充不足erasable PROM 可擦除可编程只读存储器erosion腐蚀，浸蚀establish vt・建立，设立，安置，使定居，使人民接受，确定v.建立etch 刻蚀etch bias刻蚀涨缩量etch profile 刻蚀刨面etch rate 刻蚀速率etch residue 刻蚀残渣etch uniformity 刻蚀均匀性etchant 刻蚀剂etchback planarization 返刻平坦化eutectic attach 共晶焊接eutectic temperature 共晶温度evaporation 蒸发even adj.平的，平滑的，偶数的，一致的，平静的，恰好的，平均的，连贯的adv.［加强语气］甚至（・・・也）, 连…都，即使，恰好，正当vt.使平坦，使相等vi. 变平，相等n.偶数，偶校验exceed vt. 超越，胜过vi.超过其他excimer laser 准分之激光exposal n. 曝光,显露exposure 曝光exposure dose 曝光量extraction electrode 吸极extreme UV 极紫外线extrinsic silicon 掺杂硅F Fables无制造厂公司fabrication 制造facilities 设施factor n.因素，要素，因数，代理人fast ramp furnaces 快速升降温炉fault model 失效模式FCC diamond 面心立方金刚石feature size 特征尺寸FEOL 前工序Fick ' s lawsFICK 定律field-effect transistor 场效应晶体管field oxide 场氧化field-by-field alignment 逐场对准field-programmable PROM 现场可编程只读存储器film 膜film stress 膜应力final assembly and packaging 最终装配和圭寸装final test 终测first interlayer dielectric(ILD-1)第一层层间介质fixed oxide charge 固定氧化物电荷flats 定位边flip chip 倒装芯片float zone 区熔法fluorosilicate glass(FSG) 氟化玻璃focal length 焦距focal plane 焦平面focal point 焦点focus聚焦focus ion beam(FIB) 聚焦离子束footprint 占地面积formula n.公式，规则，客套语forward bias 正偏压four-point probe 四探针frenkel defect Frenkel 缺陷front-opening unified pod(FOUP)前开口盒functional test 功能测试furnace flat zone 恒温区G g-line G 线gallium(Ga)镓gallium arsenide(GaAs)砷化镓gap fill间隙填充gas 气体gas cabinet 气柜gas manifold 气瓶集装gas phase nucleation 气相成核gas purge 气体冲洗gas throughput 气体产量gate 栅gate oxide 栅氧化硅gate oxide integrity 栅氧完整性germanium(Ge) 错getter 俘获glass玻璃glazing 光滑表面global alignment 全局对准global planarization 全局平坦化glow discharge 起辉放电gray area 灰区，技术夹层gross defect 层错grove n. 小树林grown oxide layer 热氧化生长氧化层HHalogen 卤素hardbake 坚膜hardware n.五金器具，(电脑的)硬件，(电子仪器的)部件HEPA filter 高效过滤器hermetic sealing 密圭寸heteroepitaxy 异质外延heterogeneous reaction 异质反应hexamethyldisilazane(HMDS)六甲基二硅氨烷high-density plasma(HDPCVD) 高密度等离子体化学气相淀积高温扩散炉 high-density plasma etch 高密度等离子刻蚀 high-pressure oxidation 高压氧化high-temperature diffusion furnace high vacuum 高真空 high vacuum pumps 高真空泵 hillock 小丘(铝)尖刺 homoepitaxy 同质外延 homogeneous reaction 同质反应 horizontal adj.地平线的，水平的 horizontal furnace 臣卜式炉 hot electron 热电子 hot wall 热壁 hydrochloric acid(HCL)盐酸 hydrofluoric acid(HF)氢氟酸 hydrogen(H2)氢气 hydrogen chloride(HCL)氯化氢 hydrogen peroxide(H2O2)双氧水 hydeophilic 亲水性 hydrophobic 憎水性，疏水性 hyperfiltration 超过滤Ii-line I 线IC packaging 集成电路封装IC reliability 集成电路可靠性 Iddq testing 静态漏电流测试 image resolution 图象清晰度 图象分解力implant v.灌输（注入） impurity 杂质 increment n.增力口,增量 initial adj.最初的，词首的，初始的 n.词首大写 字母 in situ measurements 在线测量 index of refraction 折射率 indium 铟 inductively coupled plasma （ICP ）电感耦合等离子体 inert gas惰性气体infrared interference 红外干涉ingot 锭ink mark墨水标识in-line parametric test 在线参数测试input/output（I/O）pin 输入/ 输出管脚institute n. 学会，学院，协会vt.创立，开始，制定，开始（调查）,提起（诉讼） insulator 绝缘体integrate vt.使成整体，使一体化，求…的积分v.结合integrated circuit(IC)集成电路integrated measurement tool 集成电路测量仪interval n.间隔，距离，幕间休息n.时间间隔interconnect 互连interconnect delay 互连连线延迟interface-trapped charge 界面陷阱电荷interferometer 干涉仪interlayer dielectric(ILD) 层间介质interstitial 间隙(原子) intrinsic silicon 本征硅invoke v.调用ion 离子ion analyzer 离子分析仪ion beam milling or ion beam etching(IBE) 离子铣或离子束刻蚀ion implantation 离子注入ion implantation damage 离子注入损伤ion implantation doping 离子注入掺杂ion implanter离子注入机ion projection lithography(IPL) 离子投影机PVD ionization 离子化ionized metal plasma PVD 离子化金属等离子IPA vapor dry 异丙醇气相干燥isolation regions 隔离区isotropic etch profile各向同性刻蚀刨面JJEFT结型场效应管junction(pn) PN 结junction depth 结深junction spiking 结尖刺KKelvin绝对温度killer defect致命缺陷kinetically controlled reaction 功能控制效应L laminar air flow 层状空气流，层流式lapping 拋光latchup闩锁效应lateral diffusion 横向扩散law of reflection 反射定律LDD轻掺杂漏Leadframe 引线框架leakage cuttent 漏电流len透镜lens compaction 透镜收缩light 光light intensity 光强light scattering 光散射lightly doped drain(LDD) 轻掺杂漏linear 线性linear accelerator 线性加速器linear stage 线宽阶段，线性区linewidth 线宽liquid 液体lithography 光刻loaded brush沾污的毛刷loaded effect 负载效应loadlock真空锁local interconnect(LI)局部互连local planarization 局部平坦化local oxidation of silicon(LOCOS)硅局部氧化隔离法logic逻辑lot批low-pressure chemical vapor deposition (LPCVD) 低压化学气相淀积LSI大规模集成电路Mmagnetic CZ( MCZ )磁性切克劳斯基晶体生长法magnetically enhanced RIE(MERIE)磁增强反应离子刻蚀magnetron sputtering 磁控溅射Magnification n. 扩大，放大倍率magnificent adj. 华丽的，高尚的，宏伟的majority carrier 多子make-up loop补偿循环mask掩膜版n.面具，掩饰，石膏面像vt.戴面具,掩饰，使模糊vi.化装，戴面具，掩饰，参加化装舞会mask-programmable gate array 掩膜可编程门阵歹Umass flow controller(MFC) 质量流量计mass spectrometer 质谱仪mass-transport limited reaction 质量传输限制效应mathematical adj.数学的，精确的mean free path(MFP) 平均自由程medium vacuum 中真空adj. megasonic cleaning 超声清洗melt熔融membrane contactor薄膜接触器，隔膜接触器membrane filter薄膜过滤器，隔膜过滤器merchant n. 商人，批发商，贸易商，店主商业的，商人的mercury arc lamp 汞灯MESFET用在砷化镓结型场效应晶体管中的金属栅metal contact 金属接触孔metal impurities 金属杂质metal stack复合金属，金属堆叠metallization 金属化metalorganic CVD金属有机化学气相淀积metrology 度量衡学microchip微芯片microdefect 微缺陷microlithography 微光刻microloading微负载，与刻蚀相关的深宽比micron微米microprocessor n.［计］微处理器microprocessor unit 微处理器microroughness 微粗糙度Miller indices 密勒指数minienvironment 微环境minimum geometry 最小尺寸minority carrier 少子mix and match 混合与匹配mobile ionic contaminants(MIC)可动离子沾污mobile oxide charge 可动氧化层电荷module n.模数，模块,登月舱，指令舱modify vt・更改，修改v.修改molecular beam epitaxy (MBE) 分子束外延molecular flow 分子流monitor wafer(test wafer) 陪片，测试片，样片monocrystal 单晶monolithic device 单片器件Moore's law 摩尔定律MOS 金属氧化物半导体MOSFET 金属氧化物半导体场效应管motor curreant endpoint 电机电流终点检测(法) MSI中规模集成电路Multiplier n.增加者，繁殖者,乘数，增效器，乘法器multichip module(MCM) 多芯片模式multilenel metallization 多重金属化Murphy's model 墨菲模型N nanometer(nm)纳米native oxide 自然氧化层n-channel MOSFET n 沟道MOSFET negatine resist 负性光刻胶negative n.否定，负数，底片adj.否定的，消极的，负的，阴性的vt.否定，拒绝(接受) negatine resist development 负性光刻胶显影neutral beam trap 中性束陷阱next-generation lithography 下一代光刻技术nitric acid(HNO3)硝酸nitrogen(N2)氮气nitrogen trifluoride(NF3) 三氟化氮nitrous oxide (N2O) 一氧化二氮、笑气nMOS n沟道MOS场效应晶体管noncritical layer 非关键层nonvolatile memory 非挥发性存储器normality 归一化notch 定位槽novolak苯酚甲醛聚树脂材料npn npn 型(三极管) n-type silicon n 型硅nuclear stopping 离子终止nucleation 成核现象，晶核形成nuclei coalescence 核合并numericalaperture(NA) 数值孑L径n-well n 阱Oobjective (显微镜的)物镜off-axis illumination(OAI) 偏轴式曝光，离轴式曝光ohmic contact 欧姆接触op amp 运算放大器optical interferometry endpoint 光学干涉法终点检测optical lithography 光学光刻optical microscope(light microscope) 光学显微镜optical proximity correction(OPC)光学临近修正optical pyrometer 光学高温计optics 光学organic compound 有机化合物氧化诱生层积 vi.划桨，戏 out-diffusion 反扩散 outgassing 除气作用 overdrive 过压力 overetch step 过刻蚀 overflow rinser 溢流清洗 overlay accuracy 套准精度 overlay budget 套准偏差 overlay registration 套刻对准 oxidation 氧化 oxidation-induced stacking faults(OISF) 缺陷，氧化诱生堆垛层错 oxide 氧化物、氧化层、氧化膜 oxidezer 氧化齐ij oxide-trapped charge 氧化层陷阱电荷 ozone(O3)臭氧Ppackage 封装管壳 pad conditioning 垫修整 pad oxide 垫氧化膜 paddle 悬臂 n.短桨，划桨，明轮翼 水，涉水 vt ・用桨划，搅，拌parabolic stage 拋物线阶段parallel-plate(planar)reactor 平板反应parallel testing 并行测试 parameter 参数parametric test 参数测试 parasitic 寄生parasitic capacitance 寄生电容 parasiticresistance 寄生电阻 parasitic transistor 寄生电阻器 partial pressure 分压 particledensity 颗粒密度 particle per wafer perpass(PWP)每步每片上的颗粒 数passivation 钝化 passivation layer 钝化层passive components 无源元件pattern sensitivity 图形灵敏性patterned etching 图形刻蚀pattern wafer 带图形硅片patterning 图形转移，图形成型，刻印pc board 印刷电路版完成任务 p-channel MOSFETp 沟道 MOSFET PCM 工艺控制监测 PEB 曝光后烘焙 PECVD 等离子体增强化学气相淀积PEL 允许曝露极限值pellicle 贴膜 pentavalent 五价元素 perform vt ・ 履行,执行，表演，演出 v. performing adj. 表演的，履行的 perimete array 周边阵列式(圭寸装) pH scale pH 值 phase-shift mask(PSM) 相移掩膜技术 phosphine(PH3) 磷化氢 phosphoric acid(H3PO4)磷酸 phosphorus(P)磷 phosphorus oxychloride(POCL3)三氯氧磷 phosphosilicate glass(PSG)磷硅玻璃 photoacid generator(PAG)光酸产生剂 photoacoustics 光声的 photoactive compound(PAC)感光化合物 photography n.摄影，摄影术 光刻photolithography 光刻(技术) photomask 光掩膜 photoresist 光刻胶 photoresist stripping 去胶、光刻胶去除 physical etch mechanism 物理刻蚀机理 physical vapor deposition(PVD)物理气相淀积 pigtail 引出头 pin grid array(PGA) 针栅阵列式(封装)pinhole 针孑 L piranha 3 号液 pitch 间距 planar 平面 planar capacitor 平面电容 planar process 平面工艺 planarization 平坦化 plasma 等离子体 n.［解］血浆，乳浆，［物］等离子体，plasma-induced damage 等离子体诱导损伤plasma potential distribution 等离子体势分布plastic dual in-line package(DIP) 双列直插塑料圭寸装plastic leaded chip carrier(PLCC) 塑料电极芯片载体plastic packaging 塑料圭寸装plug塞，填充vt.堵，塞，插上，插栓n塞子，插头, 插销pMOS(p-channel) p 沟道MOSpn junction diode pn 结型二极管pnp pnp型三极管point defect 点缺陷Poisson's model 泊松模型polarization 极化，偏振polarized light 极化光，偏振光polish拋光polish rate 拋光速率polished wafer edge(edge grind) 倒角polishing loop 磨拋循环polishing pad 拋光(衬)垫polycide 多晶硅化物光刻胶显影post-develop inspection 显影后检查post-exposure bake(PEB) 曝光后烘焙ppb 十亿分之几ppm 百万分之几ppt 万亿分之几preamorphization 预非晶化precursor 先驱物predeposition 预淀积premetaldielectric(PMD) 金属前介质preston equation Preston 方程primary orientation flat 主定位边print bias光刻涨缩量printed circuit boade(PCB) 印刷电路板probe探针probe card 探针卡prober探针台process 工艺process chamber工艺腔，工艺反应室process chemical 工艺化学process control monitor(PCM)工艺控制监测(图形) process latitude工艺水平，工艺能力process recipe 工艺菜单programmable arraylogic(PLA) 可编程阵列逻辑programmable logic device 可编程逻辑器件programmable read-only memory 可编程只读存储器projected range 投影射程prompt n.提示，付款期限vt・提示，鼓动，促使, (给演员)提白adj.敏捷的，迅速的，即时的adv.准时地n. DOS命令：改变DOS系统提示符的风格proportion n.比例，均衡，面积，部分vt.使成比例，使均衡，分摊proportional adj. 比例的，成比例的，相称的，均衡的proportional band 比例区，比例带，比例尺范围proximityaligner 接近式光刻机p-type silicon P 型硅puddle develop搅拌式显影pump speed 抽气速率punchthrough 穿通purge （冲气）清洗purge cycle （冲气抽气）清洗循环PVD物理气相淀积p-well P 阱pyrogenic steam 热流pyrogen 热原（质）pyrolytic 热解pyrophoric 自燃的Qquad flatpack（QFP）方型管壳封装quadrupole mass analyzer （QMA）四极质量分析仪quality measure 质量测量quarz石英quarz tube 石英管quarz wafer boat 石英舟queue time排队时间R radiation damage 辐射损伤radical 激发random access memory(RAM) 随机存储器range射程rapid thremal anneal(RTA) 快速热退火rapid thermal processor(RTP)快速热处理RCA clean RCA 清洗reaction rate limited 反应速率限制reactive ion etch(RIE)反应离子刻蚀reactivity 反应性reactor反应室，反应腔read-only memory(ROM)只读存储器recombination 复合redistribution 再分布reflection spectroscopy 反射光谱仪reflective notching 反射开槽reflow回流refraction 折身寸refractory metal 难融金属regeneration 再生regeneration套准精度relative index of refraction,n removal n. 移动，免职,切除repeat n.重复，反复vt・重做，复述，向他人转述，复制，使再现vi.重复，留有味道representation n. 表示法,表现,陈述,请求，扮演，画像，继承，代表reset v.重新安排residual gas analyzer(RGA)残余气体分析器resist光刻胶resist development 光刻胶显影resistance 电阻resistivity 电阻率resolution 分辨率reticle掩膜版retrograde well 倒掺杂阱reverse bias 反偏reverse osmosis(RO)反向渗透RF射频RF sputtering射频溅射rinse v嗽口，(用清水)刷，冲洗掉，漂净n.清洗嗽洗，漂洗，漂清，冲洗RO反向渗透Roots blower罗茨(机械增压)泵roughing pump 低真空泵，机械泵RTA快速热退火RTP快速热处理Ssatisfy vt.满足，使满意，说服，使相信v.满意，确保Scaling按比例缩小SCALPEL具有角度限制分散投影电子束光刻Scanner扫描仪scanning electron microscope(SEM)扫描电子显微镜scanning projection aligner 扫描投影光刻机schottky diode 肖特基二极管screen oxide layer 掩蔽氧化层scribe line 戈H 片道scribe line monitor(SLM)戈J片线监测scumming 底膜secondary electron 二次电子secondary electron flood 二次电子流secondary ion mass spectrometry(SIMS)二次离子质谱 (法) seed' s model SEE 模型selective etching 选择性刻蚀selective oxidation 选择性氧化selectivity 选择性semiconductor grade silicon 半导体极硅semiconductor 半导体sensitivity 灵敏度shallow trench isolation(STI)浅沟槽隔离sheet resistance,RS 方块电阻sheet resistivity,方块电阻率shot size胶(点)尺寸shrinking 缩小SI units 公制Sidewall spacer 侧墙Silane(siH4)硅烷Silicide硅化合物silicon 硅silicon dioxide(SIO2)二氧化硅silicon nitride(SI3N4)氮化硅silicon on sapphire 蓝宝石伤硅silicon on insulator(SOI)绝缘体上硅silicontetrachloride(SIC4) 碳化硅silicon tetrafluoride(SIF4)四氟化硅silicon tetrachloride(SICL4)四氯化硅single crystal silicon 单晶硅silylation硅烷化(作用)SIMOX 由注入氧隔离，一种SOI材料single crystal 单晶slip滑移slurry磨料SMIF标准机械接口Sodium hydroxide(NaOH)氢氧化钠soft bake 前烘solid固体solvent 溶齐ijSOS蓝宝石上硅Source 源source drain implants 源漏注入spacer n.取间隔的装置，逆电流器spatial coherence 空间相干spatial signature analysis 空间信号分析specialty gase 特种气体species 种类specific gravity 比重specific heat 比热speckle 斑点spectroscipic ellipsometry 椭圆偏振仪spin coating光刻胶旋涂spin dryer 旋转式甩干桶spin-on-dielectric（SOD）旋转介质法spin-on-glass（SOG）旋转玻璃法spray cleaning 喷雾清洗spray rinser喷雾清洗槽spreading resistance probe 扩散电阻探测sputter n・喷溅声，劈啪声，急语，咕哝vi.唾沫飞溅，发劈啪声，急忙地讲vt.喷出，飞溅出，气急败坏地说sputtering 溅射sputter etch溅射刻蚀sputtered aluminum 溅射铝sputtering yield 溅射产额SSI小规模集成电路stacking fault层积缺陷，堆垛层错standard clean 1(SC-1) 1 号清洗液standard clean 2(SC-2) 2 号清洗液standard mechanical interface(SMIF)机械标准接口standing wave 驻波static RAM静态存储器statistical process control ( SPC)统计过程控制step coverage台阶覆盖step height台阶高度step-and-repeat aligner 分步重复光刻机step-and-scan system步进扫描光刻机stepper步进光刻机stepping motor driver步进电机驱动器电路stepper步进光刻机stoichiometry化学计量(配比) staggle投射标准偏差stress应力striation 条纹strip vt・剥，剥去n. 条，带stripping 去胶structure 结构subatmospheric CVD亚大气压化学气相淀积submicron 亚微米sub-quarter micron 亚0・25微米substrate 衬底sublimation 升华substitutional atom 替位原子subtract v (〜from)减去,减subwaverlength lithography 亚波长光刻sulfur hexafluoride(SF6)六氟化硫sulfuric acid (H2SO4 )硫酸surface profiler 表面形貌surface tension 表面张力susceptor 基座Ttarget chamber 靶室target 靶temperature ramp rate 温度斜率temperature 温度TEOS正硅酸乙脂test algorithm 测试算法test coverage 测试覆盖test structure 测试结构test vector测试向量thermal budget 热预算thermal oxide 热氧化thermocompression bonding 热压键合thermocouple 热电偶thermogravimetric analysis (TGA) 热重量分析thermosonic bonding 热超声键合thin film 薄膜thin small outline package(TSOP)薄小型圭寸装川-V compound 三/五族化合物thorough adj.十分的，彻底的Threshold 域值threshold voitage 域值电压threshold voltage adjustment implant 调栅注入，域值调整注入throughput 产量tilt [tilt] v.(使)倾斜，(使)翘起，以言词或文字抨击time of flight SIMS(TOF -SIMS) 飞行时间二次离子质谱titanium silicide 钛硅化合物TLV极限域值top surface imaging 上表面图形topography 形貌torr 托toxic有毒track system(also track) 轨道系统transient enhanced diffusion(TED)瞬时增强扩散transistor 晶体管trench 槽trench capacitor 槽电容trichlorosilane(TCS or SiHCL3)三氯氢硅triode planar reactor三真空管平面反应室triple well 三阱trivalent 三价tungsten(W)钨tungsten stch back 钨反刻tungsten hexafluoride(WF6)六氟化钨tungstenplug钨塞，钨填充turbomolecular pump(turbo pump) 涡轮分子泵twin planes(twinning) 双平面twin-well(twin-tub)双阱UULSI甚大规模集成电路ultralow penetration air(ULPA)超低穿透空气ultrafiltration 超过滤ultrafine particle 超细颗粒ultrahigh purity 超高纯度ultrahigh vacuum 超高真空ultrashallow junction 超浅结ultrashallow junction 超声键合(压焊) ultraviolet 紫外线undercut 钻蚀uniformity 均匀性unit cell元包，晶胞unpatterned etching(spripping)无图形刻蚀(剥离) unpatterned wafer 无图形硅片unplug v.拔去(塞子，插头等),去掉…的障碍物UV紫外线VVacancy 空位vacuum 真空vacuum wand真空吸片棒，真空镊子van der pauw method 范德堡法vapor phase epotaxy(VPE)气相外延vapor pressure 气压vapor prime气相熏增粘剂，气相成底膜vaporization 气化variable n.［数］变数，可变物，变量adj. 可变的，不定的，。

晶圆（Wafer）制程工藝學習之迟辟智美创作晶圆（Wafer）的生产由砂即（二氧化硅）开始，经由电弧炉的提炼还原成冶炼级的硅，再经由盐酸氯化，发生三氯化硅，经蒸馏纯化后，透过慢速分解过程，制成棒状或粒状的「多晶硅」.一般晶圆制造厂，将多晶硅融解后，再利用硅晶种慢慢拉出单晶硅晶棒.一支85公分长，重76.6公斤的8吋硅晶棒，约需2天半时间长成.经研磨、拋光、切片后，即成半导体之原料晶圆片.光学显影光学显影是在光阻上经过曝光和显影的法式，把光罩上的图形转换到光阻下面的薄膜层或硅晶上.光学显影主要包括了光阻涂布、烘烤、光罩瞄准、曝光和显影等法式.小尺寸之显像分辨率，更在 IC 制程的进步上，饰演着最关键的角色.由于光学上的需要，此段制程之照明采纳偏黄色的可见光.因此俗称此区为黄光区.干式蚀刻技术在半导体的制程中，蚀刻被用来将某种材质自晶圆概况上移除.干式蚀刻（又称为电浆蚀刻）是目前最经常使用的蚀刻方式，其以气体作为主要的蚀刻媒介，并藉由电浆能量来驱动反应.电浆对蚀刻制程有物理性与化学性两方面的影响.首先，电浆会将蚀刻气体分子分解，发生能够快速蚀去资料的高活性分子.另外，电浆也会把这些化学成分离子化，使其带有电荷.晶圆系置于带负电的阴极之上，因此当带正电荷的离子被阴极吸引并加速向阴极方向前进时，会以垂直角度撞击到晶圆概况.芯片制造商即是运用此特性来获得绝佳的垂直蚀刻，而后者也是干式蚀刻的重要角色.基本上，随着所欲去除的材质与所使用的蚀刻化学物质之分歧，蚀刻由下列两种模式独自或混会进行：1. 电浆内部所发生的活性反应离子与自由基在撞击晶圆概况后，将与某特定成分之概况材质起化学反应而使之气化.如此即可将概况材质移出晶圆概况，并透过抽气举措将其排出.2. 电浆离子可因加速而具有足够的动能来扯断薄膜的化学键，进而将晶圆概况材质分子一个个的冲击或溅击（sputtering）出来.化学气相堆积技术化学气相堆积是制造微电子组件时，被用来堆积出某种薄膜(film)的技术，所堆积出的薄膜可能是介电资料(绝缘体)(dielectrics)、导体、或半导体.在进行化学气相堆积制程时，包括有被堆积资料之原子的气体，会被导入受到严密控制的制程反应室内.当这些原子在受热的昌圆概况上起化学反应时，会在晶圆概况发生一层固态薄膜.而此一化学反应通常必需使用单一或多种能量源(例如热能或无线电频率功率).CVD制程发生的薄膜厚度从低于0.5微米到数微米都有，不外最重要的是其厚度都必需足够均匀.较为罕见的CVD薄膜包括有：■二气化硅（通常直接称为氧化层）■ 氮化硅■ 多晶硅■耐火金属与这类金属之其硅化物可作为半导体组件绝缘体的二氧化硅薄膜与电浆氮化物介电层（plasmas nitride dielectrics）是目前CVD技术最广泛的应用.这类薄膜资料可以在芯片内部构成三种主要的介质薄膜：内层介电层（ILD）、内金属介电层（IMD）、以及呵护层.另外、金层化学气相堆积（包括钨、铝、氮化钛、以及其它金属等）也是一种热门的CVD应用.物理气相堆积技术如其名称所示，物理气相堆积（Physical Vapor Deposition）主要是一种物理制程而非化学制程.此技术一般使用氩等钝气，藉由在高真空中将氩离子加速以撞击溅镀靶材后，可将靶材原子一个个溅击出来，并使被溅击出来的材质（通常为铝、钛或其合金）如雪片般堆积在晶圆概况.制程反应室内部的高温与高真空环境，可使这些金属原子结成晶粒，再透过微影图案化（patterned）与蚀刻，来获得半导体组件所要的导电电路.解离金属电浆（IMP）物理气相堆积技术解离金属电浆是最近发展出来的物理气相堆积技术，它是在目标区与晶圆之间，利用电浆，针对从目标区溅击出来的金属原子，在其达到晶圆之前，加以离子化.离子化这些金属原子的目的是，让这些原子带有电价，进而使其行进方向受到控制，让这些原子得以垂直的方向往晶圆行进，就像电浆蚀刻及化学气相堆积制程.这样做可以让这些金属原子针对极窄、极深的结构进行沟填，以形成极均匀的表层，尤其是在最底层的部份.高温制程多晶硅（poly）通经常使用来形容半导体晶体管之部份结构：至于在某些半导体组件上罕见的磊晶硅（epi）则是长在均匀的晶圆结晶概况上的一层纯硅结晶.多晶硅与磊晶硅两种薄膜的应用状况虽然分歧，却都是在类似的制程反应室中经高温（600℃至1200℃）堆积而得.即使快速高温制程（Rapid Thermal Processing, RTP）之工作温度范围与多晶硅及磊晶硅制程有部份重叠，其实质不同却极年夜.RTP其实不用来沈积薄膜，而是用来修正薄膜性质与制程结果.RTP将使晶圆历经极为长久且精确控制高温处置过程，这个过程使晶圆温度在短短的10至20秒内可自室温升到1000℃.RTP通经常使用于回火制程（annealing），负责控制组件内掺质原子之均匀度.另外RTP也可用来硅化金属，及透过高温来发生含硅化之化合物与硅化钛等.最新的发展包括，使用快速高温制程设备在晶极重要的区域上，精确地堆积氧及氮薄膜.离子植入技术离子植入技术可将掺质以离子型态植入半导体组件的特定区域上，以获得精确的电子特性.这些离子必需先被加速至具有足够能量与速度，以穿透（植入）薄膜，达到预定的植入深度.离子植入制程可对植入区内的掺质浓度加以精密控制.基本上，此掺质浓度（剂量）系由离子束电流（离子束内之总离子数）与扫瞄率（晶圆通过离子束之次数）来控制，而离子植入之深度则由离子束能量之年夜小来决定.化学机械研磨技术化学机械研磨技术（Chemical Mechanical Polishing, CMP）兼其有研磨性物质的机械式研磨与酸碱溶液的化学式研磨两种作用，可以使晶圆概况达到全面性的平坦化，以利后续薄膜堆积之进行.在CMP制程的硬设备中，研磨头被用来将晶圆压在研磨垫上并带动晶圆旋转，至于研磨垫则以相反的方向旋转.在进行研磨时，由研磨颗粒所构成的研浆会被置于晶圆与研磨垫间.影响CMP制程的变量包括有：研磨头所施的压力与晶圆的平坦度、晶圆与研磨垫的旋转速度、研浆与研磨颗粒的化学成分、温度、以及研磨垫的材质与磨损性等等.制程监控在下个制程阶段中，半导体商用CD-SEM来量测芯片内次微米电路之微距，以确保制程之正确性.一般而言，只有在微影图案（photolithographic patterning）与后续之蚀刻制程执行后，才会进行微距的量测.光罩检测（Retical Inspection）光罩是高精密度的石英平板，是用来制作晶圆上电子电路图像，以利集成电路的制作.光罩必需是完美无缺，才华出现完整的电路图像，否则不完整的图像会被复制到晶圆上.光罩检测机台则是结合影像扫描技术与先进的影像处置技术，捕捉图像上的缺失.当晶圆从一个制程往下个制程进行时，图案晶圆检测系统可用来检测出晶圆上是否有瑕疵包括有微尘粒子、断线、短路、以及其它各式各样的问题.另外，对已印有电路图案的图案晶圆制品而言，则需要进行深次微米范围之瑕疵检测.一般来说，图案晶圆检测系统系以白光或雷射光来照射晶圆概况.再由一或多组侦测器接收自晶圆概况绕射出来的光线，并将该影像交由高功能软件进行底层图案消除，以辨识并发现瑕疵.切割晶圆经过所有的制程处置及测试后，切割成壹颗颗的IC.举例来说：以0.2 微米制程技术生产，每片八吋晶圆上可制作近六百颗以上的64M DRAM.封装制程处置的最后一道手续，通常还包括了打线的过程.以金线连接芯片与导线架的线路，再封装绝缘的塑料或陶瓷外壳，并测试IC功能是否正常.由于切割与封装所需技术层面比力不高，因此常成为一般业者用以介入半导体工业之切入点.300mm为协助晶圆制造厂克服300mm晶圆生产的挑战，应用资料提供了业界最完整的解决方案.不单拥有种类齐全的300mm 晶圆制造系统，提供最好的服务与支持组织，还掌握先进制程与制程整合的技术经验；从降低风险、增加成效，加速量产时程，到协助告竣最年夜生产力，将营运本钱减到最高等，以满足晶圆制造厂所有的需求.应用资料的300mm 全方位解决方案，完整的产物线为：高温处置及离子植入设备(Thermal Processes and Implant)介质化学气相堆积(DCVD：Dielectric Chemical Vapor Deposition)金属堆积(Metal Deposition)蚀刻(Etch)化学机械研磨(CMP：Chemical Mechanical Polishing)检视与量测(Inspection & Metrology)制造执行系统(MES：Manufacturing Execution System)服务与支持(Service & Support)铜制程技术在传统铝金属导线无法突破瓶颈之情况下，经过多年的研究发展，铜导线已经开始成为半导体资料的主流，由于铜的电阻值比铝还小，因此可在较小的面积上承载较年夜的电流，让厂商得以生产速度更快、电路更密集，且效能可提升约30-40％的芯片.亦由于铜的抗电子迁移（electro-migration）能力比铝好，因此可减轻其电移作用，提高芯片的可靠度.在半导体制程设备供货商中，只有应用资料公司能提供完整的铜制程全方位解决方案与技术，包括薄膜堆积、蚀刻、电化学电镀及化学机械研磨等.应用资料公司的铜制程全方位解决方案在半导体组件中制造铜导线，牵涉不单是铜的堆积，还需要一系列完整的制程步伐，并加以仔细规划，以便发挥最年夜的效能.应用资料公司为发展铜制程相关技术，已与重要客户合作多年，具有丰富的经验；另外在半导体制程设备所有供货商中，也只有应用资料公司能够提供铜导线结构的完整制程技术，包括薄膜堆积、蚀刻、电化学电镀及化学机械研磨等.。