Si823x

含氢硅油中活性氢的测定贾建国　陈明九　王广瑞(南京金陵石化德赛化工技术有限公司,南京210038) 摘要:以苯为内标物,采用核磁共振(1H NMR )法,根据可测试的氢质子峰的积分面积,计算出含氢硅油中活性氢的质量分数。

该方法所需样品量为60～80mg ,分析时间为15min ,具有简单、省时、准确等特点。

关键词:核磁共振,含氢硅油,活性氢收稿日期:2002-05-08。

作者简介:贾建国(1958-),男,金陵石化公司化工二厂表面活性剂研究所副所长,主要从事表面活性剂和油田化学品的研发与应用,已发表论文5篇。

含氢硅油在硅油系列产品中由于具有活性氢基团,应用领域十分广泛。

随着我国烯丙醇聚醚的生产技术和产品质量不断提高,与含氢硅油相配套的烯丙醇聚醚已形成了系列产品;这对含氢硅油的改性及改善液体界面性能起到了关键的作用。

目前,改性后的含氢硅油在聚氨酯匀泡剂、涂料流平剂、纺织整理剂、化妆品用乳化剂、乳液聚合用消泡剂等领域的应用相当广泛,并具有较高的经济附加值。

我厂多年来对丙烯醇聚醚的合成及含氢硅油的改性、应用进行了研究,并对含氢硅油中活性氢(Si —H )的质量分数的分析方法进行了研究,建立了用核磁共振法(1H NMR )测定含氢硅油中活性氢质量分数的分析方法—实践中发现,与常规化学法[1]相比,用核磁共振法测定含氢硅油中活性氢的质量分数具有操作简单、省时、准确、可靠、所需样品量少等优点。

1　实验111　仪器和试剂核磁共振仪:EM -360L 型,60MHz ,美国,Varien ;分析天平:万分之一,上海天平仪器厂;四氯化碳:电子纯,北京化学试剂厂;苯:色谱纯,南京化学试剂厂。

112　NMR 仪器条件射频:015T (0105m G );扫描宽度:10×10-6;扫描时间:5min ;滤波:0105s 。

113样品制备准确称取60～80mg 含氢硅油,同时准确称取8mg 左右的苯作为内标,放入核磁共振仪专用试管中,用015mL 的四氯化碳做溶剂,摇匀后,把试管放入核磁共振仪的探头中,记录谱图,同时进行积分。

Vishay SiliconixSi3407DVP-Channel 20-V (D-S) MOSFETFEATURES•Halogen-free According to IEC 61249-2-21Definition•TrenchFET ® Power MOSFET •PWM Optimized •100 % R g Tested •100 % UIS Tested•Compliant to RoHS Directive 2002/95/ECPRODUCT SUMMARYV DS (V)R DS(on) (Ω)I D (A)Q g (Typ.)- 200.0240 at V GS = - 4.5 V - 8.0a 21 nC0.0372 at V GS = - 2.5 V- 8.0aNotes:a.Package limited.b.Surface Mounted on 1" x 1" FR4 board.c.t = 5 s.d.Maximum under Steady State conditions is 110 °C/W.ABSOLUTE MAXIMUM RATINGS T A = 25°C, unless otherwise notedParameter Symbol Limit UnitDrain-Source VoltageV DS - 20VGate-Source Voltage V GS± 12Continuous Drain Current (T J = 150 °C)T C = 25 °C I D - 8.0a AT C = 70 °C - 8.0aT A = 25 °C - 7.5b, c T A = 70 °C - 6.0b, cPulsed Drain Current I DM - 25Continuous Source-Drain Diode Current T C = 25 °C I S- 3.5T A = 25 °C - 1.7b, cAvalanche Current L = 0.1 mHI AS - 8Single Pulse Avalanche Energy E AS 3.2mJ Maximum Power Dissipation T C = 25 °C P D 4.2WT C = 70 °C 2.7T A = 25 °C 2.0b, c T A = 70 °C 1.3b, cOperating Junction and Storage T emperature Range T J , T stg - 55 to 150°CTHERMAL RESISTANCE RATINGSParameter Symbol Typical MaximumUnitMaximum Junction-to-Ambientb, d t ≤ 5 s R thJA 4562.5°C/WMaximum Junction-to-Foot (Drain)Steady State R thJF 2530Vishay SiliconixSi3407DVNotes:a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.b. Guaranteed by design, not subject to production testing.Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.SPECIFICATIONS T J = 25°C, unless otherwise notedParameter Symbol Test Conditions Min.Typ.Max.UnitStaticDrain-Source Breakdown Voltage V DS V GS = 0 V , I D = - 250 µA- 20V V DS Temperature Coefficient ΔV DS /T J I D = - 250 µA-18.7mV/°C V GS(th) T emperature Coefficient ΔV GS(th)/T J 3.7Gate-Source Threshold Voltage V GS(th)V DS = V GS , I D = - 250 µA - 0.65- 1.5V Gate-Source LeakageI GSS V DS = 0 V , V GS = ± 12 V ± 100nA Zero Gate Voltage Drain Current I DSS V DS = - 20 V , V GS = 0 V - 1µA V DS = - 20 V, V GS = 0 V , T J = 55 °C- 10On-State Drain Current aI D(on) V DS ≤ - 5 V, V GS = - 4.5 V - 25A Drain-Source On-State Resistance a R DS(on)V GS = - 4.5 V, I D = - 7.5 A 0.02000.0240ΩV GS = - 2.5 V, I D = - 6.4 A 0.03100.0327Forward T ransconductance a g fsV DS = - 10 V , I D = - 7.5 A25SDynamic bInput Capacitance C iss V DS = - 10 V , V GS = 0 V , f = 1 MHz1670pFOutput CapacitanceC oss 335Reverse Transfer Capacitance C rss 284Total Gate Charge Q g V DS = - 10 V , V GS = - 10 V, ID = - 7.5 A 4263nC V DS = - 10 V , V GS = - 4.5 V , I D = - 7.5 A 2132Gate-Source Charge Q gs 6Gate-Drain Charge Q gd 5Gate Resistance R g f = 1 MHz1.36.513ΩTurn-on Delay Time t d(on) V DD = - 10 V , R L = 1.7 ΩI D ≅ - 6.0 A, V GEN = - 10 V , R g = 1 Ω816ns Rise Timet r 1117Turn-Off Delay Time t d(off) 6598Fall Timet f 3959Turn-on Delay Time t d(on) V DD = - 10 V , R L = 1.7 ΩI D ≅ - 6.0 A, V GEN = - 4.5 V, R g = 1 Ω3248Rise Timet r 6293Turn-Off Delay Time t d(off) 5380Fall Timet f3857Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current I S T C = 25 °C- 3.5A Pulse Diode Forward Current a I SM - 25Body Diode VoltageV SD I S = - 6.0 A- 0.8- 1.2V Body Diode Reverse Recovery Time t rr I F = 6.0 A, dI/dt = 100 A/µs, T J = 25 °C3756ns Body Diode Reverse Recovery Charge Q rr 2233nC Reverse Recovery Fall Time t a 12nsReverse Recovery Rise Timet b25Si3407DV TYPICAL CHARACTERISTICS 25Output CharacteristicsGate ChargeTransfer CharacteristicsCapacitanceOn-Resistance vs. Junction TemperatureVishay SiliconixSi3407DVTYPICAL CHARACTERISTICS 25Source-Drain Diode Forward VoltageThreshold VoltageSafe Operating Area, Junction-to-AmbientVishay SiliconixSi3407DVTYPICAL CHARACTERISTICS 25 °C, unless otherwise noted* The power dissipation P D is based on T J(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit.Si3407DVVishay SiliconixTYPICAL CHARACTERISTICS 25°C, unless otherwise notedVishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see /ppg?69987.Vishay SiliconixPackage InformationAN823Vishay SiliconixMounting LITTLE FOOT R TSOP-6 Power MOSFETsSurface mounted power MOSFET packaging has been based on integrated circuit and small signal packages. Those packages have been modified to provide the improvements in heat transfer required by power MOSFET s. Leadframe materials and design,molding compounds, and die attach materials have been changed. What has remained the same is the footprint of the packages.The basis of the pad design for surface mounted power MOSFET is the basic footprint for the package. For the TSOP-6 package outline drawing see /doc?71200 and see /doc?72610 for the minimum pad footprint.In converting the footprint to the pad set for a power MOSFET , you must remember that not only do you want to make electrical connection to the package, but you must made thermal connection and provide a means to draw heat from the package, and move it away from the package.In the case of the TSOP-6 package, the electrical connections are very simple. Pins 1, 2, 5, and 6 are the drain of the MOSFET and are connected together. For a small signal device or integrated circuit, typical connections would be made with traces that are 0.020 inches wide. Since the drain pins serve the additional function of providing the thermal connection to the package, this level of connection is inadequate. The total cross section of the copper may be adequate to carry the current required for the application, but it presents a large thermal impedance. Also, heat spreads in a circular fashion from the heat source. In this case the drain pins are the heat sources when looking at heat spread on the PC board.Figure 1 shows the copper spreading recommended footprint for the TSOP-6 package. This pattern shows the starting point for utilizing the board area available for the heat spreading copper. T o create this pattern, a plane of copper overlays the basic pattern on pins 1,2,5, and 6. The copper plane connects the drain pins electrically, but more importantly provides planar copper to draw heat from the drain leads and start the process of spreading the heat so it can be dissipated into the ambient air. Notice that the planar copper is shaped like a “T” to move heat away from the drain leads in all directions. This pattern uses all the available area underneath the body for this purpose.FIGURE 1. Recommended Copper Spreading Footprint0.0491.250.0100.250.1674.250.0491.25Since surface mounted packages are small, and reflow soldering is the most common form of soldering for surface mount components, “thermal” connections from the planar copper to the pads have not been used. Even if additional planar copper area is used, there should be no problems in the soldering process. The actual solder connections are defined by the solder mask openings. By combining the basic footprint with the copper plane on the drain pins, the solder mask generation occurs automatically.A final item to keep in mind is the width of the power traces. The absolute minimum power trace width must be determined by the amount of current it has to carry. For thermal reasons, this minimum width should be at least 0.020 inches. The use of wide traces connected to the drain plane provides a low impedance path for heat to move away from the device.REFLOW SOLDERINGVishay Siliconix surface-mount packages meet solder reflow reliability requirements. Devices are subjected to solder reflow as a test preconditioning and are then reliability-tested using temperature cycle, bias humidity, HAST , or pressure pot. The solder reflow temperature profile used, and the temperatures and time duration, are shown in Figures 2 and 3.Ramp-Up Rate+6_C/Second Maximum Temperature @ 155 " 15_C 120 Seconds Maximum Temperature Above 180_C 70 − 180 Seconds Maximum Temperature 240 +5/−0_C Time at Maximum Temperature20 − 40 Seconds Ramp-Down Rate+6_C/Second MaximumFIGURE 2. Solder Reflow Temperature ProfileAN823Vishay Siliconix_C/s (max)3_C/s (max)140 −THERMAL PERFORMANCEA basic measure of a device’s thermal performance is the junction-to-case thermal resistance, R q jc , or the junction-to-foot thermal resistance, R q jf . This parameter is measured for the device mounted to an infinite heat sink and is therefore a characterization of the device only, in other words, independent of the properties of the object to which the device is mounted. T able 1 shows the thermal performance of the TSOP-6.TABLE 1.Equivalent Steady State Performance—TSOP-6Thermal Resistance R q jf30_C/WSYSTEM AND ELECTRICAL IMPACT OF TSOP-6In any design, one must take into account the change in MOSFET r DS(on) with temperature (Figure 4).0.60.81.01.21.41.6−50−250255075100125150On-Resistance vs. Junction TemperatureT J − Junction Temperature (_C)FIGURE 4.Si3434DVr D S (o n ) − O n -R e s i i s t a n c e (N o r m a l i z e d )Application Note 826Vishay SiliconixP P L I C A T I O N N O T ERECOMMENDED MINIMUM PADS FOR TSOP-6Legal Disclaimer Notice VishayDisclaimerALL PRODU CT, PRODU CT SPECIFICATIONS AND DATA ARE SU BJECT TO CHANGE WITHOU T NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product.Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. 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Parameters provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All operating parameters, including typical parameters, must be validated for each customer application by the customer’s technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein.Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Vishay product could result in personal injury or death. Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. 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八运放集成电路芯片型号八运放集成电路芯片型号简介引言：八运放集成电路芯片是一种常用于电子设备中的集成电路芯片，其具有多种型号和规格，可广泛应用于各种电子设备中的信号放大、滤波、混频等功能。

本文将对几种常见的八运放集成电路芯片型号进行介绍，以便读者更好地了解和应用这些芯片。

一、AD823AD823是一款高性能、低功耗的八运放集成电路芯片。

该芯片具有低噪声、高增益和低失真等特点，适用于医疗设备、心电图仪等需要高精度信号放大的应用场景。

AD823采用了先进的CMOS工艺，具有较低的功耗和较广的工作电压范围，能够满足不同应用的需求。

二、LM358LM358是一款经典的八运放集成电路芯片，被广泛应用于各种电子设备中。

该芯片具有低功耗、低噪声和高增益等特点，适用于信号放大、滤波和直流偏置等应用。

LM358采用了双运放结构，具有较高的输入阻抗和较低的输出阻抗，能够提供稳定和可靠的信号放大功能。

三、TL072TL072是一款高性能、低噪声的八运放集成电路芯片。

该芯片具有较高的增益带宽积和较低的失调电流，适用于音频放大、滤波和混频等应用。

TL072采用了双JFET输入结构，具有较高的输入阻抗和较低的输入偏置电流，能够提供高质量的信号放大和处理功能。

四、OPA2340OPA2340是一款高精度、低功耗的八运放集成电路芯片。

该芯片具有低噪声、高增益和低失真等特点，适用于精密测量仪器、音频放大和滤波等应用。

OPA2340采用了先进的CMOS工艺和镁铁封装，具有较低的功耗和较高的工作温度范围，能够在恶劣环境下稳定工作。

五、AD827AD827是一款高性能、高精度的八运放集成电路芯片。

该芯片具有低噪声、高增益和低失真等特点，适用于音频放大、测量仪器和通信设备等应用。

AD827采用了先进的CMOS工艺和镁铁封装，具有较低的功耗和较高的工作电压范围，能够满足各种应用的需求。

结论：八运放集成电路芯片是一种常用的电子元器件，具有多种型号和规格，可应用于各种电子设备中的信号放大、滤波、混频等功能。

AN1006: Differences Between Si534x/8x Revision B and Revision D SiliconThis document highlights differences between Revision B and Revision D silicon forthe following part numbers:•Si5340•Si5341•Si5342•Si5344•Si5345•Si5346•Si5347•Si5348•Si5380SUMMARYCompared to Revision B, Revision D silicon for Si534x/8x fixes several errata, supports higher maximum output frequency ranges, and offers several new features. This document outlines those differences.1. Migration from Si534x/8x Revision B to Revision DApplies to Si5380/48/47/46/45/44/42/41/40With the release of Revision D for Si534x/8x, the Revision B devices are now classified as "Not Recommended for New Designs" (NRND). As of the Revision D release date, Silicon Labs has no plans to EOL the Si5348/47/46/45/44/42/41/40 Revision B devices and will continue production of both the Revision B devices and the newer Revision D devices. As of the Revision D release date, Silicon Labs does not plan to continue production of Si5380 Revision B devices. Customers using Si5380 must follow the instructions below to migrate their existing Revision B designs to Revision D.Revision D devices are pin-compatible and footprint-compatible with Revision B devices. However, Revision D devices are not intended to be drop-in replacements for Revision B devices. As a result of changes to the circuitry in Revision D devices, their performance and behavior will not completely match that of Revision B.•Customers currently using Si5348/47/46/45/44/42/41/40 Revision B in production may continue to do so. Silicon Labs will maintain production of both Revision B and Revision D concurrently.•Customers who wish to migrate a design from Revision B to Revision D should download the latest version of ClockBuilder Pro and create a new custom OPN for Revision D with their desired configuration. Once a new Revision D OPN has been created, customers should verify functionality of the device in their system prior to starting production with Revision D.•Silicon Labs does not recommend writing a register file, settings file, or regmap that was created for Revision B to a RevisionD device. When migrating an existing design from Revision B to Revision D, customers should download the latest version ofClockBuilder Pro and create new register files, settings files, or regmap exports to be used with Revision D.1.1 Device Ordering and IdentificationApplies to Si5380/48/47/46/45/44/42/41/40The revision letter which is the 9th digit of the ordering part number indicates "D" for product Revision D. For example: Si5345A-D-GM or Si5345-Dxxxxx-GM, where xxxxx is the custom OPN ID, and D refers to the product revision.1.2 Evaluation Boards Ordering and IdentificationApplies to Si5380/48/47/46/45/44/42/41/40New evaluation boards are available for all Revision D devices. The Revision D evaluation boards are identified with "-D" in the 7th and 8th characters of the OPN. For example, the Si5345 Revision D OPN is Si5345-D-EVB.1.3 Handling Revisions in ClockBuilder ProClockBuilder Pro (CBPro) version 2.9 or later supports both Revision B and Revision D of Si534x/8x. Selection of the target device revision is done in Step 2 of the configuration Wizard:Figure 1.1. Device Revision DThe default revision is "D" for all newly created designs.CBPro stores the target device revision for each project in the .slabtimeproj project file. When an existing project file is opened, CBPro will set the target device revision according to the data stored in the project file.With the NRND classification of Si534x/8x Revision D, CBPro will no longer support creation of new custom ordering part numbers (OPNs) for Revision B. Customers with an ongoing Revision B design who still wish to create custom OPNs for Revision B should contact Silicon Labs.1.4 Changing the Target Device Revision for an Existing CBPro ProjectAt any time the target device revision for a project can be changed in CBPro by choosing Step 2 "Revision" and then selecting the new target revision from the drop-down box at the top of the screen. Customers who have created projects for Revision B in an earlier version of CBPro can migrate their projects to Revision D using the following steps:•Open the original project file in CBPro (CBPro will default to Revision B after opening the file.).•Choose Step 2: "Revision" and select device revision D.•Click the "Finish" button on the lower right side of the screen.When changing a project from Revision B to Revision D in CBPro, note the following:•CBPro will select the default values for any new registers and features that are present in Revision D but were not present in Revision B. This will enable the new Revision D features described below.•CBPro will recalculate the frequency plan using the latest algorithm for Revision D. As a result, the internal frequency plan for Revision D may differ from the plan used on a Revision B project file.Although CBPro will allow the device revision to be changed backwards to Revision D from Revision B, this is not recommended, as Revision D contains several enhancements that are not present on Revision B.AN1006: Differences Between Si534x/8x Revision B and Revision D Silicon • Errata Fixes2. Errata Fixes2.1 Revision B Errata Fixed on Revision D2.2 Revision B Errata Not Fixed on Revision D2.3 Crystal Drive LevelApplies to: Si5380In data sheet rev 0.96 for Si5380 Revision B, the maximum crystal drive level was incorrectly specified as 200 μW. This has been updated to 300 μW for the Si5380 Revision D data sheet and will be corrected in a future release of the Si5380 Revision B data sheet. In addition, the list of approved crystals in the Si5380 reference manual has been updated to reflect this change.AN1006: Differences Between Si534x/8x Revision B and Revision D Silicon • Extended Output Frequency Ranges3. Extended Output Frequency RangesRevision D of Si5345/44/42/41/40 offers higher maximum output frequencies than Revision B. The maximum output frequency for eachNote: Certain limitations apply when output frequencies above 720 MHz are selected. Refer to to the Reference Manual for more information.AN1006: Differences Between Si534x/8x Revision B and Revision D Silicon • New Features and Capabilities4. New Features and CapabilitiesA variety of new features and capabilities are available on Si534x/8x Revision D. These are described in the following sections.4.1 Frequency Ramping on Holdover ExitApplies to Si5380/48/47/46/45/44/42When coming out of holdover, Revision D allows for the adjustment of frequency ramp rate. This greatly minimizes phase transients due to frequency drift while in holdover. The frequency ramp rate adjustment occurs regardless of whether the output frequencies are using fractional or integer synthesis. This feature may be enabledd or disabled in CBPro, and a variety of ramp rates are selectable from 0.2 ppm/s to 40,000 ppm/s.•On Si5380/45/44/42, all outputs will ramp in frequency when the DSPLL is coming out of holdover.•On a Si5348/47/46, only the outputs that connect to the DSPLL that is coming out of holdover will have a ramp in frequency.4.2 Frequency Ramping on an Input Clock SwitchApplies to: Si5380/48/47/46/45/44/42When switching between clock inputs that are not synchronous, Revision D allows for the adjustment of the frequency ramp rate. This greatly minimizes phase transients on the output clocks during the input switching. The frequency ramp rate adjustment occurs regardless of whether the output frequencies are using fractional or integer synthesis. This feature may be enabled or disabled in CBPro, and a variety of ramp rates are selectable from 0.2 ppm/s to 40,000 ppm/s.•On Si5380/45/44/42, all outputs will ramp in frequency when the input clock is switched.•On a Si5348/47/46, when a DSPLL input switch occurs, only the outputs that connect to that DSPLL will have a ramp in frequency. 4.3 Holdover Exit Bandwidth SelectionApplies to: Si5380/48/47/46/45/44/42In Revision D, it is possible to select a PLL bandwidth to be used upon Holdover and Free Run exit. This bandwidth cannot be set to less than the normal bandwidth. The device returns to the normal bandwidth after the PLL has locked.4.4 Loss of Lock Detector ImprovementsApplies to: Si5380/48/47/46/45/44/42/41/40In Revision D, the Si534x/8x LOL detector has been improved to quickly assert LOL on large changes in ppm. Previously on Revision B, a large input frequency change took much longer to assert LOL. The threshold at which LOL is asserted for large ppm changes is set automatically by CBPro based on the frequency plan, and will range from 100 ppm to 1,000,000 ppm.The Si534x/8x Revision D LOL detector has also been improved to detect loss of an input clock signal. On Revision D, if an input clock edge is not detected within 417 μs, LOL will be asserted. Previously on Revision B, loss of an input clock would only trigger LOS and not LOL.4.5 Out of Frequency Detector ImprovementsApplies to: Si5380/48/47/46/45/44/42In Si534x/8x Revision D, the OOF detector has been improved so that OOF is asserted when a loss of signal occurs. Previously on Revision B, the OOF detector would not assert when a loss of signal occurs.Previously on Revision B, either the fast OOF threshold or the precision OOF threshold could be used to both assert and deassert the OOF signal. With Revision D, if the input frequency exceeds either the fast OOF threshold or the precision OOF threshold, OOF will be asserted. However, the input frequency must fall below both OOF thresholds in order for the OOF detector to be deasserted.4.6 Reductions in Output Clock Phase TransientsApplies to: Si5380/48/47/46/45/44/42When performing hitless switching, the output clock phase transient has been reduced in Si534x/8x revision D. New values for this can be found in the data sheet.Additional circuitry optimizes the switching time between Fastlock and normal bandwidth. This reduces output clock phase transients when changing bandwidths.AN1006: Differences Between Si534x/8x Revision B and Revision D Silicon • Changes to Registers from Revision B to Revision D5. Changes to Registers from Revision B to Revision DThe majority of registers present in Si534x/8x Revision B have been left unchanged in Revision D. The exceptions to this are documented below.5.1 Device RevisionApplies to: Si5380/48/47/46/45/44/42/41/40In Si534x/8x the DEVICE_REV register will now read back 0x03 to indicate Revision D. Previously this read back as 0x01 to indicate Revision B.5.2 Preamble and PostambleApplies to: Si5380/48/47/46/45/44/42/41/40In order to change certain registers that affect PLL lock status it is necessary to write a preamble and postamble sequence to the device. The values for the preamble and postamble sequences have changed for Revision D as shown below.Table 5.1. Preamble Sequence for Si5380/47/46/45/44/42/41/40Table 5.2. Postamble Sequence for Si5380/47/46/45/44/42/41/40Table 5.3. Preamble Sequence for Si5348Table 5.4. Postamble Sequence for Si5348Note that on a Revision D device, either the Revision B values or the Revision D values can be written for the preamble/postamble sequence and the device will function the same in either case. However only the Revision D values can be read back from the device.5.3 New Registers Present on Revision DApplies to Si5380/48/47/46/45/44/42/41/40Several new registers have been added to the Si534x/8x Revision D devices to support the new features described above. Details about these new features can be found in the reference manual for each device.Copyright © 2021 Skyworks Solutions, Inc. All Rights Reserved.Information in this document is provided in connection with Skyworks Solutions, Inc. (“Skyworks”) products or services. These materials, including the information contained herein, are provided by Skyworks as a service to its customers and may be used for informational purposes only by the customer. Skyworks assumes no responsibility for errors or omissions in these materials or the information contained herein. Skyworks may change its documentation, products, services, specifications or product descriptions at any time, without notice. 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