74HC165中文资料

74HC165 概述74HC165是一款高速CMOS器件，74HC165遵循JEDEC标准no.7A。

74HC165引脚兼容低功耗肖特基TTL（LSTTL）系列。

74HC165是8位并行读取或串行输入移位寄存器，可在末级得到互斥的串行输出（Q7和Q7），当并行读取（PL）输入为低时，从D0到D7口输入的并行数据将被异步地读取进寄存器内。

而当PL为高时，数据将从DS输入端串行进入寄存器，在每个时钟脉冲的上升沿向右移动一位（Q0 → Q1 → Q2，等等）。

利用这种特性，只要把Q7输出绑定到下一级的DS输入，即可实现并转串扩展。

74HC165的时钟输入是一个“门控或”结构，允许其中一个输入端作为低有效时钟使能（CE）输入。

CP和CE的引脚分配是独立的并且在必要时，为了布线的方便可以互换。

只有在CP为高时，才允许CE由低转高。

在PL上升沿来临之前，不论是CP还是CE，都应当置高，以防止数据在PL的活动状态发生位移。

74HC165 特性异步8位并行读取同步串行输入兼容JEDEC标准no.7AESD保护HBM EIA/JESD22-A114E超过2000 VMM EIA/JESD22-A115-A超过200 V温度范围-40～+85 ℃-40～+125 ℃74HC165 参数74HC165 基本参数电压 2.0～6.0V驱动电流+/-5.2 mA传输延迟16 ns@5V74HC165 其他特性最高频率56 MHz逻辑电平CMOS功耗考量低功耗或电池供电应用74HC165 封装与引脚SO16, SSOP16, DIP16, TSSOP168 位移位寄存器（并行输入，互补串行输出）简要说明当移位/置入控制端（SH/LD）为低电平时，并行数据（A－H）被置入寄存器，而时钟（CLK,CLK INH）及串行数据（SER）均无关。

当SH/LD为高电平时，并行置数功能被禁止。

CLK和CLK INK在功能上是等价的，可以交换使用。

74HCT165D中文资料DATA SHEETProduct speci?cationFile under Integrated Circuits, IC06December 1990INTEGRATED CIRCUITS74HC/HCT1658-bit parallel-in/serial-out shift registerFor a complete data sheet, please also download:The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications ?The IC06 74HC/HCT/HCU/HCMOS Logic Package Information ?The IC06 74HC/HCT/HCU/HCMOS Logic Package OutlinesFEATURESAsynchronous 8-bit parallel load ?Synchronous serial input ?Output capability: standard ?I CC category: MSI GENERAL DESCRIPTIONThe 74HC/HCT165 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.The 74HC/HCT165 are 8-bit parallel-load or serial-in shift registers with complementary serial outputs (Q 7and Q 7)available from the last stage. When the parallel load (PL)input is LOW, parallel data from the D 0toD 7inputs are loaded into the register asynchronously.When PL is HIGH, data enters the register serially at the D s input and shifts one place to the right(Q 0→Q 1→Q 2,etc.) with each positive-going clock transition. This feature allows parallel-to-serial converterexpansion by tying the Q 7output to the D S input of the succeeding stage.The clock input is a gated-OR structure which allows one input to be used as an active LOW clock enable (CE)input.The pin assignment for the CP and CE inputs is arbitrary and can be reversed for layout convenience. The LOW-to-HIGH transition of input CE should only take place while CP HIGH for predictable operation. Either the CP or the CE should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the data when PL is activated.APPLICATIONSParallel-to-serial data conversionQUICK REFERENCE DATAGND = 0 V; T amb = 25°C; t r = t f = 6 ns Notes1.C PD is used to determine the dynamic power dissipation (P D in μW):P D = C PD ×V CC 2×f i +∑(C L ×V CC 2×f o )where:f i = input frequency in MHz f o = output frequency in MHz ∑(C L ×V CC 2×f o )= sum of outputs C L =output load capacitance in pF V CC =supply voltage in V2.For HC the condition is V I = GND to V CCFor HCT the condition is V I = GND to V CC ?1.5 V ORDERING INFORMATIONSee “74HC/HCT/HCU/HCMOS Logic Package Information”.SYMBOL PARAMETERCONDITIONS TYPICAL UNITHCHCTt PHL / t PLHpropagation delay CP to Q 7,Q 7PL to Q 7,Q 7D 7 to Q 7,Q 7C L = 15 pF; V CC = 5 V161511141711ns ns ns f max maximum clock frequency 5648MHz C I input capacitance3.5 3.5pF C PD power dissipation capacitance per packagenotes 1 and 23535pFPIN DESCRIPTIONPIN NO.SYMBOL NAME AND FUNCTION1PL asynchronous parallel load input (active LOW)7Q7complementary output from the last stage9Q7serial output from the last stage2CP clock input (LOW-to-HIGH edge-triggered)8GND ground (0 V)10D s serial data input11, 12, 13, 14, 3, 4, 5, 6D0to D7parallel data inputs15CE clock enable input (active LOW)16V CC positive supply voltageFig.1 Pin configuration.Fig.2 Logic symbol.Fig.3 IEC logic symbol.FUNCTION TABLE Note1.H = HIGH voltage levelh = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition L = LOW voltage levelI =LOW voltage level one set-up time prior to the LOW-to-HIGH clock transitionq =lower case letters indicate the state of the referenced output one set-up time prior to theLOW-to-HIGH clock transition X = don’t care↑=LOW-to-HIGH clock transitionOPERATING MODESINPUTS Q n REGISTERS OUTPUTS PLCECPD SD 0-D 7Q 0Q 1-Q 6Q 7Q 7parallel load L L X X X X X X L H L H L - L H - H L H H L serial shift H H L L ↑↑l h X X L H q 0-q 5q 0-q 5q 6q 6q 6q 6hold “do nothing”HH X X X q 0q 1-q 6q 7q 7Fig.4 Functional diagram.Fig.5 Logic diagram.DC CHARACTERISTICS FOR 74HCFor the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standardI CC category: MSIAC CHARACTERISTICS FOR HCGND = 0 V; t r= t f= 6 ns; C L= 50 pFSYMBOL PARAMETERT amb(°C)UNITTEST CONDITIONS74HCV CC(V)WAVEFORMS +25?40to+85?40to+125 min.typ.max.min.max.min.max.t PHL/ t PLH propagation delay CE,CP to Q7,Q7521915165332820541352505043ns 2.04.56.0Fig.6t PHL/ t PLH propagation delayPL to Q7,Q75018141653328205413525043ns 2.04.56.0Fig.6t PHL/ t PLH propagation delay D7to Q7,Q7361310120242015030261803631ns 2.04.56.0Fig.6t THL/ t TLH output transition time 197675151319161102219ns 2.04.56.0Fig.6t W clock pulse width HIGH or LOW 801614176510020171202420ns 2.04.56.0Fig.6t W parallel load pulse width; LOW 8016145410020171202420ns 2.04.56.0Fig.6t rem removal time PL to CP,CE 100 2017228612525211503026ns 2.04.56.0t su set-up timeD s to CP,CE 801614114310020171202420ns 2.04.56.0Fig.6t su set-up time CE to CP;CP to CE 801614176510020172420ns 2.04.56.0Fig.6t su set-up timeD n to PL 801614228610020171202420ns 2.04.56.0Fig.6t h hold timeD s to CP,CED n to PL 555622555555ns 2.04.56.0Fig.6t h hold time CE to CP CP to CE 5 551765555555ns 2.04.56.0Fig.6f max maximum clockpulse frequency 630351751615242842024MHz 2.04.56.0Fig.6SYMBOL PARAMETERT amb(°C)UNITTEST CONDITIONS74HCV CC(V)WAVEFORMS +25?40to+85?40to+125min.typ.max.min.max.min.max.DC CHARACTERISTICS FOR 74HCTFor the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”.Output capability: standardI CC category: MSINote to HCT typesThe value of additional quiescent supply current (?I CC)for a unit load of 1 is given in the family specifications. To determine?I CC per input, multiply this value by the unit load coefficient shown in the table below.INPUT UNIT LOAD COEFFICIENTD n D s CP CE PL 0.35 0.35 0.65 0.65 0.65AC CHARACTERISTICS FOR 74HCT GND = 0 V; t r= t f= 6 ns;C L= 50 pFSYMBOL PARAMETERT amb(°C)UNITTEST CONDITIONS74HCTV CC(V)WAVEFORMS +25?40to+85?40to+125min.typ.max.min.max.min.max.t PHL/ t PLH propagation delayCE,CP to Q7,Q717344351ns 4.5Fig.6t PHL/ t PLH propagation delayPL to Q7,Q720405060ns 4.5Fig.6t PHL/ t PLH propagation delayD7to Q7,Q714283542ns 4.5Fig.6 t THL/ t TLH output transition time7151922ns 4.5Fig.6t W clock pulse widthHIGH or LOW1662024ns 4.5Fig.6t W parallel load pulsewidth; LOW2092530ns 4.5Fig.6t rem removal timePL to CP,CE2082530ns 4.5Fig.6t su set-up timeD s to CP,CE2022530ns 4.5Fig.6t su set-up timeCE to CP; CP to CE2072530ns 4.5Fig.6t su set-up timeD n to PL20102530ns 4.5Fig.6t h hold timeD s to CP,CE;D n to PL7?1911ns 4.5Fig.6t h hold timeCE to CP, CP to CE0?700ns 4.5Fig.6f max maximum clock pulsefrequency26442117MHz 4.5Fig.6AC WAVEFORMSThe changing to output assumes internal Q6 opposite state from Q7.(1)HC: V M= 50%; V I= GND to V CC.HCT:V M= 1.3 V; V I=GND to 3 V.Fig.6Waveforms showing the clock (CP) to output (Q7or Q7) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency.The changing to output assumes internal Q6opposite state from Q7.(1)HC: V M= 50%; V I= GND to V CC.HCT:V M= 1.3 V; V I =GND to 3 V.Fig.7Waveforms showing the parallel load (PL) pulse width, the parallel load to output (Q7or Q7)propagation delays, the parallel load to clock (CP) and clock enable (CE) removal time.(1)HC: V M= 50%; V I= GND to V CC.HCT:V M= 1.3 V; V I=GND to 3 V.Fig.8 Waveforms showing the data input (D n)to output (Q7or Q7)propagation delays when PL is LOW.CE may change only from HIGH-to-LOW while CPis LOW.The shaded areas indicate when the input ispermitted to change for predictable outputperformance.(1)HC: V M= 50%; V I= GND to V CC.HCT:V M= 1.3 V; V I=GND to 3 V.Fig.9Waveforms showing the set-up and hold times from the serial data input (D s)to the clock (CP)and clock enable (CE)inputs, from the clock enable input (CE)to the clock input (CP)and from the clock input (CP) to the clock enable input (CE).(1)HC: V M= 50%; V I= GND to V CC.HCT:V M= 1.3 V; V I=GND to 3 V.Fig.10 Waveforms showing the set-up and hold times fromthe data inputs (D n)to the parallel load input (PL).PACKAGE OUTLINESSee“74HC/HCT/HCU/HCMOS Logic Package Outlines”.。

74HC165功能说明
1.并行输入：74HC165具有8个并行输入引脚（A-H），可以同时读取8个输入信号。

这些输入信号可以是数字信号，也可以是模拟信号。

2.串行输出：74HC165具有串行输出引脚（QH），它可以将输入信号转换为串行输出信号。

输出信号的顺序与输入信号的读取顺序相同。

3.移位操作：74HC165可以通过移位操作来读取并且存储输入信号。

移位操作可以由一个时钟信号（SH/LD）和一个时钟使能信号（CLKINH）来控制。

当时钟使能信号为高电平时，移位操作生效；当时钟使能信号为低电平时，移位操作被禁止。

4.并行加载：除了移位操作之外，74HC165还可以通过并行加载操作来读取并存储输入信号。

并行加载操作可以通过时钟使能引脚（CLKINH）和并行加载引脚（PL）来控制。

当时钟使能引脚为高电平时，同时并行加载引脚为高电平，即可进行并行加载操作。

5.级联操作：多个74HC165芯片可以级联在一起，以扩展输入信号的数量。

级联操作可以通过级联引脚（SERA/B）和级联输出引脚（QH）来实现。

级联引脚可以将一个74HC165的输出连接到另一个74HC165的输入，以实现数据的串行传输。

总结起来，74HC165是一种用于将8个并行输入信号转换为串行输出信号的移位寄存器芯片。

它通过移位操作和并行加载操作来读取并存储输入信号，并且可以通过级联操作扩展输入信号的数量。

这种芯片在数字电路控制和数据采集等应用中非常常见，具有广泛的用途。

74hc165 电平标准740HC165是一种8位移位寄存器，它常用于电子设备中的数据输入和输出。

在设计和使用电子电路中，了解和理解其电平标准是非常重要的。

首先，让我们来了解一下何为电平标准。

在电子领域中，电平标准用来定义不同电压值所代表的逻辑状态，例如高电平表示1，低电平表示0。

电平标准是为了保证不同设备和电路之间的互操作性以及通信的可靠性。

740HC165的电平标准和逻辑电平定义如下：1.电源电压：740HC165的工作电压范围通常为2V至6V。

这意味着电路在这个电压范围内工作时，可以正常执行其功能。

2.逻辑高电平：对于输入信号而言，当输入电压高于特定阈值电压（通常称为ViH）时，电路将识别为逻辑高电平。

在740HC165中，典型的ViH电平为0.7VCC，其中VCC是电路的电源电压。

也就是说，如果输入电压高于0.7VCC，电路将被视为处于逻辑高电平。

3.逻辑低电平：对于输入信号而言，当输入电压低于特定阈值电压（通常称为ViL）时，电路将识别为逻辑低电平。

在740HC165中，典型的ViL电平为0.3VCC，其中VCC是电路的电源电压。

也就是说，如果输入电压低于0.3VCC，电路将被视为处于逻辑低电平。

4.输出电平：对于输出信号而言，当输出电压高于特定阈值电压（通常称为VOH）时，电路将输出逻辑高电平。

在740HC165中，典型的VOH电平为0.9VCC，其中VCC是电路的电源电压。

相反，当输出电压低于特定阈值电压（通常称为VOL）时，电路将输出逻辑低电平。

在740HC165中，典型的VOL电平为0.1VCC，其中VCC是电路的电源电压。

总结一下，740HC165的电平标准意味着输入电压高于0.7倍的电源电压将被视为逻辑高电平，低于0.3倍的电源电压将被视为逻辑低电平。

对于输出电平而言，高于0.9倍的电源电压将输出逻辑高电平，低于0.1倍的电源电压将输出逻辑低电平。

了解电平标准对于正确设计和使用电子电路至关重要。

74hｃ１65编程说明接触单片机,嵌入式有好长一段时间了，一直想找个机会把自己总结得东西拿出来晒晒太阳(其实没有什么,高手可能早已经了解),在这里我只想分享给与我一样奋斗在单片机一线得广大童鞋么一点小小得甚至卑微得经验．我们都知道通信从大得方面有两种:串行与并行。

串行得最大优点就是占用总线少,但就是传输速率低;并行恰恰相反，占用总线多,传输速率高.市面上有很多这样得芯片,有串入并出得(通俗讲就就是一个一个进，最后一块出来)，有并入串出得（相对前者而言)。

具体用哪种类型要根据我们得实际情况。

比如利用单片机显示数码管单纯得显示一个数码管如果仅仅就是为了显示那么动用单片机一个端口（如P0或Ｐ1/P２/Ｐ3)那没有什么,当然这里我说得数码管就是8段得(如果利用BCD类型１6进制数码管那么只需四个即可)就拿５１类型得单片机来说,总共32个Ｉ/O口，一般如果不就是做太大得工程就是完全够用得,但有些时候您会恨单片机怎么不多长几条“腿"，怎么省还就是不够用。

别急集成串行芯片来帮忙哈哈客套话就不多说了言归正传,今天我介绍一下几个在数码管显示或键盘处理中经常用到得移位寄存器芯片,首先登场得就是7４HC165:７4HＣ16５/７４LS165就是典型并入串出芯片,用它来读取外界键盘信息再好不过了，前提我们得了解它，我们先了解其引脚：引出端符号ﻫＣLK，ＣLK INH 时钟输入端(上升沿有效）Ａ－H 并行数据输入端SER 串行数据输入端QH 输出端ﻫQHn 互补输出端ＳH/ＬＤ移位控制/置入控制（低电平有效）真值表时序图其实瞧一个芯片就是如何使用得,不只就是瞧引脚功能，更重要得就是要瞧时序图与真值表，从其中我们可以详细得了解到它就是如何使用得,然后转化成程序代码即可.从上面我们得真值表与时序图中我们要特别注意几个端口得变化,真值表中SH／LD只有在高电平得时候方才有效；ＣLＫ，CLK INH只有当其中一个为低电平得时候，另一个时钟才能正确得输入，这就是非常重要得（一般得我们在使用时，可以将其中得一个直接接地,另一个做时钟输入端口使用)．但就是我们做事要细心,要一丝不苟，从时序图中我们瞧到SH／LD有一个负脉冲这就是什么缘故呢?在程序设计中如果忽略了此处，那么注定结果就是悲剧得。

May 2008 Rev 51/21M74HC1658-bit PISO shift registerFeatures■High speed:–t PD = 15 ns (typ.) at V CC = 6 V ■Low power dissipation:–I CC = 4 μA (max.) at T A = 25 °C ■High noise immunity:V NIH = V NIL = 28 % V CC (Min.)■Symmetrical output impedance:|I OH | = I OL = 4 mA (min)■Balanced propagation delays:t PLH ≅ t PHL■Wide operating voltage range:V CC (opr) = 2 V to 6 V■Pin and function compatible with 74 series 165DescriptionThe M74HC165 is a high speed CMOS 8-bit PISO (parallel-in-serial-out) shift registerfabricated with silicon gate C 2MOS technology. This device contains eight clocked master slave RS flip-flops connected as a shift register, with auxiliary gating to provide overridingasynchronous parallel entry. The parallel data enter when the shift/load input is low and can change while shift/load is low, provided that the recommended set-up and hold times areobserved. For clocked operation, shift/load must be high. The two clock inputs perform identically: one can be used as a clock inhibit by applying a high signal, to allow this operation clocking is accomplished through a 2-input nor gate. T o avoid double clocking, however, the inhibit signal should only go high while the clock is high. Otherwise the rising inhibit signal causes the same response as rising clock edge. All inputs are equipped with protection circuits against static discharge and transient excess voltage.Table 1.Device summaryOrder code Package Packaging M74HC165B1R DIP-16T ube M74HC165RM13TR SO-16Tape and reel M74HC165TTRTSSOP16Tape and reelContents M74HC165Contents1Logic symbols and I/O equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . 32Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.1Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.2Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Logic states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53.1Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53.2Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53.3Timing chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74.1Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172/21M74HC165Logic symbols and I/O equivalent circuit 1 Logic symbols and I/O equivalent circuit3/21Pin settings M74HC1654/212 Pin settings2.1 Pin connectionFigure 3.Pin connection (top through view)2.2 Pin descriptionTable 2.Pin descriptionPin numberSymbol Name and function1SHIFT/LOAD Data inputs2CLOCK Clock input (low to high, edge triggered)7QH Complementary output 9QH Serial output 10SI Serial input 11, 12, 13, 14, 3, 4, 5, 6A to H Parallel data inputs 15CLOCK INHClock inhibit 8GND Ground (0V)16V CCPositive supply voltageM74HC165Logic states5/213 Logic states3.1 Truth tableNote:a........h : the level of steady input voltage at inputs a through respectively QAn - QGn : the level of QA - QG, respectively. Before the most recent transition of the clock.3.2 Logic diagramFigure 4.Logic diagramNote:This logic diagram has not to be used to estimate propagation delaysLogic states M74HC1656/213.3 Timing chartFigure 5.Timing chartM74HC165Maximum rating7/214 Maximum ratingStressing the device above the rating listed in the “absolute maximum ratings” table maycause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the STMicroelectronics sure program and other relevant quality documents.4.1 Recommended operating conditionsTable 4.Absolute maximum ratingsSymbol ParameterValue Unit V CC Supply voltage -0.5 to +7V V I DC input voltage -0.5 to V CC + 0.5V V O DC output voltage -0.5 to V CC + 0.5V I IK DC input diode current ± 20mA I OK DC output diode current ± 20mA I O DC output current ± 25mA I CC or I GND DC V CC or ground current ± 50mA P D Power dissipation 500(1)1.(*) 500mW at 65 °C ; derate to 300mW by 10mW/°C from 65°C to 85°CmW T stg Storage temperature -65 to +150°C T LLead temperature (10 sec)300°CTable 5.Recommended operating conditionsSymsbol ParameterValue Unit V CC Supply voltage 2 to 6V V I Input voltage 0 to V CC V V O Output voltage 0 to V CC V T opOperating temperature-55 to 125°C t r , t fInput rise and fall timeV CC = 2.0V0 to 1000ns V CC = 4.5V 0 to 500ns V CC = 6.0V0 to 400nsElectrical characteristics M74HC1658/215 Electrical characteristicsTable 6.DC specificationsSymbolParameterTest conditionValueUnit V CC(V)T A = 25°C -40 to 85°C -55 to 125°C Min Typ Max Min MaxMin MaxV IHHigh level input voltage2.01.5 1.5 1.5V4.5 3.15 3.15 3.156.0 4.24.24.2V ILLow level input voltage2.00.50.50.5V 4.5 1.35 1.35 1.356.0 1.81.81.8V OHHigh level output voltage2.0I O = -20 μA 1.9 2.0 1.9 1.9V4.5I O =-20 μA 4.4 4.5 4.4 4.46.0I O =-20 μA 5.96.0 5.9 5.94.5I O =-4.0 mA 4.18 4.31 4.13 4.106.0I O =-5.2 mA 5.685.8 5.63 5.60V OLLow level output voltage2.0I O =20 μA 0.00.10.10.1V 4.5I O =20 μA 0.00.10.10.16.0I O =20 μA 0.00.10.10.14.5I O =4.0 mA 0.170.260.330.406.0I O =5.2 mA0.180.260.330.40I I Input leakage current 6.0V I = V CC or GND ± 0.1± 1± 1μA I CCQuiescent supply current6.0V I = V CC or GND44080μAM74HC165Electrical characteristics9/21Table 7.AC electrical characteristics (C L = 50 pF , Input t r = t f = 6ns)SymbolParameterTest conditionValueUnitV CC (V)T A = 25°C -40 to 85°C -55 to 125°C MinTyp Max MinMax MinMax t TLH t THLOutput transition time2.0307595110ns4.581519226.07131619t PLH t PHL Propagation delaytime(CLOCK - QH, QH) 2.0551********ns4.5183038456.015263338t PLH t PHLPropagation delay time(SHIFT/LOAD - QH, QH) 2.065165205250ns4.5213341506.018283543t PLH t PHL Propagation delaytime(H - QH, QH)2.052135170205ns4.5172734416.014232935fMAXMaximum clock frequency2.07.415 6.0 4.8MHz4.5376030246.044713528t W(H) t W(L)Minimum pulse width (CLOCK) 2.024*******ns4.561519226.05131619t W(L)Minimum pulse width(SHIFT/LOAD)2.0327595110ns 4.581519226.07131619t sMinimum set-uptime(PI - S HIFT/LOAD) (SI - CLOCK) (SHIFT/LOAD - CK)2.024*******ns4.561519226.05131619t hMinimum hold time (PI - SHIFT/LOAD)(SI - CLOCK)(SHIFT/LOAD - CK)2.0000ns 4.50006.0000t REMMinimum removal time(CLOCK - CK INH)2.020*******ns 4.551519226.04131619Electrical characteristicsM74HC16510/21Table 8.Capacitive characteristicsSymbolParameterTest conditionValue UnitV CC (V)T A = 25 °C -40 to 85°C -55 to 125°C MinTyp Max MinMax MinMax C IN Input capacitance 5.05101010pF C PDPower dissipation capacitance (1)5.055pF1.C PD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating currentconsumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I CC(opr) = C PD x V CC x f IN + I CCM74HC165Test circuit11/216 Test circuitC L = 50pF or equivalent (includes jig and probe capacitance)R T = Z OUT of pulse generator (typically 50Ω)Waveforms M74HC16512/217 WaveformsFigure 7.Serial mode propagation delay (f = 1MHz; 50% duty cycle)Figure 8.Parallel mode propagation delay (f = 1MHz; 50% duty cycle)M74HC165Waveforms13/21Figure 9.Minimum pulse width (S/L), propagation delay times (f =1MHz; 50% duty cycle)Figure 10.Setup and hold time (PI to S/L)(f = 1MHz; 50% duty cycle)Figure 11.Minimum removal time (CK INH to CK) (f =1MHz; 50% duty cycle)Package mechanical data M74HC165 8 Package mechanical dataIn order to meet environmental requirements, ST offers these devices in ECOPACK®packages. These packages have a Lead-free second level interconnect . The category ofsecond level interconnect is marked on the package and on the inner box label, incompliance with JEDEC Standard JESD97. The maximum ratings related to solderingconditions are also marked on the inner box label. ECOPACK is an ST trademark.ECOPACK specifications are available at: .14/21M74HC165Package mechanical data15/21Package mechanical data M74HC16516/21M74HC165Package mechanical data17/21Package mechanical data M74HC16518/21M74HC165Package mechanical data19/21Revision history M74HC16520/219 Revision historyTable 9.Document revision historyDate RevisionChanges9-Jul-20013Final release.21-Mar-20074The document has been reformatted, updated T able 2: Pindescription on page 426-May-20085Removed: M74HC165M1R order code.Minor changes in the text.Added: SO-16 and TSSOP16 tape and reel specifications.M74HC165Please Read Carefully:Information in this document is provided solely in connection with ST products. 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HD74HC165Parallel-load 8-bit Shift RegisterADE-205-457 (Z)1st. EditionSep. 2000 DescriptionThis 8-bit serial shift register shifts data from QA to QHwhen clocked. Parallel inputs to each stage areenabled by a low level at the Shift/Load input. Also included is a gated clock input and a complementary output from the eighth bit.Clocking is accomplished through a 2-input NOR gate permitting one input to be used as a clock inhibit function. Holding either of the clock inputs high inhibits clocking, and holding either clock input low with the Shift/Load input high enables the other clock input. Data transfer occurs on the positive going edge of the clock. Parallel loading is inhibited as long as the Shift/Load input is high. When taken low, data at the parallel inputs is loaded directly into the register independent of the state of the clock.Features• High Speed Operation: t pd (Clock to Q H) = 21 ns typ (C L = 50 pF)• High Output Current: Fanout of 10 LSTTL Loads• Wide Operating Voltage: V CC = 2 to 6 V• Low Input Current: 1 µA max• Low Quiescent Supply Current: I CC (static) = 4 µA max (Ta = 25°C)Function TableInputsParallel Internal outputs OutputShift/Load Clock Inhibit Clock Serial A ······ H QA QBQHL X X X a ······h a b hH L L X X QA0QB0QH0H L H X H QAn QGnH L L X L QAn QGnH H X X X QA0QB0QH0HD74HC165 Pin ArrangementTiming Diagram2HD74HC1653DC CharacteristicsTa = 25°CTa = –40 to +85°CItem Symbol V CC (V)Min Typ Max MinMax Unit Test ConditionsInput voltageV IH2.0 1.5—— 1.5—V4.5 3.15—— 3.15—6.04.2—— 4.2—V IL2.0——0.5—0.5V 4.5—— 1.35—1.356.0——1.8— 1.8Output voltageV OH2.0 1.9 2.0— 1.9—VVin = V IH or V IL I OH = –20 µA4.5 4.4 4.5— 4.4—6.05.96.0— 5.9—4.5 4.18—— 4.13—I OH = –4 mA 6.05.68——5.63—I OH = –5.2 mAV OL2.0—0.00.1—0.1VVin = V IH or V IL I OL = 20 µA4.5—0.00.1—0.16.0—0.00.1—0.14.5——0.26—0.33I OL = 4 mA 6.0——0.26—0.33I OL = 5.2 mAInput current Iin 6.0——±0.1—±1.0µA Vin = V CC or GNDQuiescent supply currentI CC6.0——4.0—40µAVin = V CC or GND, Iout = 0 µAHD74HC1654AC Characteristics (C L = 50 pF, Input t r = t f = 6 ns)Ta = 25°CTa = –40 to +85°CItemSymbol V CC (V)Min Typ Max MinMax Unit Test ConditionsMaximum clock f max2.0——5—4MHzfrequency4.5——27—216.0——32—25Propagation delay t PLH 2.0——150—190nsClock to Q H or Q Htimet PHL 4.5—2130—386.0——26—332.0——160—200Shift/Load to Q H or Q H4.5—2332—406.0——27—342.0——150—190H to Q H or Q H4.5—2130—386.0——26—33Setup timet su2.0100——125—nsParallel data inputs to 4.520–3—25—Shift/Load 6.017——21—2.0100——125—Sherial input to Clock4.5203—25—6.017——21—2.0100——125—Shift/load to Clock 4.520——25—6.017——21—Removal timet rem2.0100——125—nsClock to Clock inhibit or 4.5206—25—Clock inhibit to Clock 6.017——21—Hold timet h2.05——5—nsShift/Load to parallel data input4.55–3—5—6.05——5—2.05——5—Clock to Serial data input4.553—5—6.05——5—2.05——5—Clock to Shift/Load 4.55——5—6.05——5—HD74HC1655AC Characteristics (C L = 50 pF, Input t r = t f = 6 ns) (cont)Ta = 25°CTa = –40 to +85°CItem Symbol V CC (V)Min Typ Max MinMax Unit Test Conditions Pulse widtht w2.080——100—nsClock, Shift/Load4.5166—20—6.014——17—Output rise/fall t TLH 2.0——75—95ns timet THL 4.5—515—196.0——13—16Input capacitanceCin——510—10pFHD74HC165 Package Dimensions6HD74HC1657HD74HC1658Cautions1.Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,copyright, trademark, or other intellectual property rights for information contained in this document.Hitachi bears no responsibility for problems that may arise with third party’s rights, includingintellectual property rights, in connection with use of the information contained in this document.2.Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use.3.Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,traffic, safety equipment or medical equipment for life support.4.Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installationconditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product.5.This product is not designed to be radiation resistant.6.No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi.7.Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products.Hitachi, Ltd.Semiconductor & Integrated Circuits.Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109Copyright © Hitachi, Ltd., 2000. All rights reserved. Printed in Japan.Hitachi Asia Ltd. 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