- 1、下载文档前请自行甄别文档内容的完整性，平台不提供额外的编辑、内容补充、找答案等附加服务。
- 2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
- 3、如文档侵犯您的权益，请联系客服反馈,我们会尽快为您处理(人工客服工作时间：9:00-18:30)。
2.1 Introduction
In this chapter, we study the physics of MOSFETs at an elementary level, covering the bare minimum that is necessary for basic analog design. We begin our study with the structure of MOS transistors and derive their I-V characteristics. Next, we describe second-order effects such as body effect, channel length modulation and subthreshold conduction. In the last, we derive a small signal model.
If Vds<Vgs-Vth, the device is operated in the triode region. Vgs-Vth: overdrive voltage
2011-12-14 11
W/L: aspect ratio
DME, GDUT
Design of Analog CMOS Integrated Circuits
2011-12-14 8 DME, GDUT
Design of Analog CMOS Integrated Circuits
2.3.2 Derivation of I-V characteristics-1
The current flows through a semiconductor bar can be described as :
2011-12-14 12
Vds 1 = I ds µ W C V − V n ox ( GS th ) L
DME, GDUT
Design of Analog CMOS Integrated Circuits
2.3.2 Derivation of I-V characteristics-5
If Vds>Vgs-Vth, Ids becomes relatively constant and we define the device is operated in the saturation region. Why? The density of inversion layer charge is proportional to Vgs-V(x)-Vth. If channel potential V(x) approaches Vgs-Vth, then Qd(x) drops to zero and the channel is pinch off. As Vds increase further, the point at which Qd equals to zero gradually moves toward the source.
2011-12-14
3
DME, GDUT
Design of Analog CMOS Integrated Circuits
2.2.1 MOS structure
Fabricated on a p-type substrate (bulk or body), the device consists of two heavily doped n regions (source and drain), a heavily-doped piece of polysilicon (gate) and a thin layer of silicon dioxide (gate oxide). The structure is symmetric with respect to S and D. Source is defined as the terminal that provides the charge carriers and drain as the terminal that collects them. The source and drain may exchange roles as the voltage varied. LD is the amount of side diffusion, Ldrawn is the total length of gate, Leff is the effective length which is equal to Leff=Ldrawn-2LD.
Qdep = 4qε si φ f N sub
1. Φms is the difference between the work functions of the polysilicon gate and the silicon substrate. 2. Φf is the difference between the intrinsic Fermi level and the actual Fermi level. 3. Qdep is the charge in the depletion region. (negative ions)
Outline
Introduction MOS Structure MOS I-V Characteristics Second-order Effects MOS Small Signal Model
2011-12-14
2
DME, GDUT
Design of Analog CMOS Integrated Circuits
The charge density can be calculated by:
Qd = WCox (VGS − Vth − V ( x ) )
Cox: Capacitance of gate oxide per unit area
Cox = εε ox / tox
V ( x ) = Vds ⋅ x / L
6
DME, GDUT
Design of Analog CMOS Integrated Circuits
2.3.1 Threshold voltage-1
As Vgs increases, the interface of NMOS begins with holes accumulation, and then depleted with negative ions as to mirror the charge in the gate. Finally, when the surface potential reaches a sufficiently positive value, the interface is inversed with the electrons flow from the source and thus a channel is formed between the source and drain. The threshold voltage is defined as the gate voltage for which the interface is “as much n-type as the substrate is p-type”.
Lectus
Dr. Liu Yuan Liuyuan@ Department of Microelectronics Guangdong University of Technology
Design of Analog CMOS Integrated Circuits
The MOSFET is operated as a resistor whose value is controlled by the overdrive voltage. With the condition Vds<<2(Vgs-Vth), the device is operated in the deep triode region.
2.3.2 Derivation of I-V characteristics-4
If Vds<<2(Vgs-Vth), then
I ds = µn W 1 2 Cox (VGS − Vth )Vds − Vds L 2
I ds ≈ µn
Ron =
W Cox (VGS − Vth )Vds L
I = Qd ⋅ v
Qd: charge density along the direction of current V: velocity of the charge
2011-12-14
9
DME, GDUT
Design of Analog CMOS Integrated Circuits
2.3.2 Derivation of I-V characteristics-2
2011-12-14 5 DME, GDUT
Design of Analog CMOS Integrated Circuits
2.3 MOS I-V characteristics
Threshold voltage Derivation of I-V characteristics
2011-12-14
2011-12-14
13
DME, GDUT
Design of Analog CMOS Integrated Circuits
2011-12-14 4 DME, GDUT
Design of Analog CMOS Integrated Circuits
2.2.2 MOS symbols
The substrate is denoted by “B” (bulk) rather than “S” to avoid confusion with the source. The source is positioned on top as a visual aid because it has a higher potential than its gate. The bulk terminal of NMOS and PMOS are always tied to ground and Vdd, we usually omit these connections in drawing.
