FPGA可编程逻辑器件芯片XC2V8000-5FG256I中文规格书

lacement Part
No direct replacement No direct replacement No direct replacement No direct replacement No direct replacement No direct replacement No direct replacement No direct replacement No direct replacement No direct replacement No direct replacement No direct replacement No direct replacement No direct replacement No direct replacement
Part Number
Replacement Part
XCV405E-6BG560C XCV405E-6BG560I XCV405E-6BGG560C XCV405E-6BGG560I XCV405E-6FG676C XCV405E-6FG676I XCV405E-7BG560C XCV405E-7BG560I XCV405E-7BGG560C XCV405E-7BGG560I XCV405E-7FG676C XCV405E-7FG676I XCV405E-8BG560C XCV405E-8BGG560C XCV405E-8FG676C
• Spartan-IIE Family FPGA Commercial Products Affected • Virtex-E Family FPGA Commercial Products Affected • Virtex-EM Family FPGA Commercial Products Affected • Virtex-II Family FPGA Commercial Products Affected • EasyPath Virtex-II Family FPGA Ordering Products Affected • EasyPath Virtex-II Family FPGA Quoting Products Affected • Automotive Market (XA) Spartan-IIE Family FPGA Products Affected • Defense/Aerospace (XQ) Spartan-IIE FPGA Products Affected • Appendix A – All Commercial SCD Products Affected

Appendix A MGT to GTX Transceiver Design MigrationOverviewThis appendix describes important differences regarding migration from theVirtex®-II Pro and Virtex-4 multi-gigabit transceivers (MGTs) to the Virtex-5 FPGARocketIO™ GTX transceivers. This appendix does not describe all of the features andcapabilities of these devices but only highlights relevant PCB, power supply, and referenceclock differences. For more information on Virtex-II Pro and Virtex-4 FPGAs, refer toVirtex-II Pro and Virtex-II Pro X Complete Data Sheet [Ref11], RocketIO Transceiver User Guide[Ref12], and Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide[Ref13].Primary DifferencesVirtex-5 FXT/TXT FPGAs are a different family from the Virtex-II Pro and Virtex-4families. The Virtex-5 FXT/TXT devices are not pin compatible with these previousgeneration devices. However, many aspects of the MGTs and GTX transceivers are thesame between families. The primary differences are:•Number of MGTs and GTX transceivers per device•Clocking•Serial rates and ranges•Encoding standards – 8B/10B, 64B/66B, SONET, and others•Clock multiplier settings and PLL ranges•Flexibility due to partial reconfiguration, PMA programming bus, dynamicreconfiguration port (DRP)•Board design guidelinesMGTs per DeviceVirtex-5 FPGAs allow for a large range of GTP and GTX transceivers per device. Table A-1shows the number of transceivers available for each family.Table A-1:Transceivers per DeviceVirtex Device# of TransceiversVirtex-II Pro FPGA4, 8, 12, 16, 20Virtex-4 FPGA8, 12, 16, 20, 24RXSTA TUS BusSeveral buses have changed over the FPGA generations to improve the information that is indicated. Table A-13 shows the migration from Virtex-II Pro to Virtex-5 devices.Pre-emphasis, Differential Swing, and EqualizationThe differential signaling techniques are more robust in recent Xilinx transceivers. The Virtex-5 FPGA GTP and GTX transceivers add ports to control TX characteristics tosimplify reconfiguration. Table A-14 shows the migration of attributes from Virtex-II Pro and Virtex-4 MGTs to Virtex-5 FPGA GTP and GTX transceivers.Table A-13:Status Bus ChangesDescription Virtex-II ProMGT Virtex-4 MGT Virtex-5 FPGA (LXT and SXT) GTP Transceiver (1)Virtex-5 FPGA (FXT and TXT)GTX Transceiver (2)Indicates channel bonding complete CHBONDONE (3)RXSTATUS[5]RXCHANISALIGNED0RXCHANISALIGNED1RXCHANISALIGNED0RXCHANISALIGNED1Indicates status bus is status, data, event N/ARXSTATUS[4:3]RXSTATUS[2:0]RXSTATUS[2:0]Indicates channel bonding or clock correction pointers changeRXCLKCORCNT0[2:0]RXCLKCORCNT0[2:0]RXSTATUS[2:0]RXCHANREALIGN0RXCHANREALIGN1RXCHANREALIGN0RXCHANREALIGN1Indicates that an RX buffer hasunderflow/overflowRXBUFSTATUS[1]RXBUFERR RXBUFSTATUS[2:0]RXBUFSTATUS[2:0]Notes:1.Signal optimization settings are independent between both GTP transceivers of a GTP_DUAL tile. GTP0 is indicated by the suffix “0” after the signal name, and GTP1 is indicated by the suffix “1” (for example, RXEQMIX0 or RXEQMIX1).2.Signal optimization settings are independent between both GTX transceivers of a GTX_DUAL tile. GTX0 is indicated by the suffix “0” after the signal name, and GTX1 is indicated by the suffix “1” (for example, RXEQMIX0 or RXEQMIX1).3.RXCLKCORCNT must go to 3'b101 before channel bonding is complete.Table A-14:Signal Optimization Attributes and PortsDescriptionVirtex-II ProMGTVirtex-4 MGTVirtex-5 FPGAGTP Transceivers (1)Virtex-5 FPGAGTX Transceivers (1)PortsAttributesPortsAttributesControls TX pre-emphasis and edge rateTX_PREMPHASISTXPRE_PRDRV_DAC TXPRE_TAP_PD TXSLEWRATETXPOST_PRDRV_DAC TXDAT_PRDRV_DAC TXPOST_TAP_PDTXPREEMPHASIS[3:0]TXPREEMPHASIS[3:0]Controlsdifferential amplitude of the transmitted signalTX_DIFF_CTRLTXPRE_TAP_DAC TXPOST_TAP_DAC TXDAT_TAP_DACTXBUFDIFFCTRL0[2:0] TXBUFDIFFCTRL1[2:0] TXDIFFCTRL0[2:0] TXDIFFCTRL1[2:0]TX_DIFF_BOOST_0TX_DIFF_BOOST_1TXBUFDIFFCTRL0[2:0]TXBUFDIFFCTRL1[2:0] TXDIFFCTRL0[2:0] TXDIFFCTRL1[2:0]Appendix C:8B/10B Valid Characters。

Chapter 6:GTX Transmitter (TX)FPGA TX InterfaceOverviewThe FPGA TX interface is the FPGA’s gateway to the TX datapath of the GTX transceiver.Applications transmit data through the GTX transceiver by writing data to the TXDATAport on the positive edge of TXUSRCLK2.The width of the port can be configured to be one, two, or four bytes wide. The actualwidth of the port depends on the GTX_DUAL tile's INTDATAWIDTH setting (controls thewidth of the internal datapath), and whether or not the 8B/10B encoder is enabled. Portwidths can be 8 bits, 10 bits, 16 bits, 20 bits, 32 bits, and 40 bits.The rate of the parallel clock (TXUSRCLK2) at the interface is determined by the TX linerate, the width of the TXDATA port, and whether or not 8B/10B encoding is enabled. Asecond parallel clock (TXUSRCLK) must be provided for the internal PCS logic in thetransmitter. This chapter shows how to drive the parallel clocks and explains theconstraints on those clocks for correct operation. The highest transmitter data rates requirea 4-byte interface to achieve a TXUSRCLK2 rate in the specified operating range.Ports and AttributesTable6-1 defines the FPGA TX interface ports.Table 6-1:FPGA TX Interface PortsPort Direction Clock Domain DescriptionINTDATAWIDTH In Async Specifies the width of the internal datapath for the entire GTX_DUAL tile. This shared port is also described in “Shared PMA PLL,” page 86.•0: Internal datapath is 16 bits wide•1: Internal datapath is 20 bits wideREFCLKOUT Out N/A The REFCLKOUT port from each GTX_DUAL tile provides direct access to the reference clock provided to the shared PMA PLL (CLKIN). It can be routed for use in the FPGA logic.TXCHARDISPMODE0[3:0] TXCHARDISPMODE1[3:0]In TXUSRCLK2TXCHARDISPMODE and TXCHARDISPVAL allow controlof the 8B/10B outgoing data disparity when 8B/10Bencoding is enabled.When 8B/10B encoding is disabled, TXCHARDISPMODE isused to extend the data bus for TX interfaces with a widththat is a multiple of 10. See “FPGA TX Interface,” page 120.TXCHARDISPMODE[3] corresponds to TXDATA[31:24]TXCHARDISPMODE[2] corresponds to TXDATA[23:16]TXCHARDISPMODE[1] corresponds to TXDATA[15:8]TXCHARDISPMODE[0] corresponds to TXDATA[7:0]Table6-5, page133 shows how to use TXCHARDISPMODEto control the disparity of outgoing data when 8B/10Bencoding is enabled.FPGA TX InterfaceTXCHARDISPVAL0[3:0] TXCHARDISPVAL1[3:0]In TXUSRCLK2TXCHARDISPVAL and TXCHARDISPMODE allow controlof the 8B/10B outgoing data disparity when 8B/10Bencoding is enabled.When 8B/10B encoding is disabled, TXCHARDISPVAL isused to extend the data bus for 10- and 20-bit TX interfaces.See “FPGA TX Interface,” page 120.TXCHARDISPVAL[3] corresponds to TXDATA[31:24]TXCHARDISPVAL[2] corresponds to TXDATA[23:16]TXCHARDISPVAL[1] corresponds to TXDATA[15:8]TXCHARDISPVAL[0] corresponds to TXDATA[7:0]Table6-5, page133 shows how to use TXCHARDISPVAL tocontrol the disparity of outgoing data when 8B/10Bencoding is enabled.TXDATA0[31:0] TXDATA1[31:0]In TXUSRCLK2The bus for transmitting data. The width of this port dependson TXDATAWIDTH:•TXDATAWIDTH = 0: TXDATA[7:0] = 8 bits wide•TXDATAWIDTH = 1: TXDATA[15:0] = 16 bits wide•TXDATAWIDTH = 2: TXDATA[31:0] = 32 bits wideWhen a 10-bit, 20-bit, or 40-bit bus is required, theTXCHARDISPVAL and TXCHARDISPMODE ports from the8B/10B encoder are concatenated with the TXDATA port. SeeFigure6-3, page123.TXDATAWIDTH0[1:0] TXDATAWIDTH1[1:0]In TXUSRCLK2Selects the width of the TXDATA port.•0: TXDATA is 8 bits or 10 bits wide•1: TXDATA is 16 bits or 20 bits wide•2: TXDATA is 32 bits or 40 bits wide•3: ReservedTXENC8B10BUSE0 TXENC8B10BUSE1In TXUSRCLK2TXENC8B10BUSE is set High to enable the 8B/10B encoder.INTDATAWIDTH must also be High.0: 8B/10B encoder bypassed. This option reduces latency.1: 8B/10B encoder enabled. INTDATAWIDTH must beHigh.TXOUTCLK0 TXOUTCLK1Out N/AThis port provides a parallel clock generated by the GTXtransceiver. This clock can be used to drive TXUSRCLK forone or more GTX transceivers. The rate of the clock dependson INTDATAWIDTH:•INTDATAWIDTH is Low: F TXOUTCLK = Line Rate/16•INTDATAWIDTH is High: F TXOUTCLK = Line Rate/20Note:•When INTDATAWIDTH is High, the duty cycle is 60/40instead of 50/50.•When oversampling is enabled, the line rate in thecalculation of F TXOUTCLK is equal to the oversampled linerate, not the PMA line rate.Table 6-1:FPGA TX Interface Ports (Cont’d)Port Direction Clock Domain DescriptionTX Out-of-Band/Beacon SignalingRX OOB/Beacon SignalingTable7-14 defines the RX OOB/beacon signaling attributes.Table 7-14:RX OOB/Beacon Signaling AttributesAttribute Type DescriptionOOB_CLK_DIVIDER Integer Sets the squelch clock rate. The squelch clock must be set between 25MHz and 37.5MHz, as close to 25MHz as possible for the SATA OOB detector to work correctly.Squelch Clock rate = CLKIN/OOB_CLK_DIVIDERValid divider settings are 1, 2, 4, 6, 8, 10, 12, and 14.OOBDETECT_THRESHOLD_0 OOBDETECT_THRESHOLD_13-bit BinarySets the minimum differential voltage between RXN and RXP.When the differential voltage drops below this level, theincoming signal is considered an OOB signal. This 3-bit binaryencoded attribute has the following nominal values of the OOBthreshold voltage(1):Value OOB Nominal Threshold Voltage [mV]000 – 101Not supported110 (default)9011195RX_STATUS_FMT_0 RX_STATUS_FMT_1StringDefines which status encoding is used:PCIE: PCI Express encodingSATA: SATA encodingSATA_BURST_VAL_0 SATA_BURST_VAL_13-bit BinaryNumber of bursts required to declare a COM match. The defaultfor SATA_BURST_VAL is 4, which is the burst count specified inSATA for COMINIT, COMRESET, and COMWAIT.SATA_IDLE_VAL_0 SATA_IDLE_VAL_13-bit BinaryNumber of idles required to declare a COM match. Each idle is anOOB signal with a length that matches eitherCOMINIT/COMRESET or COMWAIT. When the SATA detectorstarts to count one type of idle (for example,COMRESET/COMINIT), it resets the count if it receives the othertype. This value defaults to 3 to match the SATA specification.SATA_MAX_BURST_0 SATA_MAX_BURST_1IntegerSets the threshold for the SATA detector to reject a burst in termsof squelch clock cycles. SATA_MAX_BURST has valid valuesbetween 1 and 61 (the default is 7) and must be greater thanSATA_MIN_BURST. See the “Description” section to learn howto calculate the best value for a given squelch clock rate.SATA_MAX_INIT_0 SATA_MAX_INIT_1IntegerSets the maximum time allowed for a COMINIT/COMRESETidle for the SATA detector in terms of squelch clock cycles.SATA_MAX_INIT has valid values between 1 and 61 (the defaultis 22) and must be greater than SATA_MIN_INIT. See the“Description” section to learn how to calculate the best value fora given squelch clock rate.SATA_MAX_WAKE_0 SATA_MAX_WAKE_1IntegerSets the maximum time allowed for a COMWAKE idle for theSATA detector in terms of squelch clock cycles.SATA_MAX_WAKE has valid values between 1 and 61 (thedefault is 7) and must be greater than SATA_MIN_WAKE. See the“Description” section to learn how to calculate the best value fora given squelch clock rate.Configurable Loss-of-Sync State Machine。

These generic primitives can each support most of the available differential I/O standards:•IBUFDS: Differential input buffer•IBUFDS_INTERMDISABLE: Differential input buffer with on-die input termination disable control and input buffer disable•IBUFDS_DIFF_OUT: Differential input buffer with complementary outputs•IBUFDS_DIFF_OUT_INTERMDISABLE: Differential input buffer with complementary outputs, input buffer disable, and on-die input termination disable control•IOBUFDS: Differential bidirectional buffer•IOBUFDS_INTERMDISABLE: Differential bidirectional buffer with on-die input termination disable control and input buffer disable•IOBUFDS_DIFF_OUT: Differential bidirectional buffer with complementary outputs from the input buffer•IOBUF_DIFF_OUT_INTERMDISABLE: Differential bidirectional buffer with complementary outputs from the input buffer with on-die input termination disable controls and input buffer disable controls•OBUFDS: Differential output buffer•OBUFTDS: Differential tristate output bufferHD IOB Supported Single-Ended StandardsLVTTLThe LVTTL standard is a general-purpose EIA/JESD standard for 3.3V applications that uses a single-ended CMOS input buffer and a push-pull output buffer.LVCMOSThe low-voltage CMOS (LVCMOS) standards LVCMOS33 (3.3V), LVCMOS25 (2.5V), and LVCMOS18 (1.8V) are implemented with CMOS transistors. These standards are defined in the JEDEC standards JESD8-7A, JESD8-5A, and JESD 8C.01.Table 108: Allowed Attributes for LVTTL, LVCMOS18, LVCMOS25, and LVCMOS33 I/O PrimitivesAttributesIBUF/IBUFE3OBUF/OBUFT/IOBUF/IOBUFE3 Allowed Values Default Allowed Values DefaultIOSTANDARD LVTTL, LVCMOS18, LVCMOS25, LVCMOS33LVTTL, LVCMOS18, LVCMOS25, LVCMOS33 DRIVE N/A4, 8, 1212SLEW N/A FAST, SLOW SLOWChapter 7: HD IOB ResourcesSSTLSSTL18_I is defined by the JEDEC standard JESD8-15, and is used for DDR2 SDRAM interfaces.For some topologies (such as short, point-to-point interfaces), the class-I driver can result in reduced overshoot and better signal integrity.HSTLThe high-speed transceiver logic (HSTL) HSTL_I_18 (1.8V) standard is a general-purpose high-speed bus standard as defined by the JEDEC standard JESD8-6.Table 109: Allowed Attributes for SSTL18_I and HSTL_I_18 I/O PrimitivesAttributesIBUF/IBUFE3OBUF/OBUFT IOBUF/IOBUFE3Allowed Values Default Allowed Value Default Allowed Values Default IOSTANDARDSSTL18_I, HSTL_I_18SSTL18_I, HSTL_I_18SSTL18_I, HSTL_I_18SLEWN/A FAST, SLOW SLOW FAST, SLOW SLOW ODT RTT_48,RTT_NONE RTT_NONE N/A RTT_48,RTT_NONERTT_NONE UNDEFINED Default IOSTANDARDWhen an IOSTANDARD is not defined by the user, the default assignment for the IOSTANDARD defaults to UNDEFINED. For a Versal ACAP design to complete implementation, a non-default IOSTANDARD must be defined with one of the valid I/O standards described in this section. The UNDEFINED standard acts as a placeholder to allow a design to complete the early stages or implementation.Single-Ended Input Buffer PrimitivesFigure 64: Single-Ended Input Buffer PrimitivesI OIBUFInput fromDevice Pad IBUF_INTERMDISABLEINTERMDISABLEOI Input fromDevice Pad IBUFDISABLEX21628-100720Table 110: IBUF and IBUF_INTERMDISABLE AttributesAttributeValues Description IOSTANDARDSee HD IOB Supported Standards Assigns an I/O standard to the E_IBUFDISABLE FALSE IBUFDISABLE is not supported in HD IOB and must be set to FALSE.(IBUF_INTERMDISABLE only)Table 111: IBUF and IBUF_INTERMDISABLE PortsPortI/O Description OOutput Buffer output representing the input path to the device.IInput Input port connection. Connect directly to top-level port in the design.IBUFDISABLE Input The IBUFDISABLE pin can disable the input buffer and force the O output to the internal logic to a logic High when the IBUFDISABLE signal is asserted High. (IBUF_INTERMDISABLE only)INTERMDISABLE InputIBUFDISABLE is not supported in HD IOB. (IBUF_INTERMDISABLE only)Single-Ended Bidirectional Buffer PrimitivesFigure 65: Single-Ended Bidirectional Buffer PrimitivesIOBUF_INTERMDISABLE IOIOBUFT I O IO X21629-092318Table 112: IOBUF, IOBUF_INTERMDISABLE AttributesAttributeValues Description DRIVE4, 8, 12Specifies the drive strength of the output.SLEWSLOW, FAST Specifies the slew rate of the output.IOSTANDARDSee HD IOB Supported Standards Assigns an I/O standard to the E_IBUFDISABLE FALSE IBUFDISABLE is not supported in HD IOB and must be set to FALSE.(IOBUF_INTERMDISABLE only)。