FPGA可编程逻辑器件芯片XCVU095-2FFVD1517E中文规格书
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FMC Connector JTAG Bypass
When an FMC is attached to the VCU108 board, it is automatically added to the JTAG chain through electronically controlled single-pole single-throw (SPST) switches U26 (HPC0) and U132 (HPC1). The SPST switches are in a normally closed state and transition to an open state when the FMC is attached. Switch U26 adds an attached HPC FMC to the FPGAs JTAG chain as determined by the FMC_HPC0_PRSNT_M2C_B signal. Switch U132 adds an attached
HPC FMC to the FPGAs JTAG chain as determined by the FMC_HPC1_PRSNT_M2C_B signal.
The JTAG connectivity on the VCU108 board allows a host computer to download bitstreams to the FPGA using the Xilinx tools. In addition, the JTAG connector allows debug tools such as the Vivado serial I/O analyzer or a software debugger to access the FPGA. The Xilinx tools can also program the BPI parallel flash memory.
Clock Generation
The VCU108 evaluation board provides twelve clock sources to the FPGA as listed in Table1-9.
Table 1-9:VCU108 Board Clock Sources
Clock Name Clock Reference
Description Description
System clock 300 MHz U122/U157Silicon Labs Si5335A 1.8V LVDS any frequency quad clock generator CLK0 drives U157 quad clock buffer. (SYSCLK1_300_P/N and SYSCLK2_300_P/N)
System clock 125 MHz U122Silicon Labs Si5335A 1.8V LVDS any frequency quad
clock generator CLK1. (CLK_125 MHz)
EMC clock 90 MHz U122Silicon Labs Si5335A 1.8V LVCMOS single-ended any frequency quad clock generator CLK2.
(FPGA_EMCCLK)
System control clock
33.333MHz U122Silicon Labs Si5335A 1.8V LVCMOS single-ended any frequency quad clock generator CLK3. (SYSCTLR_CLK)
User clock 10MHz-810MHz U32/U104Silicon Labs Si570 3.3V LVDS I2C programmable oscillator, 156.250 MHz default. U32 output Q0 drives U104 quad clock buffer. (USER_SI570_CLOCK_P/N and MGT_SI570_CLOCK1_P/N thru
MGT_SI570_CLOCK3_P/N)
Jitter attenuated clock U57Silicon Labs Si5328B LVDS precision clock multiplier/jitter attenuator. See Jitter Attenuated Clock (SI5328_OUT1_P and SI5328_OUT1_N).
Table 1-25:VCU108 Board FPGA U1 to CFP2 Module Connections
FPGA (U1) Pin Schematic Net
Name FPGA (U1)
Direction CFP2 Pin Number CFP2 Pin Name
AC40CFP2_TX9_X_P Output3TX9_P AC41CFP2_TX9_X_N Output2TX9_N AA40CFP2_TX8_X_P Output6TX8_P AA41CFP2_TX8_X_N Output5TX8_N W40CFP2_TX7_X_P Output102TX7_P W41CFP2_TX7_X_N Output103TX7_N T42CFP2_TX6_3_P Output99TX6_P T43CFP2_TX6_3_N Output100TX6_N P42CFP2_TX5_2_P Output96TX5_P P43CFP2_TX5_2_N Output97TX5_N U40CFP2_TX4_X_P Output93TX4_P U41CFP2_TX4_X_N Output94TX4_N
Table 1-29 lists the HDMI Codec U52 to the XCVU095 device U1 connections. All HDMI nets in this table are series resistor coupled.
For more information about the Analog Devices ADV7511KSTZ-P, see the Analog Devices website [Ref 21]. For additional information about HDMI IP options, see the DisplayPort LogiCORE IP Product Guide (PG064) [Ref 22].
Table 1-29:HDMI Codec U52 to XCVU095 Device U1 Connections
FPGA (U1)
Pin
Schematic Net
Name
FPGA (U1) Direction
I/O Standard
ADV7511 U52Pin Number
Name
R36HDMI_D0Output LVCMOS1888D8R34HDMI_D1Output LVCMOS1887D9P34HDMI_D2Output LVCMOS1886D10V30HDMI_D3Output LVCMOS1885D11V33HDMI_D4Output LVCMOS1884D12V34HDMI_D5Output LVCMOS1883D13U35HDMI_D6Output LVCMOS1882D14T36HDMI_D7Output LVCMOS1881D15Y34HDMI_D8Output LVCMOS1880D16W34HDMI_D9Output LVCMOS1878D17V32HDMI_D10Output LVCMOS1874D18U33HDMI_D11Output LVCMOS1873D19AH33HDMI_D12Output LVCMOS1872D20AH30HDMI_D13Output LVCMOS1871D21AM33HDMI_D14Output LVCMOS1870D22AM31HDMI_D15Output LVCMOS1869D23AH34HDMI_DE Output LVCMOS1897DE AJ35HDMI_SPDIF Output LVCMOS1810SPDIF AK33HDMI_CLK Output LVCMOS1879CLK AK30HDMI_VSYNC Output LVCMOS182VSYNC AK29HDMI_HSYNC Output LVCMOS1898HSYNC AJ33HDMI_INT Input LVCMOS1845INT AJ36
HDMI_SPDIF_OUT
Input
LVCMOS18
46
SPDIF_OUT。
