FPGA可编程逻辑器件芯片XC5VSX50T-2FFG1136I中文规格书

Virtex-5 FPGA Electrical CharacteristicsVirtex®-5 FPGAs are available in -3, -2, -1 speed grades, with -3 having the highest performance. Virtex-5 FPGA DC and AC characteristics are specified for both commercial and industrial grades. Except the operating temperature range or unless otherwise noted, all the DC and ACelectrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1 speed grade industrial device are the same as for a -1 speed grade commercial device). However, only selected speed grades and/or devices might be available in the industrial range.All supply voltage and junction temperature specifications are representative of worst-case conditions. Theparameters included are common to popular designs and typical applications.This Virtex-5 FPGA data sheet, part of an overall set of documentation on the Virtex-5 family of FPGAs, is available on the Xilinx website:•Virtex-5 Family Overview •Virtex-5 FPGA User Guide•Virtex-5 FPGA Configuration Guide•Virtex-5 FPGA XtremeDSP™ Design Considerations •Virtex-5 FPGA Packaging and Pinout Specification•Embedded Processor Block in Virtex-5 FPGAs Reference Guide•Virtex-5 FPGA RocketIO™ GTP Transceiver User Guide •Virtex-5 FPGA RocketIO GTX Transceiver User Guide •Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC User Guide•Virtex-5 FPGA Integrated Endpoint Block User Guide for PCI Express® Designs•Virtex-5 FPGA System Monitor User Guide •Virtex-5 FPGA PCB Designer’s GuideAll specifications are subject to change without notice.DS202 (v5.5) June 17, 2016Product Specification找FPGA 和CPLD可编程逻辑器件，上深圳宇航军工半导体有限公司Dedicated Arithmetic LogicDSP48E Quad 12-bit Adder/Subtracter550500450MHz DSP48E Dual 24-bit Adder/Subtracter550500450MHz DSP48E 48-bit Adder/Subtracter550500450MHz DSP48E 48-bit Counter550500450MHz DSP48E 48-bit Comparator550500450MHz DSP48E 25x18 bit Pipelined Multiplier550500450MHz DSP48E Direct 4-tap FIR Filter Pipelined510458397MHz DSP48E Systolic n-tap FIR Filter Pipelined550500450MHzI/O Standard Adjustment Measurement MethodologyInput Delay MeasurementsTable58 shows the test setup parameters used for measuring input delay.Table 58:Input Delay Measurement MethodologyDescription I/O Standard Attribute V L(1,2)V H(1,2)V MEAS(1,4,5)V REF(1,3,5) LVTTL (Low-Voltage Transistor-Transistor Logic)LVTTL0 3.0 1.4–LVCMOS (Low-Voltage CMOS), 3.3V LVCMOS330 3.3 1.65–LVCMOS, 2.5V LVCMOS250 2.5 1.25–LVCMOS, 1.8V LVCMOS180 1.80.9–LVCMOS, 1.5V LVCMOS150 1.50.75–LVCMOS, 1.2V LVCMOS120 1.20.6–PCI (Peripheral Component Interconnect),PCI33_3Per PCI™ Specification–33 MHz, 3.3VPCI, 66 MHz, 3.3V PCI66_3Per PCI Specification–PCI-X, 133 MHz, 3.3V PCIX Per PCI-X™ Specification–GTL (Gunning Transceiver Logic)GTL V REF–0.2V REF+0.2V REF0.80 GTL Plus GTLP V REF–0.2V REF+0.2V REF 1.0 HSTL (High-Speed Transceiver Logic),HSTL_I, HSTL_II V REF–0.5V REF+0.5V REF0.75 Class I & IIHSTL, Class III & IV HSTL_III, HSTL_IV V REF–0.5V REF+0.5V REF0.90 HSTL, Class I & II, 1.8V HSTL_I_18, HSTL_II_18V REF–0.5V REF+0.5V REF0.90 HSTL, Class III & IV, 1.8V HSTL_III_18, HSTL_IV_18V REF–0.5V REF+0.5V REF 1.08 SSTL (Stub Terminated Transceiver Logic),SSTL3_I,SSTL3_II V REF–1.00V REF+1.00V REF 1.5 Class I & II, 3.3VSSTL, Class I & II, 2.5V SSTL2_I,SSTL2_II V REF–0.75V REF+0.75V REF 1.25 SSTL, Class I & II, 1.8V SSTL18_I,SSTL18_II V REF–0.5V REF+0.5V REF0.90 AGP-2X/AGP (Accelerated Graphics Port)AGP V REF–(0.2xV CCO)V REF+(0.2xV CCO)V REF AGP Spec LVDS (Low-Voltage Differential Signaling), 2.5V LVDS_25 1.2–0.125 1.2+0.1250(6)LVDSEXT (LVDS Extended Mode), 2.5V LVDSEXT_25 1.2–0.125 1.2+0.1250(6)LDT (HyperTransport), 2.5V LDT_250.6–0.1250.6+0.1250(6)LVPECL_25 1.15–0.3 1.15–0.30(6)LVPECL (Low-Voltage Positive Emitter-CoupledLogic), 2.5VNotes:1.The input delay measurement methodology parameters for LVDCI are the same for LVCMOS standards of the same voltage. Input delaymeasurement methodology parameters for HSLVDCI are the same as for HSTL_II standards of the same voltage. Parameters for all other DCI standards are the same for the corresponding non-DCI standards.2.Input waveform switches between V L and V H.3.Measurements are made at typical, minimum, and maximum V REF values. Reported delays reflect worst case of these measurements. V REF valueslisted are typical.4.Input voltage level from which measurement starts.5.This is an input voltage reference that bears no relation to the V REF / V MEAS parameters found in IBIS models and/or noted in Figure11.6.The value given is the differential input voltage.HSTL, Class IV HSTL_IV 2500.9 1.5HSTL, Class I, 1.8V HSTL_I_18500V REF 0.9HSTL, Class II, 1.8V HSTL_II_18250V REF 0.9HSTL, Class III, 1.8V HSTL_III_18500 1.1 1.8HSTL, Class IV, 1.8VHSTL_IV_18250 1.1 1.8SSTL (Stub Series Terminated Logic), Class I, 1.8V SSTL18_I 500V REF 0.9SSTL, Class II, 1.8V SSTL18_II 250V REF 0.9SSTL, Class I, 2.5V SSTL2_I 500V REF 1.25SSTL, Class II, 2.5VSSTL2_II 250V REF 1.25LVDS (Low-Voltage Differential Signaling), 2.5V LVDS_2510000(4) 1.2LVDSEXT (LVDS Extended Mode), 2.5V LVDS_2510000(4) 1.2BLVDS (Bus LVDS), 2.5V BLVDS_2510000(4)0LDT (HyperTransport), 2.5VLDT_2510000(4)0.6LVPECL (Low-Voltage Positive Emitter-Coupled Logic), 2.5VLVPECL_2510000(4)0LVDCI/HSLVDCI(Low-Voltage Digitally Controlled Impedance), 3.3V LVDCI_33, HSLVDCI_331M 0 1.650LVDCI/HSLVDCI, 2.5V LVDCI_25, HSLVDCI_251M 0 1.250LVDCI/HSLVDCI, 1.8V LVDCI_18, HSLVDCI_181M 00.90LVDCI/HSLVDCI, 1.5V LVDCI_15, HSLVDCI_151M 00.750HSTL (High-Speed Transceiver Logic), Class I & II, with DCI HSTL_I_DCI, HSTL_II_DCI500V REF 0.75HSTL, Class III & IV, with DCI HSTL_III_DCI, HSTL_IV_DCI 5000.9 1.5HSTL, Class I & II, 1.8V, with DCI HSTL_I_DCI_18, HSTL_II_DCI_18500V REF 0.9HSTL, Class III & IV, 1.8V, with DCIHSTL_III_DCI_18, HSTL_IV_DCI_18500 1.1 1.8SSTL (Stub Series Termi.Logic), Class I & II, 1.8V, with DCI SSTL18_I_DCI, SSTL18_II_DCI 500V REF 0.9SSTL, Class I & II, 2.5V, with DCISSTL2_I_DCI, SSTL2_II_DCI 500V REF 1.25GTL (Gunning Transceiver Logic) with DCI GTL_DCI 5000.8 1.2GTL Plus with DCI GTLP_DCI501.01.5Notes:1.C REF is the capacitance of the probe, nominally 0 pF.2.Per PCI specifications.3.Per PCI-X specifications.4.The value given is the differential input voltage.Table 59:Output Delay Measurement Methodology (Cont’d)DescriptionI/O Standard Attribute R REF (Ω)C REF (1)(pF)V MEAS (V)V REF (V)。

Symbol DescriptionSpeed GradeUnits -2I-1I-1MSequential DelaysT REG Clock to A–D outputs 1.43 1.73 1.73ns, Max T REG_MUX Clock to AMUX–DMUX output 1.55 1.87 1.87ns, Max T REG_M31Clock to DMUX output via M31 output 1.15 1.38 1.38ns, Max Setup and Hold Times Before/After Clock CLKT WS/T WH WE input0.24–0.040.29–0.020.29–0.02ns, MinT CECK/T CKCE CE input to CLK0.27–0.070.33–0.060.33–0.06ns, MinT DS/T DH A–D inputs to CLK 0.660.090.780.110.780.11ns, MinClock CLKT MPW Minimum pulse width0.700.850.85ns, MinNotes:1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if a “0” islisted, there is no positive hold time.DSP48E Switching CharacteristicsMaximum Frequency F MAXBlock RAM in all modes500450450MHz F MAX_CASCADE Block RAM in cascade configuration 450400400MHz F MAX_FIFO FIFO in all modes500450450MHz F MAX_ECC Block RAM and FIFO in ECC configuration375325325MHzNotes:1.TRACE will report all of these parameters as T RCKO_DO .2.T RCKO_DOR includes T RCKO_DOW , T RCKO_DOPR , and T RCKO_DOPW as well as the B port equivalent timing parameters.3.These parameters also apply to synchronous FIFO with DO_REG =0.4.T RCKO_DO includes T RCKO_DOP as well as the B port equivalent timing parameters.5.These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG =1.6.T RCKO_FLAGS includes the following parameters: T RCKO_AEMPTY , T RCKO_AFULL , T RCKO_EMPTY , T RCKO_FULL , T RCKO_RDERR , T RCKO_WRERR .7.T RCKO_POINTERS includes both T RCKO_RDCOUNT and T RCKO_WRCOUNT .8.The ADDR setup and hold must be met when EN is asserted even though WE is deasserted. Otherwise, block RAM data corruption is possible.9.T RCKO_DI includes both A and B inputs as well as the parity inputs of A and B.10.These parameters also apply to RDEN.11.T RCO_FLAGS includes the following flags: AEMPTY , AFULL, EMPTY , FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT .Table 69:DSP48E Switching CharacteristicsSymbolDescriptionSpeed Grade Units-2I -1I -1M Setup and Hold Times of Data/Control Pins to the Input Register Clock TDSPDCK_{AA, BB, ACINA, BCINB}/TDSPCKD_{AA, BB, ACINA, BCINB}{A, B, ACIN, BCIN} input to {A, B} register CLK 0.210.230.260.300.260.30ns TDSPDCK_CC/TDSPCKD_CCC input to C register CLK0.160.310.200.370.200.50nsSetup and Hold Times of Data Pins to the Pipeline Register Clock TDSPDCK_{AM, BM, ACINM, BCINM}/TDSPCKD_{AM, BM, ACINM, BCINM}{A, B, ACIN, BCIN} input to M register CLK1.440.191.710.191.710.19nsSetup and Hold Times of Data/Control Pins to the Output Register Clock TDSPDCK_{AP , BP , ACINP , BCINP}_M/TDSPCKD_{AP , BP , ACINP , BCINP}_M {A, B, ACIN, BCIN} input to P register CLK using multiplier2.74–0.303.25–0.30 3.25–0.30ns TDSPDCK_{AP , BP , ACINP , BCINP}_NM/TDSPCKD_{AP , BP , ACINP , BCINP}_NM {A, B, ACIN, BCIN} input to P register CLK not using multiplier1.54–0.10 1.83–0.10 1.83–0.10ns TDSPDCK_CP/TDSPCKD_CP C input to P register CLK1.42–0.13 1.70–0.13 1.70–0.13ns TDSPDCK_{PCINP , CRYCINP , MULTSIGNINP}/TDSPCKD_{PCINP , CRYCINP , MULTSIGNINP}{PCIN, CARRYCASCIN, MULTSIGNIN} input to P register CLK1.170.111.310.111.310.11nsSetup and Hold Times of the CE PinsTDSPCCK_{CEA1A, CEA2A, CEB1B,CEB2B}/TDSPCKC_{CEA1A, CEA2A, CEB1A, CEB2B}{CEA1, CEA2A, CEB1B, CEB2B} input to {A,B} register CLK 0.280.250.330.310.330.31nsTDSPCCK_CECC/TDSPCKC_CECC CEC input to C register CLK 0.210.210.260.280.260.28ns TDSPCCK_CEMM/TDSPCKC_CEMMCEM input to M register CLK0.290.210.360.260.360.26nsTable 68:Block RAM and FIFO Switching Characteristics (Cont’d)SymbolDescriptionSpeed Grade Units-2I -1I -1MPLL Switching Characteristics Table 74:PLL SpecificationSymbol DescriptionSpeed GradeUnits -2I-1I-1MF INMAX Maximum Input Clock Frequency710645645MHz F INMIN Minimum Input Clock Frequency191919MHz F INJITTER Maximum Input Clock Period Jitter<20% of clock input period or 1ns Max F INDUTY Allowable Input Duty Cycle: 19—49MHz25/75%Allowable Input Duty Cycle: 50—199MHz30/70%Allowable Input Duty Cycle: 200—399MHz35/65%Allowable Input Duty Cycle: 400—499MHz40/60%Allowable Input Duty Cycle: >500MHz45/55% F VCOMIN Minimum PLL VCO Frequency400400400MHz F VCOMAX Maximum PLL VCO Frequency120010001000MHzF BANDWIDTH Low PLL Bandwidth at T ypical(1)111MHz High PLL Bandwidth at Typical(1)444MHzT ST APHAOFFSET Static Phase Offset of the PLL Outputs120120120ps T OUTJITTER PLL Output Jitter(2)Note 1T OUTDUTY PLL Output Clock Duty Cycle Precision(3)±200±200±200ps T LOCKMAX PLL Maximum Lock Time(4)100100100µs F OUTMAX PLL Maximum Output Frequency for LX30T, LX85, LX110,LX110T, SX50T, and FX70T(I) devices667600N/A MHzPLL Maximum Output Frequency for LX155T, FX70T(M), andFX100T devices600550550MHz PLL Maximum Output Frequency for FX130T devices500450N/A MHzPLL Maximum Output Frequency for LX220T, LX330T, SX95T,SX240T, and FX200T devices500450N/A MHz F OUTMIN PLL Minimum Output Frequency(5) 3.125 3.125 3.125MHz T EXTFDVAR External Clock Feedback Variation<20% of clock input period or 1ns Max RST MINPULSE Minimum Reset Pulse Width555ns F PFDMAX Maximum Frequency at the Phase Frequency Detector500450450MHz F PFDMIN Minimum Frequency at the Phase Frequency Detector191919MHz T FBDELAY Maximum Delay in the Feedback Path3ns Max or one CLKIN cycle Notes:1.The PLL does not filter typical spread spectrum input clocks because they are usually far below the bandwidth filter frequencies.2.Values for this parameter are available in the Architecture Wizard.3.Includes global clock buffer.4.The LOCK signal must be sampled after T LOCKMAX. The LOCK signal is invalid after configuration or reset until the T LOCKMAX time hasexpired.5.Calculated as F VCO/128 assuming output duty cycle is 50%.。

FPGA RX InterfaceOverviewThe FPGA receives RX data from the GTX receiver through the FPGA RX interface. Data is read from the RXDATA port on the positive edge of RXUSRCLK2.The width of RXDATA can be configured to be one or two bytes wide. The actual width of the port depends on the internal data width of the GTX_DUAL tile, and whether or not the 8B/10B decoder is enabled. Ports widths of 8 bits, 10 bits, 16 bits, 20 bits, 32 bits, and 40 bits are possible.The rate of the parallel clock (RXUSRCLK2) at the interface is determined by the RX line rate, the width of the RXDATA port, and whether or not 8B/10B decoding is enabled. RXUSRCLK must be provided for the internal PCS logic in the receiver. This section shows how to drive the parallel clocks and explains the constraints on those clocks for correct operation.Ports and AttributesPortDirClock DomainDescriptionINT D ATAWI D TH InAsyncS pecifies the bit width for the TX and RX paths. The bit width of TX and RXmust be identical for both channels.0: 16-bit width 1: 20-bit widthREFCLKOUT Out N/AThe REFCLKOUT port from each GTX_DUAL tile provides access to thereference clock provided to the shared PMA PLL (CLKIN). It can be routed for use in the FPGA logic.RXDATA0[31:0]RXDATA1[31:0]Out RXUSRCLK2Receive data bus of the receive interface to the FPGA. The width of RXDATA(0/1) depends on the setting of RXDATAWIDTH(0/1).RXDATAWIDTH0RXDATAWIDTH1InRXUSRCLK2Selects the width of the RXDATA(0/1) receive data connection to the FPGA.0: One-byte interface => RXDATA(0/1)[7:0]1: Two-byte interface => RXDATA(0/1)[15:0]2: Four-byte interface => RXDATA(0/1)[31:0]The clock domain depends on the selected clock (RXRECCLK(0/1), RXUSRCLK(0/1), and RXUSRCLK2(0/1)) for this interface.RXRECCLK0RXRECCLK1Out N/ARecovered clock from the CDR. Clocks the RX logic between the PMA and the RX elastic buffer. Can be used to drive RXUSRCLK synchronously with incoming data.When RXPOWERDOWN[1:0] is set to 11, which is P2 the lowest power state, then RXRECCLK of this transceiver is indeterminate. RXRECCLK of this GTX transceiver is either a static 1 or a static 0.RXRESET0RXRESET1In AsyncPCS RX system reset. Resets the RX elastic buffer, 8B/10B decoder, comma detect, and other RX registers. This is a per channel subset of GTXRESET.FPGA RX InterfaceThere are no attributes in this section.DescriptionThe FPGA RX interface allows parallel received data to be read from the GTX transceiver. For this interface to be used, the following must be done: •The width of the RXDATA port must be configured•RXUSRCLK2 and RXUSRCLK must be connected to clocks running at the correct rate.Configuring the Width of the InterfaceTable 7-44 shows how to select the interface width for the RX datapath. 8B/10B decoding is discussed in more detail in “Configurable 8B/10B Decoder,” page 200.RXUSRCLK0RXUSRCLK1In N/AThis port provides a clock for the internal RX PCS datapath. This clock must always be provided. The rate depends on INTDATAWIDTH where:INTDATAWIDTH is Low; F RXUSRCLK = Line Rate/16INTDATAWIDTH is High; F RXUSRCLK = Line Rate/20RXUSRCLK20RXUSRCLK21In N/AThis port synchronizes the FPGA logic with the RX interface. This clock must be positive-edge aligned to RXUSRCLK. The clock rate depends on F RXUSRCLK and RXDATAWIDTH:RXDATAWIDTH =0; F RXUSRCLK2=2x F RXUSRCLK RXDATAWIDTH =1; F RXUSRCLK2=F RXUSRCLK RXDATAWIDTH =2; F RXUSRCLK2=F RXUSRCLK /2Table 7-43:FPGA RX Interface Ports (Cont’d)PortDirClock DomainDescriptionTable 7-44:RX Datapath Width ConfigurationINTDATAWIDTH (1)RXDATAWIDTH (2)RXDEC8B10BUSEFPGA RX Interface Width(bits)00N/A 801N/A 1602N/A 3210010110201204010181111612132Notes:1.The internal datapath is 16 bits when INTDATAWIDTH is Low and 20 bits when INTDATAWIDTH is High.2.The RXDATA interface is one byte wide when RXDATAWIDTH = 0, two bytes wide when RXDATAWIDTH = 1, and four bytes when RXDATAWIDTH = 2.Chapter 7:GTX Receiver (RX)Figure7-42 shows how RXDATA is received serially when the internal datapath is 16bits(INTDATAWIDTH is Low) and 8B/10B decoding is disabled.Figure 7-42:RX Interface with 8B/10B Bypassed (16-Bit Internal Datapath)Figure7-43 shows how RXDATA is received serially when the internal datapath is 20 bits(INTDATAWIDTH is High) and 8B/10B decoding is disabled. When RXDATA is 10 bits or20bits wide, the RXDISPERR and RXCHARISK ports are taken from the 8B/10B decoderinterface and are used to present the extra bits.Figure 7-43:RX Interface with 8B/10B Bypassed (20-Bit Internal Datapath)DescriptionUsing the CRC BlocksFigure8-3 shows a CRC block calculating the CRC for input data. Also shown in this figureis the CRC32 primitive. This operation is performed when the CRC is being generated orchecked. CRC_POLY is the fixed CRC32 polynomial used for all calculations.Figure 8-3:CRC Block TimingAt the start of each frame, CRCRESET must be applied to set the initial CRC value toCRC_INIT. CRC calculations are cumulative, so this step is required to start the CRCcalculation at a known value. CRC_INIT is a 32-bit value for the initial state of the CRCinternal register. Its default value is 0xFFFFFFFF. When CRCRESET is driven Low, on thefirst cycle the CRC block outputs 0x00000000 on the CRCOUT port. The following cycleswill have the calculated CRC value for the data on the CRCIN port. The CRC_INIT valuerequired for a given protocol is specified as part of that protocol’s CRC algorithm. Table8-6shows the CRC_INIT values for some common protocols that use the CRC32 polynomial.Table 8-6:CRC_INIT Values for Some Common ProtocolsProtocol CRC_INITEthernet32’hFFFF_FFFFPCI Express32’hFFFF_FFFFInfiniband32’hFFFF_FFFFFibre Channel32’hFFFF_FFFFSATA32’h5232_5032Chapter 8:Cyclic Redundancy Check。

© 2006–2010, 2014, 2016 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PowerPC is a trademark of IBM Corp. and is used under license. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property of their respective owners.Virtex-5 FPGA Electrical CharacteristicsVirtex®-5 FPGAs are available in -3, -2, -1 speed grades, with -3 having the highest performance. Virtex-5 FPGA DC and AC characteristics are specified for both commercial and industrial grades. Except the operating temperature range or unless otherwise noted, all the DC and ACelectrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1 speed grade industrial device are the same as for a -1 speed grade commercial device). However, only selected speed grades and/or devices might be available in the industrial range.All supply voltage and junction temperature specifications are representative of worst-case conditions. Theparameters included are common to popular designs and typical applications.This Virtex-5 FPGA data sheet, part of an overall set of documentation on the Virtex-5 family of FPGAs, is available on the Xilinx website:•Virtex-5 Family Overview •Virtex-5 FPGA User Guide•Virtex-5 FPGA Configuration Guide•Virtex-5 FPGA XtremeDSP™ Design Considerations •Virtex-5 FPGA Packaging and Pinout Specification•Embedded Processor Block in Virtex-5 FPGAs Reference Guide•Virtex-5 FPGA RocketIO™ GTP Transceiver User Guide •Virtex-5 FPGA RocketIO GTX Transceiver User Guide •Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC User Guide•Virtex-5 FPGA Integrated Endpoint Block User Guide for PCI Express® Designs•Virtex-5 FPGA System Monitor User Guide •Virtex-5 FPGA PCB Designer’s GuideAll specifications are subject to change without notice.Virtex-5 FPGA DC CharacteristicsProduct SpecificationTable 1:Absolute Maximum RatingsSymbol DescriptionUnits V CCINT Internal supply voltage relative to GND –0.5 to 1.1V V CCAUX Auxiliary supply voltage relative to GND–0.5 to 3.0V V CCO Output drivers supply voltage relative to GND –0.5 to 3.75V V BATT Key memory battery backup supply –0.5 to 4.05V V REFInput reference voltage–0.5 to 3.75V V IN (3)3.3V I/O input voltage relative to GND (4) (user and dedicated I/Os)–0.75 to 4.05V 3.3V I/O input voltage relative to GND (restricted to maximum of 100 user I/Os)(5)–0.95 to 4.4(Commercial Temperature)V –0.85 to 4.3(Industrial Temperature)2.5V or below I/O input voltage relative to GND (user and dedicated I/Os)–0.75 to V CCO +0.5V I IN Current applied to an I/O pin, powered or unpowered±100mA Total current applied to all I/O pins, powered or unpowered±100mA V TS Voltage applied to 3-state 3.3V output (4) (user and dedicated I/Os)–0.75 to 4.05V Voltage applied to 3-state 2.5V or below output (user and dedicated I/Os)–0.75 to V CCO +0.5V T STG Storage temperature (ambient)–65to 150°C T SOL Maximum soldering temperature (2)+220°C T JMaximum junction temperature (2)+125°CNotes:1.Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.2.For soldering guidelines, refer to UG112: Device Package User Guide . For thermal considerations, refer to UG195: Virtex-5 FPGA Packaging andPinout Specification on the Xilinx website.3. 3.3V I/O absolute maximum limit applied to DC and AC signals.4.For 3.3V I/O operation, refer to UG190: Virtex-5 FPGA User Guide, Chapter 6, 3.3V I/O Design Guidelines .5.For more flexibility in specific designs, a maximum of 100 user I/Os can be stressed beyond the normal specification for no more than 20% of a data period .找FPGA和CPLD可编程逻辑器件，上深圳宇航军工半导体有限公司DS202 (v5.5) June 17, 2016Table 2:Recommended Operating ConditionsSymbol DescriptionTemperature RangeMin Max Units V CCINT Internal supply voltage relative to GND, T J =0°C to +85°C Commercial 0.95 1.05V Internal supply voltage relative to GND, T J =–40°C to +100°C Industrial 0.95 1.05V V CCAUX (1)Auxiliary supply voltage relative to GND, T J =0°C to +85°C Commercial 2.375 2.625V Auxiliary supply voltage relative to GND, T J =–40°C to +100°C Industrial 2.375 2.625V V CCO (2,4,5)Supply voltage relative to GND, T J =0°C to +85°C Commercial 1.14 3.45V Supply voltage relative to GND, T J =–40°C to +100°C Industrial 1.14 3.45V V IN3.3V supply voltage relative to GND, T J =0°C to +85°C Commercial GND –0.20 3.45V 3.3V supply voltage relative to GND, T J =–40°C to +100°C Industrial GND –0.20 3.45V 2.5V and below supply voltage relative to GND, T J =0°C to +85°CCommercial GND –0.20V CCO +0.2V 2.5V and below supply voltage relative to GND, T J =–40°C to +100°CIndustrial GND –0.20V CCO +0.2V I IN (6)Maximum current through any pin in a powered or unpowered bank when forward biasing the clamp diode Commercial 10mA Industrial 10mA V BATT (3)Battery voltage relative to GND, T J =0°C to +85°C Commercial 1.0 3.6V Battery voltage relative to GND, T J =–40°C to +100°CIndustrial1.03.6VGTX_DUAL Tile SpecificationsGTX_DUAL Tile DC CharacteristicsTable 36:Absolute Maximum Ratings for GTX_DUAL TilesSymbol Description Units MGTAVCCPLL Analog supply voltage for the GTX_DUAL shared PLL relative to GND–0.5 to 1.1V MGTAVTTTX Analog supply voltage for the GTX_DUAL transmitters relative to GND–0.5 to 1.32V MGTAVTTRX Analog supply voltage for the GTX_DUAL receivers relative to GND–0.5 to 1.32V MGTAVCC Analog supply voltage for the GTX_DUAL common circuits relative to GND–0.5 to 1.1V–0.5 to 1.32V MGTAVTTRXC Analog supply voltage for the resistor calibration circuit of the GTX_DUALcolumnSystem Monitor Analog-to-Digital Converter SpecificationTable 51:Analog-to-Digital SpecificationsParameter Symbol Comments/Conditions Min Typ Max UnitsAV DD=2.5V±2%, V REFP=2.5V,V REFN=0V, ADCCLK=5.2MHz, T A=T MIN to T MAX, Typical values at T A=+25°CDC Accuracy: All external input channels such as V P/V N and V AUXP[15:0]/V AUXN[15:0], Unipolar Mode,and Common Mode = 0VResolution10Bits Integral Nonlinearity INL±2LSBsDifferential Nonlinearity DNL No missing codes (T MIN to T MAX)Guaranteed Monotonic±0.9LSBs Unipolar Offset Error(1)Uncalibrated±2±30LSBs Bipolar Offset Error(1)Uncalibrated measured in bipolar mode ±2±30LSBs Gain Error(1)Uncalibrated±0.2±2% Bipolar Gain Error(1)Uncalibrated measured in bipolar mode±0.2±2%Total Unadjusted Error (Uncalibrated)TUE Deviation from ideal transfer function.V REFP–V REFN=2.5V±10LSBsTotal Unadjusted Error (Calibrated)TUE Deviation from ideal transfer function.V REFP–V REFN=2.5V±1±2LSBsCalibrated Gain TemperatureCoefficientVariation of FS code with temperature±0.01LSB/°CDC Common-Mode Reject CMRR DC V N = V CM=0.5V± 0.5V,V P–V N=100mV70dB Conversion Rate(2)Conversion Time - Continuous t CONV Number of CLK cycles2632Conversion Time - Event t CONV Number of CLK cycles21T/H Acquisition Time t ACQ Number of CLK cycles4DRP Clock Frequency DCLK DRP clock frequency8250MHz ADC Clock Frequency ADCCLK Derived from DCLK1 5.2MHz CLK Duty cycle4060% Analog Inputs(3)Dedicated Analog Inputs Input Voltage RangeV P - V N Unipolar Operation01Volts Differential Inputs–0.25+0.25Unipolar Common Mode Range (FS input)0+0.5 Differential Common Mode Range (FS input) +0.3+0.7 Bandwidth20MHzAuxiliary Analog InputsInput Voltage RangeV AUXP[0] /V AUXN[0] to V AUXP[15] /V AUXN[15]Unipolar Operation01Volts Differential Operation–0.25+0.25Unipolar Common Mode Range (FS input)0+0.5 Differential Common Mode Range (FS input)+0.3+0.7 Bandwidth10kHzInput Leakage Current A/D not converting, ADCCLK stopped±1.0µA Input Capacitance10pFOn-chip Supply Monitor Error V CCINT and V CCAUX with calibration enabled±1.0% Reading On-chip Temperature MonitorError–40°C to +125°C with calibration enabled±4°C。