FPGA可编程逻辑器件芯片XC2S1200E-4FGG320I中文规格书

Table 24: Recommended Receiver Resets for Common SituationsSituation Components tobe ResetRecommended RX Reset Setting RXRESETMODE RXPMARESETMASK RXPCSRESETMASKAfter power up and confirmation RPLL, LCPLL, ILO,Entire RX2'b007'b11111115'b11111After turning on a reference clock to the LCPLL/RPLL being used RPLL, LCPLL, ILO,Entire RX2'b007'b11111115'b11111After changing the reference clock to the LCPLL/RPLL being used RPLL, LCPLL, ILO,Entire RX2'b007'b11111115'b11111After assertion/deassertion of LCPLLPD or RPLLPD for the PLL being used RPLL, LCPLL, ILO,Entire RX2'b007'b11111115'b11111After assertion/deassertion of RXPD[1:0]Entire RX2'b007'b11111115'b11111RX rate change RX PMA and RXPCS2'b007'b11111005'b11111 RX parallel clock source reset RX PCS2'b007'b00000005'b11111 After remote power up Entire RX2'b007'b11111115'b11111 Electrical Idle Entire RX2'b007'b11111115'b11111 After connecting RXN/RXP Entire RX2'b007'b11111115'b11111After recovered clock becomes stable RX Elastic Buffer2'b117'b00000005'b00100After RX elastic buffer error RX Elastic Buffer2'b117'b00000005'b00100After changing channel bonding mode in real time RX Elastic Buffer2'b117'b00000005'b00100After PRBS error PRBS ErrorCounter2'b117'b00000005'b00010 After comma alignment RX Elastic Buffer2'b117'b00000005'b00100 Eye Scan reset only Eye Scan2'b117'b00000005'b01000 After Power-up and ConfigurationThe PLL being used and the entire RX require a reset after configuration. See Transceiver RX Reset in Response to Completion of Configuration.After Turning on a Reference Clock to the LCPLL/RPLL Being Used If the reference clock(s) changes or transceiver(s) are powered up after configuration, perform a full RX sequential reset after the PLL fully completes its reset procedure.After Changing the Reference Clock to the LCPLL/RPLL Being Used Whenever the reference clock input to the PLL is changed, the PLL must be reset afterward to ensure that it locks to the new frequency. Perform a full RX sequential reset after the PLL fully completes its reset procedure.After Assertion/Deassertion of LC/RPLLPD for the PLL Being Used When the LCPLL or RPLL being used goes back to normal operation after power down, the PLL must be reset. Perform a full RX sequential reset after the PLL fully completes its reset procedure.After Assertion/Deassertion of RXPD[1:0]After the RXPD signal is deasserted, perform a full RX sequential reset.RX Rate ChangeWhen a rate change is performed using the RXRATE port, the required reset sequence is performed automatically. When RXRESETDONE is asserted, it indicates that both a rate change and then a necessary reset sequence have been applied and completed.RX Parallel Clock Source ResetThe clocks driving RXUSRCLK must be stable for correct operation. Perform an RX PCS reset after the clock source re-locks.After Remote Power-UpIf the source of incoming data is powered up after the transceiver that is receiving its data has begun operating, a full RX sequential reset must be performed to ensure a clean lock to the incoming data.Electrical Idle ResetFor protocols that support OOB and electrical idle, when the differential voltage of the RX input to the transceiver drops to OOB or electrical idle levels, the RX CDR is managed automatically when the attributes associated with electrical idle are set to appropriate values. Use the recommended values from the Wizard.Chapter 2: Shared FeaturesAfter Connecting RXN/RXPWhen the RX data to the transceiver comes from a connector that can be plugged in and unplugged, a full RX sequential reset must be performed when the data source is plugged in to ensure that it can lock to incoming data.After Recovered Clock Becomes StableDepending on the design of the clocking scheme, it is possible for the RX reset sequence to be completed before the CDR is locked to the incoming data. In this case, the recovered clock might not be stable when RXRESETDONE is asserted. When the RX PCS is used, a single mode reset targeting the RX elastic buffer must be triggered after the recovered clock becomes stable. When RX buffer bypass is used, the alignment procedure should not start until the recovered clock becomes stable.Refer to the Versal ACAP data sheets for successful CDR lock-to-data criteria.After an RX Elastic Buffer ErrorAfter an RX elastic buffer overflow or underflow, a single mode reset targeting the RX elastic buffer must be triggered to ensure correct behavior.After Changing Channel Bonding Mode During Run TimeWhen set to TRUE, RXBUF_RESET_ON_CB_CHANGE enables automatic reset of the RX elastic buffer when EB8B10B_CHAN_BOND_MASTER, EB8B10B_CHAN_BOND_SLAVE, orEB8B10B_CHAN_BOND_LEVEL change. *naming may still change*After a PRBS ErrorPRBSCNTRESET is asserted to reset the PRBS error counter.After Comma RealignmentWhen set to TRUE, EB8B10B_RESET_ON_COMMAALIGN enables automatic reset of the RX elastic buffer during comma realignment.Transceiver Master ResetA master reset controller is available in GTY and GTYP transceivers. The master reset controller automatically steps through the reset of the LCPLL, RPLL, ILO, TX programmable divider, RX programmable divider, TX channel, and RX channel. The master reset controller state machine operates as shown in Figure 23 for the TX and Figure 24 for the RX.。

Revision HistoryThe following table shows the revision history for this document.Section Revision SummaryBoot Modes Updated QSPI entry in primary boot modes table, added thevisual boot pin usage guide table, and added eMMC1 (raw)information to the boot mode search limit table.Quad SPI Signals Added details for BootROM MIO setup.SD Signals Revised the descriptions of WP, DETECT, and bus power.Added details for BootROM MIO setup.SD2.0 Interface Specified WP, DETECT, and BUSPWR signals are optional.Added external voltage level translator information andadded note to figure.SD3.0 Interface Specified WP, DETECT, and BUSPWR signals are optional.Added external voltage level translator information andadded note to figure.eMMC1 Boot Mode Added information on the raw partition support for boot. Table 28: BootROM Error Codes Revised description for 0x301, 0x302, 0x31D, 0x320,0x517, 0x518, 0x51A, and 0x51B error codes.I/O Configuration Detection Added new section.SelectMAP Boot Mode Added SelectMAP wait time and recommendation for JTAGduring early phases and debug.eMMC1 Signals Added details for BootROM MIO setup.SelectMAP Signals Added details for BootROM MIO setup.Octal SPI Signals Added details for BootROM MIO setup.BootROM Error Codes Revised error codes and added new error codes. Address Maps and Programming Interfaces4 GB Address Space Added new section and updated address maps.Detailed 4 GB Address Maps Renamed from Detailed Address Map and reorganizedsection.IOP SLCR Registers for PMC and LPD Added new chapter.NPI Programming Interface Clarified introductory paragraph.Signals, Interfaces, and PinsPower Pins and PMC Dedicated Pins Combined Power Pins chapter with PMC Dedicated Pinschapter.PMC Dedicated Pins Removed DXP/DXN pins from the table.Power Pins Reorganized power pins table.EnginesOperating Modes Renamed from Operating States and clarified information. Configuration Registers Renamed from Hardware Configuration and reviseddescriptions.Power States Renamed from Power Modes.CPU Local Memory Maps Clarified lock-step cache entries.Memory Map Diagram Clarified 0xF900_0000 address information.FPD Block Diagram Renamed from Block Diagram.APU MPCore Functional Units Renamed from Functional Units.Embedded Processor, Configuration, and Security UnitsSection VII: Embedded Processor, Configuration, and Security Units Renamed from Platform Processor, Configuration, and Security Units, as well as reorganized chapter content.Revision HistorySection Revision SummaryPMC Global Register Set Completed register descriptions.Clock Monitor Added this chapter.InterconnectOverview Extensive additions and revisions throughout this chapter. List of Interconnect Diagrams Added new section.LPD Interconnect Port Diagram Added new section.Interconnect Hardware Added new chapter.Table 79: Interconnect Switch Functionality Removed performance module probe.Figure 58: PS Memory Address Translation Significant updates, including added new pathways, as wellas added and removed masters.Transaction Routing Added Transaction Routing Options Through CCI table. Striping Added new section.Instances Removed base address information.Address Map Added new section.Interrupts and ErrorsPMC Error Status 1 and PMC Error Status 2Added SSI technology to table.Error Containment Added new chapter.Timers, Counters, and RTCTable 119: TTC Register Overview Added address offset and access type, as well as clarifiedcontent.I/O Peripheral ControllersControl and Status Revised register names.Message Space Data Revised register names.Modes and States Revised modes and options.Programming Model Added two functional anomalies.Comparison to Previous Generation Xilinx Devices Clarified device comparison.Interrupts Added new chapter.Flash Memory ControllerStart-up Sequences Clarified idle status bit section.Voltage Level Shifter Interface Added note and added bus power to figure.Figure 103: External Voltage Level Shifter Wiring Revised figure to add bus power.SD Command Response Registers Added new section.Clocks, Resets, and PowerResets Extensive additions and updates throughout this chapter. Table 241: PMC System Reference Clock Registers Added footnote.Test and DebugFigure 112: Debug Interface Block Changed HSDP Link Layer Options to DPC Link LayerOptions. Added HSDP to CPM PCIe® and Aurora (Hard IP). JTAG and Boundary-Scan Added information on JTAG interface protections.JTAG Register Reference Added to the JTAG_CONFIG register description.TAP Instructions Changed SEC_DBG to AUTH_JTAG and updated description.Updated STATUS to JTAG_STATUS.。

Table 21: Additional Ports for Auto-Negotiation (cont'd)Port Name I/O Description ClockDomainstat_an_lp_ability_1000base_kx O These signals indicate the advertised protocol from thelink partner. They all become valid when the outputsignal stat_AN_lp_Ability_Valid is asserted. A value of 1indicates that the protocol is advertised as supported bythe link partner.an_clkstat_an_lp_ability_100gbase_cr10O an_clk stat_an_lp_ability_100gbase_cr4O an_clk stat_an_lp_ability_100gbase_kp4O an_clk stat_an_lp_ability_100gbase_kr4O an_clk stat_an_lp_ability_10gbase_kr O an_clk stat_an_lp_ability_10gbase_kx4O an_clk stat_an_lp_ability_25gbase_cr O an_clk stat_an_lp_ability_25gbase_kr O an_clk stat_an_lp_ability_40gbase_cr4O an_clk stat_an_lp_ability_40gbase_kr4O an_clkstat_an_lp_ability_2_5gbase_kx O These signals indicate the advertised protocol from thelink partner. They all become valid when the outputsignal stat_AN_lp_Ability_Valid is asserted. A value of 1indicates that the protocol is advertised as supported bythe link partner.an_clkstat_an_lp_ability_5gbase_kr O an_clk stat_an_lp_ability_50gbase_krcr O an_clk stat_an_lp_ability_100gbase_kr2cr2O an_clk stat_an_lp_ability_200gbase_kr4cr4O an_clk stat_an_lp_ability_25gbase_cr1O Indicates the advertised protocol from the link partner.Becomes valid when the output signalstat_AN_lp_Extended_Ability_Valid is asserted. A value of1 indicates that the protocol is advertised as supportedby the link partner.an_clkstat_an_lp_ability_25gbase_kr1O Indicates the advertised protocol from the link partner.Becomes valid when the output signalstat_AN_lp_Extended_Ability_Valid is asserted. A value of1 indicates that the protocol is advertised as supportedby the link partner.an_clkstat_an_lp_ability_50gbase_cr2O Indicates the advertised protocol from the link partner.Becomes valid when the output signalstat_AN_lp_Extended_Ability_Valid is asserted. A value of1 indicates that the protocol is advertised as supportedby the link partner.an_clkstat_an_lp_ability_50gbase_kr2O Indicates the advertised protocol from the link partner.Becomes valid when the output signalstat_AN_lp_Extended_Ability_Valid is asserted. A value of1 indicates that the protocol is advertised as supportedby the link partner.an_clkstat_an_lp_pause O This signal indicates the advertised value of the PAUSEbit, (C0), in the receive link codeword from the linkpartner. It becomes valid when the output signalstat_AN_lp_Ability_Valid is asserted.an_clkstat_an_lp_asm_dir O This signal indicates the advertised value of the ASMDIRbit, (C1), in the receive link codeword from the linkpartner. It becomes valid when the output signalstat_AN_lp_Ability_Valid is asserted.an_clkstat_an_lp_fec_ability O This signal indicates the advertised value of the FECability bit in the receive link codeword from the linkpartner. It becomes valid when the output signalstat_AN_lp_Ability_Valid is asserted.an_clkChapter 3: Product SpecificationTable 27: XGMII/25GMII Interface Ports (cont'd)Name I/O ClockDomain Description rx_mii_clk I Refer toClocking.Receive XGMII/25GMII Clock input.tx_mii_d[63:0]I tx_mii_clk Transmit XGMII/25GMII Data bus.tx_mii_c[7:0]I tx_mii_clk Transmit XGMII/25GMII Control bus.rx_clk_out O Refer toClocking.This is the reference clock for RX PCS stats.tx_clk_out (or tx_mii_clk)O Refer toClocking.This output is used to clock the TX MII bus. Data is clocked on the positive edge of this signal.rx_mii_reset I Async Reset input for the RX MII interface.tx_mii_reset I Async Reset input for the TX MII interface.Miscellaneous Status/Control PortsThe following table shows the miscellaneous status/control ports.Table 28: Miscellaneous Status/Control PortsName I/O ClockDomain Descriptiondclk I Refer toClocking.Dynamic Reconfiguration Port (DRP) clock input. The required frequency is set by providing the value in the GT DRP Clock field in the Vivado® IDE GT Selection and Configuration tab. This must be a free running input clock.ctl_local_loopback I Async When High, this signal places the transceiver into the PMA loopbackstate.IEEE 802.3 Clause 74 FEC InterfaceThe following table shows the IEEE 802.3 Clause 74 FEC Control/Status and Statistics signals. Table 29: IEEE 802.3 Clause 74 FEC Interface Control/Status/Statistics Signals Signal I/O Clock Descriptionctl_fec_tx_enable I tx_serdes_clk Asserted to enable the clause 74 FEC encoding on thetransmitted data.ctl_fec_rx_enable I rx_serdes_clk Asserted to enable the clause 74 FEC decoding of thereceived data.ctl_fec_enable_error_to_pcs I rx_serdes_clk Clause 74 FEC enable error to PCS.stat_fec_inc_correct_count[3:0]O rx_serdes_clk This signal will be asserted roughly every 32 words, whilethe ctl_rx_fec_enable is asserted, if the FEC decoder detectedand corrected a bit errors in the corresponding frame.stat_fec_inc_cant_correct_count[3:0 ]O rx_serdes_clk This signal will be asserted roughly every 32 words, whilethe ctl_rx_fec_enable is asserted, if the FEC decoder detectedbit.Table 37: AXI4-Stream Interface - TX Path Control/Status Signals (cont'd)Name I/O ClockDomain Descriptionctl_tx_send_idle I clk Transmit IDLE code words.If sampled as a 1, the TX path only transmits IDLEcode words.This input should be set to 1 when the partner issending RFI code words.ctl_tx_ignore_fcs I clk Enable FCS error checking at the AXI4-Streaminterface by the TX core. This input only has effectwhen ctl_tx_fcs_ins_enable is Low.If set to 0 and a packet with bad FCS is beingtransmitted, it is not binned as good.If set to 1, a packet with bad FCS is binned asgood.The error is flagged on the signals stat_tx_bad_fcsand stomped_fcs and the packet is transmitted asit was received.Note: Statistics are reported as if there was no FCSerror.ctl_tx_parity_err_response I clk Parity error response by the TX Core. If this bit isset to 0, the core does not take any action if anyparity errors are detected. If this bit is set to 1, thecore stomps the outgoing FCS (i.e., bit-wiseinverse) and asserts stat_tx_bad_fcs.AXI4-Stream Control and Status Ports - RXTable 38: AXI4-Stream Interface - RX Path Control/Status SignalsName I/O ClockDomain Descriptionctl_rx_enable I clk RX enable. For normal operation this input must be set to 1.When set to 0, after the RX completes the reception of thecurrent packet (if any), it stops receiving packets by keeping thePCS from decoding incoming data. In this mode, there are nostatistics reported and the AXI4-Stream interface is idle.ctl_rx_custom_preamble_enable I clk When asserted, this signal causes the side band of a packetpresented on the AXI4-Stream to be the preamble as it appearson the line.rx_preambleout[55:0]O clk This is the preamble, and now a separate output instead ofinline with data.ctl_rx_delete_fcs I clk Enable FCS removal by the RX core.If set to 0, the core does not remove the FCS of the incomingpacket.If set to 1, the core deletes the FCS to the received packet.FCS is not deleted for packets that are less than eight bytes.This input should only be changed while the correspondingreset input is asserted.。

Chapter 59System Watchdog TimerThe system watchdog (SWDT) timer is used to detect and recover from various malfunctions.The watchdog timer can be used to prevent system lockup (e.g., when software becomes trapped in a deadlock). There are two watchdog functions:•Generic timeout•Windowed watchdogtime periods starting with the closed-window period○Three○The size of the open and closed windows are programmableThe generic watchdog timer expects an interrupt handler running on a processor to restart thewatchdog timer at regular intervals before the timer counts down to zero. When the timer does reach zero and the watchdog is enabled, one or a combination of a system reset, interrupt, orexternal signal is generated. The watchdog timeout period and the duration of any output signals are programmable.The windowed watchdog function expects the interrupt handler to send a command on aperiodic basis that is not too soon and not too late from the previous command. Watchdogtiming is commonly used in embedded systems to activate fail-safe circuitry in the event of afault. The Versal™ ACAP SWDT provides windowing, program sequence flow, and a Q&A token request/response protocols.There are two system watchdog timers:•LPD SWDTthe RPU MPCore software execution○Protectingfunctional units, or the entire PS○Reset the RPU, other•FPD SWDTthe APU MPCore software execution○Protectingfunctional units○Reset the APU and other FPDApplications•Resetting watchdog too soonWhen a fault occurs and causes the RPU processor to enter a software routine that writes theSWDT reset command, it is possible that the software erroneously stays in the loop andrepeatedly issues the reset command in relatively quick succession. This can be detected bythe SWDT and cause it to generate an interrupt. Windowing increases the complexity ofresetting the timer to prevent the likelihood of this occurring.•Performance boundingAn additional use of the watchdog timer is to ensure the performance of the LPD stays withinexpected bounds. A narrow window of time is given to the open window that is carefullycalculated to be achievable under all correct operation scenarios. If a fault occurs that causessome performance degradation, the timer is not reset within the narrow available timewindow and the SWDT issues an interrupt. If the watchdog timer detects a problem, the errormanager is alerted via the SWDT interrupt.FeaturesThe SWDT has the following features:•Selectable reference clock input from MIO/EMIO port signal or an LSBUS_CLK clock•Up to 100 MHz reference clock frequency•One or a combination of resets and interrupts•Variable timeout periods from 1 ms to 30 seconds with a 100 MHz reference clock•Programmable reset period•Multiple device reset sources•Windowed and generic watchdog timer functionsComparison to Previous Generation Xilinx DevicesThe IP for the Versal ACAP system watchdog timer is new. The new IP includes both genericfunctionality and windowed watchdog functions.InstancesThere are two watchdog timers with the same programming model.Table 121: Watchdog Timers Register Module NameInstance Name Other Known Terms Description SWDTLPD_SWDTSWDT0, WWDT0System watchdog timer in LPD with generic and windowed functions FPD_SWDT SWDT1, WWDT1,FPD_WWDT System watchdog timer in FPD with generic and windowed functionsSystem PerspectiveBlock DiagramThe system watchdog timer block diagram is shown in the following figure.Figure 72: System Watchdog Timer Block DiagramLPD and FPD TimersX23894-050320System InterfaceBoth timers have a 32-bit APB slave programming interface.•LPD SWDT is accessible from the FPD main switch•FPD SWDT is accessible from the LPD IOP switchSection X: Timers, Counters, and RTCChapter 59: System Watchdog Timer。