HardwareSoftware Co-Simulation in a VHDL-based Test Bench Approach

RFProElectromagnetic (EM)–Circuit co-simulation environment for RF circuit designersIntroductionKeysight RFPro is an EM (electromagnetic) design environment for RF circuit designers. It automates EM-circuit co-simulation to account for EM effects on RF circuit performance in 3D IC layouts, packaging, interconnects, transitions, and PCB boards. RFPro enables interactive access to EM analysis for tuning and optimization of RF circuits during design just like circuit simulators.Figure 1. RFPro automates EM-circuit co-simulation for interactive tuning and optimization to account for EM effects of physical structures on RF circuit performance in RF Modules, RFICs, MMICs and RF Boards.Using these tools to eliminate one design spin in the fab can save us $1.5M in expenses and14 months of development time.Keysight High Frequency Technology Center R&DRFPro Capabilities for RF Circuit Designers Integration•IC and packaging EM-circuit analysis in single environment with interactive 3D view•Same interface for Keysight ADS, Cadence Virtuoso, Synopsys Design Compiler & Mentor Tanner •Preserves OpenAccess (OA) design database integrity with no need for file translations•Maintains full traceability of EM data origin from design changes and simulator usedSolver•Full 3D FEM and planar 3D Momentum solvers from same environment•Automatic expert setup of EM and EM-circuit analysis ensures trustworthy results•Sweep physical and electrical parameters easily from same environment•Same interface to launch HFSS solverLayout•Interactive EM simulation on any section of layout without manual isolation (“cookie cut”).•No need to manually extract EM and circuit components for separate simulation.•Automatic data stitching of EM ports to circuit nodes for error free EM-circuit co-simulation. RFPro Application ExamplesHere are some current application examples that RFPro and ADS are deployed to develop complex multi-technology designs that must consider EM effects of the physical structure along with circuit component behavior to make them work.Complex RF Module andEvaluation BoardFigure 2. RFPro preserves designdatabase integrity and traceability toany design changes because nomanual “cookie-cutting” and exportingto a separate EM simulator is needed.Keysight ADS enables error-freeassembly and 3D routing of complexmulti-technology RF module, includingits PCB eval board for in-situ EM-circuitsimulation by RFPro.5G/6G Antenna-Circuit InteractionsFigure 3. Nonlinear circuit excitation of integrated phased array antenna in RF module analyzes impedance change vs. beam scan angle in RFPro EM-circuit co-simulation.60GHz WiGig Wafer Level Packaging with Integrated AntennaFigure 4. Multi-technology 60 GHz WiGig module with beam forming IC, 3D feed network and phased array antenna packaging are assembled in ADS for EM analysis of any chosen RF signal paths with RFPro automatic net extraction.Acknowledgement:Designed by Fraunhofer Institute and fabricated by Global Foundries.MEMs switch and Evaluation BoardFigure 5. Ultra-low loss MEMs switch integratedonto PCB evaluation board with dimensionsranging from microns to centimeters is efficientlymeshed and accurately simulated with RFPro toachieve one-pass success.Acknowledgment: Designed and fabricated byMenloMicro.Complex RF Module AssemblyFigure 6. Complex multi-technology RF modulecontaining RFICs,MMICs, packaging,laminates, antennas, andPCBs are assembled inAdvanced Design System(ADS) for RFPro EMsimulation of any selectedRF paths withouttraditional manual“cookie-cutting.”Keysight enables innovators to push the boundaries of engineering by quickly solving design, emulation, and test challenges to create the best product experiences. Start your innovation journey at .This information is subject to change without notice. © Keysight Technologies, 2018 – 2023, Published in USA, March 31, 2023, 5992-3333ENRFPro Product ConfigurationsFigure 7. RFPro includes Full 3D FEM and Planar 3D Momentum solvers launched through an intelligent RFPro UI to automate EM-circuit analysis. EM parallel high performance computing accelerators can be added to speed up simulation from 5x to 20x. HFSS link enables HFSS as a solver (separate license required).RFPro Bundles and Element as upgrades for Momentum, HFSS, Virtuoso, Custom Compiler and Tanner users•RFPro bundles along with powerful ADS multi-technology 3D assembly layout for RF modules and RF packaging:o W3604B PathWave ADS Core, EM Design, Layout, RFProo W3606B PathWave ADS Core, EM Design, Layout, RFPro, RF Ckt Sim o W3607B PathWave ADS Core, EM Design, Layout, RFPro, RF Ckt Sim, Sys-Ckt Verificationo W3608B PathWave ADS Core, EM Design, Layout, RFPro, RF Ckt Sim, Sys-Ckt Verification, VTBs o W3615B PathWave ADS Core, EM Design Core, Layout, RFPro, HB • RFPro element W3030E shown in Figure 6 is purchased as an add-on element to an existing ADS, Virtuoso, or Custom Compiler environment•RFPro EM HPC accelerator W3039E enables parallel EM simulation to speed up analysis. Multiple accelerators can be added to increase speedup from 5x to 20x depending on nature of problem.Take the Next Step with RFProFor more information or to request a free trial of RFPro and ADS, visit • https:///zz/en/lib/resources/software-releases/whats-new-in-rf-microwave.html • https:///products/W3030E。

1ContentsContentsSafety Information ...........................................................................................2Specifications ...................................................................................................3Rear I/O Panel .................................................................................................7LAN Port LED Status Table . (7)Overview of Components (8)CPU Socket .................................................................................................................9DIMM Slots................................................................................................................10M2_1~2: M.2 Slots ...................................................................................................10PCI_E1~2: PCIe Expansion Slots ..............................................................................11SATA1~4: SATA 6Gb/s Connectors ...........................................................................11JFP1, JFP2: Front Panel Connectors .......................................................................12JAUD1: Front Audio Connector ................................................................................12ATX_PWR1, CPU_PWR1: Power Connectors ...........................................................13JUSB1: USB 2.0 Connector ......................................................................................14JUSB2: USB 3.2 Gen 1 5Gbps Connector .................................................................14CPU_FAN1, SYS_FAN1: Fan Connectors .................................................................15JTPM1: TPM Module Connector ...............................................................................15JCI1: Chassis Intrusion Connector ...........................................................................16JCOM1: Serial Port Connector .................................................................................16JBAT1: Clear CMOS (Reset BIOS) Jumper ...............................................................17EZ Debug LED ...........................................................................................................17JRGB1: RGB LED connector (H410M PRO) ..............................................................18JRAINBOW1: Addressable RGB LED connector (H410M PRO) ...............................18UEFI BIOS . (19)BIOS Setup ................................................................................................................20Entering BIOS Setup .................................................................................................20Resetting BIOS ..........................................................................................................20Updating BIOS...........................................................................................................21Installing OS, Drivers & Utilities . (22)Installing Windows ® 10..............................................................................................22Installing Drivers ......................................................................................................22Installing Utilities .. (22)Thank you for purchasing the MSI ® H410M PRO/ H410M-A PRO/ H410M PRO-VH motherboard. This User Guide gives information about board layout, component overview, BIOS setup and software installation.Safety Information∙The components included in this package are prone to damage from electrostatic discharge (ESD). Please adhere to the following instructions to ensure successful computer assembly.∙Ensure that all components are securely connected. Loose connections may cause the computer to not recognize a component or fail to start.∙Hold the motherboard by the edges to avoid touching sensitive components. ∙It is recommended to wear an electrostatic discharge (ESD) wrist strap when handling the motherboard to prevent electrostatic damage. If an ESD wrist strap is not available, discharge yourself of static electricity by touching another metal object before handling the motherboard.∙Store the motherboard in an electrostatic shielding container or on an anti-static pad whenever the motherboard is not installed.∙Before turning on the computer, ensure that there are no loose screws or metal components on the motherboard or anywhere within the computer case.∙Do not boot the computer before installation is completed. This could cause permanent damage to the components as well as injury to the user.∙If you need help during any installation step, please consult a certified computer technician.∙Always turn off the power supply and unplug the power cord from the power outlet before installing or removing any computer component.∙Keep this user guide for future reference.∙Keep this motherboard away from humidity.∙Make sure that your electrical outlet provides the same voltage as is indicated on the PSU, before connecting the PSU to the electrical outlet.∙Place the power cord such a way that people can not step on it. Do not place anything over the power cord.∙All cautions and warnings on the motherboard should be noted.∙If any of the following situations arises, get the motherboard checked by service personnel:▪Liquid has penetrated into the computer.▪The motherboard has been exposed to moisture.▪The motherboard does not work well or you can not get it work according touser guide.▪The motherboard has been dropped and damaged.▪The motherboard has obvious sign of breakage.∙Do not leave this motherboard in an environment above 60°C (140°F), it may damage the motherboard.2Safety Information3Specifications4Specifications5SpecificationsPlease refer to http:///manual/mb/DRAGONCENTER2.pdf formore details.6SpecificationsH410M-A PRO)Audio 7.1-channel ConfigurationTo configure 7.1-channel audio, you have to connect front audio I/O module to JAUD1 connector and follow the below steps.1. Click on the Realtek HD Audio Manager > Advanced Settings to open the dialog below.2. Select Mute the rear output device, when a front headphone plugged in.3. Plug your speakers to audio jacks on rear and front I/O panel. When you plug intoa device at an audio jack, a dialogue window will pop up asking you which device is current connected.7Rear I/O PanelOverview of Components* Distance from the center of the CPU to the nearest DIMM slot. 8Overview of Components9Overview of ComponentsImportant∙Always unplug the power cord from the power outlet before installing or removing the CPU.∙Please retain the CPU protective cap after installing the processor. MSI will deal with Return Merchandise Authorization (RMA) requests if only the motherboard comes with the protective cap on the CPU socket.∙When installing a CPU, always remember to install a CPU heatsink. A CPU heatsink is necessary to prevent overheating and maintain system stability.∙Confirm that the CPU heatsink has formed a tight seal with the CPU before booting your system.∙Overheating can seriously damage the CPU and motherboard. Always make sure the cooling fans work properly to protect the CPU from overheating. Be sure to apply an even layer of thermal paste (or thermal tape) between the CPU and the heatsink to enhance heat dissipation.∙Whenever the CPU is not installed, always protect the CPU socket pins by covering the socket with the plastic cap.∙If you purchased a separate CPU and heatsink/ cooler, Please refer to the docu-mentation in the heatsink/ cooler package for more details about installation.10Overview of ComponentsImportant∙Always insert memory modules in the DIMMA1 slot first.∙To ensure system stability for Dual channel mode, memory modules must be of the same type, number and density.∙Some memory modules may operate at a lower frequency than the marked value when overclocking due to the memory frequency operates dependent on its Serial Presence Detect (SPD). Go to BIOS and find the DRAM Frequency to set the memory frequency if you want to operate the memory at the marked or at a higher frequency. ∙It is recommended to use a more efficient memory cooling system for full DIMMs installation or overclocking.∙The stability and compatibility of installed memory module depend on installed CPU and devices when overclocking.∙Please refer for more information on compatible memory.M2_1~2: M.2 SlotsPlease install the M.2 device into the M.2 slot as shown below.13StandoffSupplied11Overview of Componentsunplug the power supply power cable from the power outlet. Read the expansion card’s documentation to check for any necessary additional hardware or software changes.∙If you install a large and heavy graphics card, you need to use a tool such as MSI Gaming Series Graphics Card Bolster to support its weight to prevent deformationof the slot.SATA1~4: SATA 6Gb/s ConnectorsThese connectors are SATA 6Gb/s interface ports. Each connector can connect to one SATA device.⚠Important∙Please do not fold the SATA cable at a 90-degree angle. Data loss may result during transmission otherwise.∙SATA cables have identical plugs on either sides of the cable. However, it is recommended that the flat connector be connected to the motherboard for space saving purposes.∙SATA4 will be unavailable when installing M.2 SATA SSD in the M.2 slot.JFP1, JFP2: Front Panel ConnectorsJAUD1: Front Audio Connector12Overview of ComponentsATX_PWR1, CPU_PWR1: Power ConnectorsImportantMake sure that all the power cables are securely connected to a proper ATX power supply to ensure stable operation of the motherboard.13Overview of Components14Overview of ComponentsJUSB2: USB 3.2 Gen 1 5Gbps ConnectorImportantNote that the Power and Ground pins must be connected correctly to avoid possible damage.JUSB1: USB 2.0 ConnectorImportant∙Note that the VCC and Ground pins must be connected correctly to avoid possible damage.∙In order to recharge your iPad,iPhone and iPod through USB ports, please install MSI® DRAGON CENTER utility.15Overview of ComponentsImportantYou can adjust fan speed in BIOS > Hardware Monitor.CPU_FAN1, SYS_FAN1: Fan ConnectorsPWM Mode fan connectors provide constant 12V output and adjust fan speed with speed control signal. When you plug a 3-pin (Non-PWM) fan to a fan connector in PWM mode, the fan speed will always maintain at 100%, which might create a lot ofnoise.JTPM1: TPM Module ConnectorThis connector is for TPM (Trusted Platform Module). Please refer to the TPMJCI1: Chassis Intrusion Connector(default)intrusion event Using chassis intrusion detector1. Connect the JCI1 connector to the chassis intrusion switch/ sensor on thechassis.2. Close the chassis cover.3. Go to BIOS > SETTINGS > Security > Chassis Intrusion Configuration.4. Set Chassis Intrusion to Enabled.5. Press F10 to save and exit and then press the Enter key to select Yes.6. Once the chassis cover is opened again, a warning message will be displayed onscreen when the computer is turned on.Resetting the chassis intrusion warning1. Go to BIOS > SETTINGS > Security > Chassis Intrusion Configuration.2. Set Chassis Intrusion to Reset.3. Press F10 to save and exit and then press the Enter key to select Yes. JCOM1: Serial Port Connector16Overview of ComponentsJBAT1: Clear CMOS (Reset BIOS) JumperThere is CMOS memory onboard that is external powered from a battery located on the motherboard to save system configuration data. If you want to clear the system(default)BIOSResetting BIOS to default values1. Power off the computer and unplug the power cord.2. Use a jumper cap to short JBAT1 for about 5-10 seconds.3. Remove the jumper cap from JBAT1.4. Plug the power cord and power on the computer.EZ Debug LEDThese LEDs indicate the status of the motherboard.CPU - indicates CPU is not detected or fail.DRAM - indicates DRAM is not detected or fail.VGA - indicates GPU is not detected or fail.BOOT - indicates booting device is not detected or fail.17Overview of ComponentsJRGB1: RGB LED connector (H410M PRO)Important∙The JRGB connector supports up to 2 meters continuous 5050 RGB LED strips (12V/G/R/B) with the maximum power rating of 3A (12V).∙Always turn off the power supply and unplug the power cord from the power outlet before installing or removing the RGB LED strip.∙Please use MSI’s software to control the extended LED strip. JRAINBOW1: Addressable RGB LED connector (H410M PRO)The JRAINBOW connector allows you to connect the WS2812B Individually Addressable RGB LED strips 5V.CAUTIONDo not connect the wrong type of LED strips. The JRGB connector and the JRAINBOW connector provide different voltages, and connecting the 5V LED strip to the JRGB connector will result in damage to the LED strip.⚠Important∙The JRAINBOW connector supports up to 75 LEDs WS2812B Individually Address-able RGB LED strips (5V/Data/Ground) with the maximum power rating of 3A (5V). In the case of 20% brightness, the connector supports up to 200 LEDs.∙Always turn off the power supply and unplug the power cord from the power outlet before installing or removing the RGB LED strip.∙Please use MSI’s software to control the extended LED strip.18Overview of ComponentsUEFI BIOSMSI UEFI BIOS is compatible with UEFI (Unified Extensible Firmware Interface) architecture. UEFI has many new functions and advantages that traditional BIOS cannot achieve, and it will completely replace BIOS in the future. The MSI UEFI BIOS uses UEFI as the default boot mode to take full advantage of the new chipset’s capabilities. However, it still has a CSM (Compatibility Support Module) mode to be compatible with older devices. That allows you to replace legacy devices with UEFI compatible devices during the transition.⚠ImportantThe term BIOS in this user guide refers to UEFI BIOS unless otherwise noted. UEFI advantages∙Fast booting - UEFI can directly boot the operating system and save the BIOS self-test process. And also eliminates the time to switch to CSM mode during POST.∙Supports for hard drive partitions larger than 2 TB.∙Supports more than 4 primary partitions with a GUID Partition Table (GPT).∙Supports unlimited number of partitions.∙Supports full capabilities of new devices - new devices may not provide backward compatibility.∙Supports secure startup - UEFI can check the validity of the operating system to ensure that no malware tampers with the startup process.Incompatible UEFI cases∙32-bit Windows operating system - this motherboard supports only 64-bit Windows 10 operating system.∙Older graphics card - the system will detect your graphics card. When display a warning message There is no GOP (Graphics Output protocol) support detected in this graphics card.⚠ImportantWe recommend that you to use a GOP/ UEFI compatible graphics card.How to check the BIOS mode?19UEFI BIOSBIOS SetupThe default settings offer the optimal performance for system stability in normal conditions. You should always keep the default settings to avoid possible system damage or failure booting unless you are familiar with BIOS.⚠Important∙BIOS items are continuous update for better system performance. Therefore, the description may be slightly different from the latest BIOS and should be held for reference only. You could also refer to the HELP information panel for BIOS item description.∙The BIOS items will vary with the processor. Entering BIOS SetupPress Delete key, when the Press DEL key to enter Setup Menu, F11 to enter Boot Menu message appears on the screen during the boot process.Function keyF1: General HelpF2: Add/ Remove a favorite itemF3: Enter Favorites menuF4: Enter CPU Specifications menuF5: Enter Memory-Z menuF6: Load optimized defaultsF7: Switch between Advanced mode and EZ modeF8: Load Overclocking ProfileF9: Save Overclocking ProfileF10: Save Change and Reset*F12: Take a screenshot and save it to USB flash drive (FAT/ FAT32 format only). Ctrl+F: Enter Search page* When you press F10, a confirmation window appears and it provides the modification information. Select between Yes or No to confirm your choice. Resetting BIOSYou might need to restore the default BIOS setting to solve certain problems. There are several ways to reset BIOS:∙Go to BIOS and press F6 to load optimized defaults.∙Short the Clear CMOS jumper on the motherboard.⚠ImportantPlease refer to the Clear CMOS jumper section for resetting BIOS.20UEFI BIOSUpdating BIOSUpdating BIOS with M-FLASHBefore updating:Please download the latest BIOS file that matches your motherboard model from MSI website. And then save the BIOS file into the USB flash drive.Updating BIOS:1. Insert the USB flash drive that contains the update file into the USB port.2. Please refer the following methods to enter flash mode.▪Reboot and press Ctrl + F5 key during POST and click on Yes to reboot the system.▪Reboot and press Del key during POST to enter BIOS. Click the M-FLASH button and click on Yes to reboot the system.3. Select a BIOS file to perform the BIOS update process.4. When prompted click on Yes to start recovering BIOS.5. After the flashing process is 100% completed, the system will reboot automatically.Updating the BIOS with Dragon CenterBefore updating:Make sure the LAN driver is already installed and the internet connection is set properly.Updating BIOS:1. Install and launch MSI DRAGON CENTER and go to Support page.2. Select Live Update and click on Advance button.3. Click on Scan button to search the latest BIOS file.4. Select the BIOS file and click on Download icon to download and install the latest BIOS file.5. Click Next and choose In Windows mode. And then click Next and Start to start updating BIOS.6. After the flashing process is 100% completed, the system will restart automatically.21UEFI BIOSInstalling OS, Drivers & UtilitiesPlease download and update the latest utilities and drivers at Installing Windows® 101. Power on the computer.2. Insert the Windows® 10 installation disc/USB into your computer.3. Press the Restart button on the computer case.4. Press F11 key during the computer POST (Power-On Self Test) to get into BootMenu.5. Select the Windows® 10 installation disc/USB from the Boot Menu.6. Press any key when screen shows Press any key to boot from CD or DVD...message.7. Follow the instructions on the screen to install Windows® 10. Installing Drivers1. Start up your computer in Windows® 10.2. Insert MSI® Driver Disc into your optical drive.3. Click the Select to choose what happens with this disc pop-up notification,then select Run DVDSetup.exe to open the installer. If you turn off the AutoPlayfeature from the Windows Control Panel, you can still manually execute theDVDSetup.exe from the root path of the MSI Driver Disc.4. The installer will find and list all necessary drivers in the Drivers/Software tab.5. Click the Install button in the lower-right corner of the window.6. The drivers installation will then be in progress, after it has finished it will promptyou to restart.7. Click OK button to finish.8. Restart your computer.Installing UtilitiesBefore you install utilities, you must complete drivers installation.1. Open the installer as described above.2. Click the Utilities tab.3. Select the utilities you want to install.4. Click the Install button in the lower-right corner of the window.5. The utilities installation will then be in progress, after it has finished it willprompt you to restart.6. Click OK button to finish.7. Restart your computer.22Installing OS, Drivers & Utilities。

Agilent 16800 SeriesPortable Logic AnalyzersData SheetQuickly debug, validate,and optimize your digitalsystem – at a price thatfits your budget.Features and benefits•250 ps resolution (4 GHz) timingzoom to find elusive timing problemsquickly, without double probing•15” display, with available touchscreen, allows you to see more dataand navigate quicklymeasurements and displays of yourlogic analyzer and oscilloscope datalet you effectively track downproblems across the analog anddigital portions of your design•Eight models with34/68/102/136/204 channels,up to 32M memory depth andmodels with a pattern generatorprovide the measurement flexibilityfor any budget•Application support for every aspectof today’s complex designs – FPGAdynamic probe, digital VSA (vectorsignal analysis) and broad processorand bus support2Selection Guide for 16800 Series Portable Logic AnalyzersModels with a built-in pattern generator give you more measurement flexibility1Pattern generator available with 16821A, 16822A and 16823A.Choose from eight models to get the measurement capability for your specific applicationProbes are ordered separately. Please specify probes when ordering to ensure the correct connection between your logic analyzer, pattern generator, and the device under test.Agilent 16800 Series portable logic analyzers offer the performance, applications, and usability your digital development team needs to quickly debug, validate, and optimize your digital system – at a price that fits your budget.The logic analyzer’s timing and state acquisition gives you the power to:•Accurately measure precise timing relationships using4GHz (250ps) timing zoomwith 64K depth•Find anomalies separated in time with memory depthsupgradeable to 32M•Buy what you need today and upgrade in the future. 16800Series logic analyzers comewith independent upgrades for memory depth and state speed •Sample synchronous buses accurately and confidentlyusing eye finder. Eye finderautomatically adjuststhreshold and setup andhold to give you the highestconfidence in measurementson high-speed buses•Track problems from symptom to root cause across severalmeasurement modes byviewing time-correlated datain waveform/chart, listing,inverse assembly, source code, or compare display •Set up triggers quickly andconfidently with intuitive,simple, quick, and advancedtriggering. This capabilitycombines new triggerfunctionality with an intuitiveuser interface•Access the signals that holdthe key to your system’sproblems with the industry’swidest range of probingaccessories with capacitiveloading down to 0.7 pF•Monitor and correlate multiplebuses with split analyzercapability, which providessingle and multi-bus support(timing, state, timing/state orstate/state configurations)Accurately measure precisetiming relationships16800 Series logic analyzers letyou make accurate high-speedtiming measurements with 4GHz(250ps) high-speed timing zoom. Aparallel acquisition architectureprovides high-speed timingmeasurements simultaneouslythrough the same probe used forstate or timing measurements.Timing zoom stays active all thetime with no tradeoffs. View dataat high resolution over longerperiods of time with 64-K-deeptiming zoom.Figure 1. With eight models to choose from, you can get alogic analyzer with measurement capabilities that meetyour needs.3Automate measurement setup and quickly gain diagnostic clues16800 Series logic analyzers make it easy for you to get up and running quickly by automating your measurement setup process. In addition, the logic analyzer’s setup/hold window (or sampling position) and threshold voltage settings are automatically determined so you can capture data on high-speed buses with the highest accuracy. Auto Threshold and Sample Position mode allow you to...•Obtain accurate and reliable measurements•Save time during measurement setup•Gain diagnostic clues and identify problem signalsquickly•Scan all signals and buses simultaneously or just a few•View results as a composite display or as individual signals•See skew between signals and buses•Find and fix inappropriate clock thresholds•Measure data valid windows•Identify signal integrityproblems related to rise times,fall times, data valid windowwidths Identify problem signals overhundreds of channels simultaneouslyAs timing and voltage marginscontinue to shrink, confidencein signal integrity becomes anincreasingly vital requirementin the design validation process.Eye scan lets you acquire signalintegrity information on allthe buses in your design, undera wide variety of operatingconditions, in a matter ofminutes. Identify problem signalsquickly for further investigationwith an oscilloscope. Results canbe viewed for each individualsignal or as a composite ofmultiple signals or buses.Extend the life of your equipmentEasily upgrade your 16800 Serieslogic analyzer. “Turn on”additional memory depth andstate speed when you need more.Purchase the capability youneed now, then upgrade as yourneeds evolve.Figure 2. Identify problem signals quickly by viewing eye diagrams across all buses and signals simultaneously.4578910A Built-in Pattern Generator Gives You Digital Stimulus and Responsein a Single InstrumentSelected 16800 Series models (16821A, 16822A and 16823A)also include a 48-channel pattern generator to drive down risk early in product development. With a pattern generator you can:•Substitute for missing boards,integrated circuits (ICs) or buses instead of waiting for missing pieces •Write software to createinfrequently encountered test conditions and verify that the code works – before complete hardware is available •Generate patterns necessary to put a circuit in a desired state,operate the circuit at full speed or step the circuit through a series of states •Create a circuit initialization sequence Agilent 16800 Series portable logic analyzers with a pattern generator offer a variety offeatures that make it easier for you to create digital stimulus tests.Vectors up to 48 bits wideVectors are defined as a “row” of labeled data values, with each data value from one to 48 bits wide. Each vector is output on the rising edge of the clock.Create stimulus patterns for the widest buses in your system.Depth up to 16 M vectorsWith the pattern generator, you can load and run up to 16Mvectors of stimulus. Depth on this scale is most useful when coupled with powerful stimulus generated by electronic design automation tools, such as SynaptiCAD’sWaveFormer and VeriLogger.These tools create stimulus using a combination of graphicallydrawn signals, timing parameters that constrain edges, clock signals,and timing and Boolean equations for describing complex signal behavior. The stimulus also can be created from design simulation waveforms. The SynaptiCAD tools allow you to convert .VCD files into .PGB files directly, offering you an integrated solution that saves you time.Synchronized clock outputYou can output data synchronized to either an internal or external clock. The external clock is input via a clock pod, and has nominimum frequency (other than a 2ns minimum high time).The internal clock is selectable between 1MHz and 300MHz in 1-MHz steps. A Clock Out signal is available from the clock pod and can be used as an edge strobe with a variable delay of up to 8ns.Initialize (INIT) block for repetitive runsWhen running repetitively, the vectors in the initialize (init)sequence are output only once,while the main sequence isoutput as a continually repeating sequence. This “init” sequence is very useful when the circuit or subsystem needs to be initialized.The repetitive run capability is especially helpful whenoperating the pattern generator independent of the logic analyzer.“Send Arm out to…” coordinates activity with the logic analyzerVerify how your system responds to a specific stimulus sequence by arming the logic analyzer from the pattern generator. A “Send Arm out to…” instruction acts as a trigger arming event for the logic analyzer or other test equipment to begin measurements. Arm setup and trigger setup of the logic analyzer determines the action initiated by “Send Arm out to…”.Figure 3. Models with a built-in pattern generator give you more measurement flexibility.“Wait for External Event…” forinput patternThe clock pod also accepts a 3-bit input pattern. These inputs are level-sensed so that any number of “Wait for External Event”instructions can be inserted into a stimulus program. Up to four pattern conditions can be defined from the OR-ing of the eight possible 3-bit input patterns. A “Wait for External Event” also can be defined to wait for an Arm. This Arm signal can come from the logic analyzer. “Wait for External Event…” allows you to executea specific stimulus sequence only when the defined external event occurs.Simplify creation of stimulus programs with user-defined macros and loops User macros permit you to define a pattern sequence once, then insert the macro by name wherever it is needed. Passing parameters to the macro will allow you to create a more generic macro. For each call to the macro you can specify unique values for the parameters.Loops enable you to repeat a defined block of vectors for a specified number of times. Loops and macros can be nested, except that a macro cannot be nested within another macro. At compile time, loops and macros are expanded in memory to alinear sequence.Convenient data entry andediting featureYou can conveniently enterpatterns in hex, octal, binary,decimal, and signed decimal(two’s complement) bases. Tosimplify data entry, you can viewthe data associated with anindividual label with multipleradixes. Delete, Insert, and Copycommands are provided for easyediting. Fast and convenientPattern Fills give the programmeruseful test patterns with a fewkey strokes. Fixed, Count, Rotate,Toggle, and Random patterns areavailable to help you quicklycreate a test pattern, suchas “walking ones.” Patternparameters, such as step size andrepeat frequency, can be specifiedin the pattern setup.ASCII input file format: your designtool connectionThe pattern generator supportsan ASCII file format to facilitateconnectivity to other tools in yourdesign environment. Because theASCII format does not support theinstructions listed earlier, theycannot be edited into the ASCIIfile. User macros and loops alsoare not supported, so the vectorsneed to be fully expanded in theASCII file. Many design tools willgenerate ASCII files and outputthe vectors in this linear sequence.Data must be in hex format, andeach label must represent a set ofcontiguous output channels.ConfigurationThe pattern generator operateswith the clock pods, data pods,and lead sets described later inthis document. At least one clockpod and one data pod must beselected to configure a functionalsystem. You can select from avariety of pods to provide thesignal source needed for your logicdevices. The data pods, clock podsand data cables use standardconnectors. The electricalcharacteristics of the data cablesare described for users withspecialized applications who wantto avoid the use of a data pod.Direct connection to yourtarget systemYou can connect the patterngenerator pods directly to astandard connector on your targetsystem. Use a 3M brand #2520Series or similar connector. Theclock or data pods will plug rightin. Short, flat cable jumpers canbe used if the clearance aroundthe connector is limited. Use a 3M#3365/20, or equivalent, ribboncable; a 3M #4620 Series orequivalent connector on thepattern generator pod end of thecable, and a 3M #3421 Series orequivalent connector at yourtarget system end of the cable.Probing accessoriesThe probe tips of theAgilent10474A, 10347A, 10498A,and E8142A lead sets plugdirectly into any 0.1-inch gridwith 0.026-inch to 0.033-inchdiameter round pins or 0.025-inchsquare pins. These probe tipswork with the Agilent5090-4356surface mount grabbers andwith the Agilent5959-0288through-hole grabbers, providingcompatibility with industrystandard pins.A Built-in Pattern Generator Gives You Digital Stimulus and Response in a Single Instrument3-STATE IN TTLPattern generator cable pin outsData cable (Pod end)Clock cable (Pod end)2122Unleash the Complementary Power of a Logic Analyzer and an Oscilloscope Seamless scope integrationwith View ScopeEasily make time-correlatedmeasurements between Agilentlogic analyzers and oscilloscopes.The time-correlated logic analyzerand oscilloscope waveforms areintegrated into a single logicanalyzer waveform display foreasy viewing and analysis. Youcan also trigger the oscilloscopefrom the logic analyzer (or viceversa), automatically de-skew thewaveforms and maintain markertracking between the twoinstruments. Perform thefollowing more effectively:•Validate signal integrity•Track down problems caused by signal integrity•Validate correct operation of A/D and D/A converters •Validate correct logical and timing relationships betweenthe analog and digital portions of a designConnectionThe Agilent logic analyzer and oscilloscope can be physically connected with standard BNC and LAN connections. Two BNC cables are connected for cross triggering, and the LAN connection is used to transfer data between the instruments. The View Scope correlation software is standard in the logic analyzer’s application software version 3.50 or higher. The View Scope software includes:•Ability to import some or all of the captured oscilloscopewaveforms•Auto scaling of the scopewaveforms for the best fit inthe logic analyzer displayFigure 4. View Scope seamlessly integrates your scopeand logic analyzer waveforms into a single display.2324Acquisition and analysis tools provide rapid insight into your toughest debug problemsYou have unique measurement and analysis needs. When you want to understand what your target is doing and why, you need acquisition and analysis tools that rapidly consolidate data into displays that provide insight into your system’s behavior.Figure 5. Perform in-depth time, frequency and modulation domain analysis on your digital baseband and IF signals with Agilent’s 89600 Vector Signal Analysis software.Save time analyzing your unique design with a turnkey setup Agilent Technologies and our partners provide an extensive range of bus and processor analysis probes. They provide non-intrusive, full-speed,real-time analysis to accelerate your debugging process.•Save time making bus-and processor-specificmeasurements withapplication specific analysisprobes that quickly andreliably connect to yourdevice under test•Display processor mnemonicsor bus cycle decode•Get support for acomprehensive list ofindustry-standard processorsand buses252627ProgrammabilityYou can write programs to control the logic analyzer application from remote computers on the local area network using COM or ASCII. The COM automation serveris part of the logic analyzer application. This software allows you to write programs to control the logic analyzer. All measurement functionality is controllable via the COM interface.The B4608A Remote ProgrammingInterface (RPI) lets you remotelycontrol a 16800 Series logicanalyzer by issuing ASCIIcommands to the TCP socketon port 6500. This interface isdesigned to be as similar aspossible to the RPI on 16700Series logic analysis systems,so that you can reuse existingprograms.The remote programminginterface works through the COMautomation objects, methods,and properties provided forcontrolling the logic analyzerapplication. RPI commands areimplemented as Visual Basicmodules that execute COMautomation commands, translatetheir results, and return propervalues for the RPI. You can use theB4606A advanced customizationenvironment to customize andadd RPI commands.Figure 6. 16800 Series programming overview2816800 Series Interfaces2930Figure 9. 16800 Series back panelFull profile PCI card expansion slotExternal display portParallel portSerial port10/100 Base T LAN 2.0 USB ports (4)Clock inTrigger out Trigger in Keyboard Mouse AC power Figure 8. 16800 Series front panelOn/Off power switch 15 inch built-in color LCD display, Touch Screen available General purpose knob Run/stop keys Touch screen on/off (if ordered)16800 Series Physical CharacteristicsDimensionsPower 16801A 115/230 V, 48-66 Hz, 605 W max 16802A 115/230 V, 48-66 Hz, 605 W max 16803A 115/230 V, 48-66 Hz, 605 W max 16804A 115/230 V, 48-66 Hz, 775 W max 16806A 115/230 V, 48-66 Hz, 775 W max 16821A 115/230 V, 48-66 Hz, 775 W max 16822A 115/230 V, 48-66 Hz, 775 W max 16823A 115/230 V, 48-66 Hz, 775 W max Weight Max net Max shipping 16801A 12.9 kg 19.7 kg (28.5 lbs)(43.5 lbs)16802A 13.2 kg 19.9 kg (28.9 lbs)(43.9 lbs)16803A 13.7 kg 20.5 kg (30.3 lbs)(45.3 lbs)16804A 14.2 kg 21.0 kg (31.3 lbs)(46.3 lbs)16806A 14.6 kg 21.4 kg (32.1 lbs)(47.1 lbs)16821A 14.2 kg 20.9 kg (31.2 lbs)(46.2 lbs)16822A 14.2 kg 21.1 kg (31.6 lbs)(46.6 lbs)16823A14.5 kg 21.3 kg (32.0 lbs)(47.0 lbs)Instrument operating environment Temperature 0˚ C to 50˚ C (32˚ F to 122˚ F)Altitude To 3000 m (10,000 ft)Humidity8 to 80% relative humidity at 40˚ C (104˚ F)Figure 7. 16800 Series exterior dimensionsFigure 10. 16800 Series side view330.32(13.005)Dimensions: mm (inches)28.822(11.347)443.23(17.450)Agilent 1184A TestmobileThe Agilent 1184A testmobile gives you a convenient means of organizing and transporting your logic analyzer and accessories.The testmobile includes the following:•Drawer for accessories(probes, cables, power cords)•Keyboard tray with adjustable tilt and height•Mouse extension on keyboard tray for either right or lefthand operation•on uneven surfaces••Load limits:Total: 136.4 kg (300.0 lb.)Figure 11. Agilent 1184A testmobile cartFigure 12. Agilent 1184A testmobile cart dimensions3132Stationary shelfThis light-duty fixed shelf isdesigned to support 16800 Series logic analyzers. The shelf can be used in all standard Agilent racks. The stationary shelf is mounted securely into placeusing the supplied hardware and is designed to sit at the bottom of the EIA increment. Features of the stationary shelf include:•Snap-in design for easy installation •Smooth edgesRack accessoriesSliding shelfThe sliding shelf provides a flat surface with full product accessibility. It can be used in all Agilent racks to support 16800Series logic analyzers. The shelf and slides are preassembled for easy installation. Features of the sliding shelf include:•Snap-in design for easy installation •Smooth edgesConsider purchasing the steel ballast (C2790AC) to use with the sliding shelf. The ballast provides anti-tip capability when the shelf is extended.Figure 15. Sliding shelf (J1526AC)Figure 14. Stationary shelf (J1520AC)Figure 13. Sliding shelf installed in rackEach 16800 Series portable logicanalyzer comes with one PS/2keyboard, one PS/2 mouse,accessory pouch, power cord and1-year warranty standard.Selecting a logic analyzer to meet your application and budget is as easy as 1, 2, 3333435。

On-Chip Monitoring of Single-and Multiprocessor Hardware Real-Time Operating SystemsMohammed El ShobakiDepartment of Computer EngineeringM¨a lardalen University,V¨a steras,Swedenmei@mdh.seA bstractThis paper presents a novel hardware monitoring system that gives non-intrusive observability into the execution of hardware-accelerated Real-Time Operating Systems.Monitoring is a necessity for testing,debugging and per-formance evaluations of real-time computer systems.Most research into monitoring of real-time systems have been de-voted to minimising the execution interference imposed by the monitor.One approach to this has been the use of hard-ware support to extract software execution traces by prob-ing the external processor(or system)busses.However,the use of cache memories on various levels, and the increased integration of system components on-chip (SoCs)in addition to limited chip-package pins,severely obstructs traditional hardware monitors from probing pro-cessor signals and busses.For real-time systems built on these premises there is a need to access execution informa-tion residing on-chip,as well as to avoid interference with the system’s execution behaviour.In this paper we present an integrated solution to on-chip monitoring of system-level events in a real-time system.The monitor,called MAMon1,probes a hardware-based Real-Time Kernel using a Probe Unit integrated as an IP-block. This component detects and collects events regarding pro-cess’execution,communication,synchronisation,and I/O interrupt activities.Collected events are timestamped and transferred to a separate computer system hosting an event database and a set of monitoring application tools.We describe the monitor architecture,the implementation of a prototype,and an evaluation of its use.1IntroductionRun-time observability in embedded system architec-tures is a requirement for testing,debugging,and for val-1Multiprocess Application Monitor idating design assumptions made about the behaviour of the system and its environment.The classical approach to run-time observability is to apply monitoring,i.e.the pro-cess of detecting,collecting,and interpreting run-time in-formation regarding the system’s execution behaviour.In monitoring real-time systems an important aspect is to min-imise,or completely avoid,the intrusiveness of the monitor on the system’s timing and execeution properties.Failing to handle monitor intrusivity may lead to probe effects which cause non-deterministic behaviour in programs with race conditions and poor synchronisation[6,13].The research efforts on real-time monitoring has over the past decade been mostly devoted to dealing with probe ef-fects and timing interference in various applications of mon-itoring[17,18,2,8,7].Hence,a wide spectrum of moni-toring approaches have been proposed,ranging from pure software techniques[17,8]to the use of special hardware support[12,18,7].Software monitoring systems offer the cheapest and mostflexible solution where a common tech-nique is to insert instrumentation code at interesting points in the target software.When the instrumentation code is executed the monitoring process is triggered and informa-tion of interest is captured into trace buffers in target system memory.The drawbacks of instrumentation is the utilisa-tion of target resources such as memory space and proces-sor execution time.Moreover,to avoid probe effects,the instrumentation code must be kept in the deployed software or be compensated for in the real-time schedulability anal-ysis[17]-with both alternatives resulting in performance penalties.Hardware monitoring systems on the other hand use special hardware to passively probe the target’s physical busses,such as the processor and system busses,and collect information of interest without interfering with the target’s execution.The main advantage with hardware monitoring is that probe effects can be completely avoided.The disad-vantages are the dependancy on the target architecture and its related costs.Hybrid monitoring uses a combination of software and hardware monitoring and is typically used to reduce the impact of software instrumentation alone[7].With today’s highly integrated hardware,encapsulating complete systems on a chip(SoC),the traditional hardware monitors are facing severe difficulties.Processor cores,I/O components,cache memories,and even standard memory, are all integrated on the same chip.Given also that chip packages can be obstructive(as in Ball-Grid Array pack-ages)and have limited pins,it has become almost impos-sible for external hardware to probe internal signals.For real-time systems built on these premises there is a need to access execution information residing on-chip,as well as to avoid interference with the system’s execution behaviour.In this paper we present an architecture for on-chip monitoring of single-and multiprocessor real-time sys-tems that are based on hardware-accelerated operating sys-tems[1,10,14,15].The monitor,called MAMon,probes a hardware-implemented Real-Time Kernel(RTK)using a Probe Unit integrated as an IP-block at the VHDL-level.A hardware RTK implements traditional(software)RTOS functions,such as scheduling algorithms,process manage-ment and communication,in hardware[1,11].Operating at the system-level the Integrated Probe Unit detects and collects events regarding process’execution,communica-tion,synchronisation,and I/O interrupt activities.The col-lected events are timestamped with the resolution of the system clock frequency(10MHz=100ns)and then trans-ferred,via a high-speed parallel port link,to a separate host computer system.At the host the events are stored in a database which constitutes the heart of a monitoring application framework featuring event analysis and debug-ging(searching,filtering,and graphing),performance eval-uations,and more.Monitoring occur mainly at the system-level,but lower abstraction-levels are supported too by al-lowing instrumentation code to write to dedicated probe registers in the monitor hardware.This opportunity would, however,classify the monitor as a hybrid system,and thus requires a perturbation analysis of the software instrumen-tation.The main contributions of this work are the ideas on system-level monitoring of hardware RTKs,on-chip rather than by probing external processor busses.We believe that on-chip monitoring support will be required in future de-velopment of real-time systems,especially those based on SoCs.The paper is organised as follows.Section2describes a multiprocessor system concept based on a hardware-accelerated RTOS.This system will be the target platform in further discussions on our proposed monitor.Section3 describes the monitor architecture for a generic target RTOS that utilise hardware RTKs.An overview of the system and a detailed description is given for the Integrated Probe Unit, the host-based monitoring application framework,and the communication interface in between.Section4describes an FPGA prototype implementation of the monitor for a multiprocessor system with3PowerPC-750processors.An evaluation of the prototype is given in Section5,andfinally, Section6summarises the paper with some concluding re-marks and directions on future work.2A Real-Time MultiprocessorArchitecture-SARAThe Scalable Architecture for Real-Time Applications (SARA[10,9])is a research platform for real-time mul-tiprocessor computing systems.The two main research ob-jectives with SARA are:1)to provide a hardware architec-ture that behaves predictably to the real-time application, and2)to provide aflexible system architecture that simpli-fies processor(performance)scalability.In attaining these design goals,a SARA architecture is based on a hardware-accelerated RTOS.The hardware support comes from a co-processor called RTU(Real-Time Unit[1,11])which provides the RTOS with kernel-level services such as pro-cess/task scheduling,synchronisation and communication, see Section2.1for more details.Figure1shows the hardware view of a SARA system which includes one or more processor nodes,a commu-nication network(bus),and the RTU as a shared software process scheduler.This view is the same whether the hard-ware is implemented on a multi-board computer system, such as VME or CompactPCI-based[16]systems,or as a SoC.A SARA implementation on a CompactPCI system is described in Section2.2,and in[3]a SoC implementation is proposed.Figure1.Hardware view of a SARA systemThe software,which is partitioned onto each node in SARA,includes a minimal RTOS which mainly interfaces to the RTU,and a collection of processes which are sched-uled to execute on one or more processor node(s).To sim-plify the programming model,hardware is abstracted to the software so that processes need not be bound to a certain processor,and process migration is allowed.Communication between processes takes part over a vir-tual bus(VCB)which spans over all processor nodes.TheVCB programming model,shown in Figure2,uses the con-cept of virtual slots which processes must attach to in or-der to send and receive messages.Moreover,synchronised sending,broadcasting and multicasting of messages is sup-ported.Virtual Communication Bus(VCB)Figure2.Process communication model inSARA2.1RTU-Real-Time Kernel in HardwareHardware support to increase performance and pre-dictability in real-time operating systems have been pro-posed in[14,1,11,15].The Real-Time Unit,RTU by Lindh et.al.[1,11],is a co-processor with support for real-time kernel services such as process scheduling and management(create,terminate,etc),inter-process com-munication(IPC,message send/receive),synchronisation (semaphores),and I/O interrupt handling.The RTU,which supports scheduling of both single-and multiprocessor sys-tems,runs in parallel with the target system’s processor(s). Processors interface with the RTU by memory-mapping to its processor-independant register interface.Via this in-terface,service-calls are placed by writing to dedicated service-call registers.Figure3shows the basic building blocks of the RTU. The core part is the scheduler which schedules processes on-line(pre-emptive priority scheme)and dispatches pro-cess execution.Connected in between the scheduler and the programming/bus interface,a set of functional modules implements the various services in the RTU,such as man-agement of the scheduler,IPC,semaphores,clock and timer management.Process context-switching is notified to CPUs usinginterrupts causing handlers in software to perform the actual context-switching.2.2A SARA CompactPCI SystemDesribed in[9]is a SARA implementation on a CompactPCI(CPCI[16])computer system.A CPCI systemFigure3.Basic building blocks of the RTU has8slots where CPU-boards can be inserted.Thefirst slot, slot0,is dedicated as the system slot which requires that the CPU-board on that slot handles arbitration and clock distri-bution on the CPCI backplane.Figure4shows the current SARA implementation with3PowerPC-750CPU-boards. The RTU,which resides on a PMC-board(PCI Mezzanine Card[16]),is attached to the system board from where it can communicate with all CPUs in the system(see also Fig-ure10).All CPU-boards have local memory and a local PCI-bus. Processes that are allowed to migrate between CPUs require global memory to hold their Process Control Blocks(PCB). This global memory can be defined out of local memories on all CPU-boards.Currently,global memory is allocated at the system board only.MemoryFigure 4.A SARA system based onCompactPCI-board computers[9]3A Monitoring System for Hardware-Accelerated Real-Time Operating Systems 3.1OverviewThe proposed monitoring system aims at providing means for on-chip observability at the system-level in single-and multiprocessor real-time systems.The monitor, which we call MAMon(short for Multiprocess Application Monitor),is based on the following assumptions about the monitored target system:The target’s RTOS is supported by a hardware Real-Time Kernel(RTK),like the RTU or a similar compo-nent as described in Section2.1.The RTK holds information about the state of every process in the system,inter-process communication activities,timers,interrupts,etc.The RTK must allow external access to internal(vi-tal)signals and data.Since the RTU was available to us as a soft IP-component(HDL source),access to all signals and data is straightforward in VHDL.The architecture of MAMon,shown in Figure5,consists of two major parts:the Integrated Probe Unit(IPU,Sec-tion3.2)which is the hardware part of MAMon,and a host computer system.Like an IP-block,the IPU is integrated with the hardware RTK at the VHDL level.In a SoC the IPU may also be connected to processor busses,I/O com-ponents,and other hardware logic in order to extract infor-mation at various levels of abstraction.In the synthesized hardware(e.g.ASIC or FPGA implementation),the IPU monitors the RTK in run-time,and collects events regard-ing the system-level behaviour of the real-time application. The collected events are timestamped each and then trans-ferred over a high-speed parallel communication port to the host computer where they are stored in a database.In an integrated framework(Section3.5)the database serves as an event repository which can be used by monitoring appli-cation tools to provide event-based debugging,performance analysis,assessment of design constraints,etc.In certain cases there is a need to generate events from software,for instance,to mark code checkpoints(flags), or to report register and memory contents required for lower-level analysis.Such events are produced by insert-ing software instructions(software probes)that writes to a dedicated register connected in between the IPU and the system/processor bus.3.2The Integrated Probe UnitFigure6shows a block-diagram of the IPU’s internal or-ganisation.Target SystemExternal FIFOHostEvent SignalsFigure 6.The Integrated Probe UnitFigure 7.The event sample formatwidth.Moreover,it has signals that indicate when the buffer becomes full,or half-full.3.2.3FIFO ManagerThe FIFO Manager mainly provides a byte-wide interface for the Host Port to read event data from the FIFO.In cir-cumstances when the required FIFO size is not feasible on-chip,e.g.in FPGA implementations,the FIFO Manager can also be used to extend the FIFO using external RAM.In this case,the FIFO Manager will also take care of flushing the contents of the on-chip FIFO out to the external RAM.The option to use external RAM can be set via the Host Port.3.2.4Host PortThe Host Port is responsible for taking care of host-inititated acquisition of event data.It also provides the host with a programming interface to read the status of the IPU and to control its behaviour (the Control Logic in Figure 6).Since FIFO buffering is limited it is important that event samples are transferred to the host with a guaranteed high communication bandwidth.Therefore,the Host Port im-plements the bi-directional Enhanced Parallel Port protocol (EPP 1.9[4]).In theory the EPP supports transfer rates up to 2MB/s (approx.160k events/s).To indicate availability of events in the FIFO the Host Port can be programmed to generate an interrupt to the host computer.When this feature is enabled,it can be set into one of three modes:Interrupt whenever new events arrive Interrupt when the FIFO buffer is half-full Interrupt when the FIFO buffer is fullThe first two modes are useful when continous monitor-ing is desired.The third mode is more useful if the IPU is set to sample from a given command until the FIFO becomes full,and then stop.Providing the ability to choose the in-terrupt mode gives a customised solution that best suits the capabilities of the host computer performance,the tools,or the user.When the interrupt function is disabled,events can still be acquired in polled mode.3.3EventsCurrently the Event Detector supports detection of four types of events;Taskswitches,Service-Calls,Interrupts,and Software Probes .The conditions for these events are hardcoded in the Event Detector.Therefore,the size of the Event Detector logic is linearly proportional to the number of supported events.Given below is a description of each event-type;its condition(s)and related data to be collected.3.3.1Taskswitch eventsFor a taskswitch to be detected,the IPU is connected directly to the scheduler module in the RTU.Whenever a taskswitch is to occur,the scheduler asserts an interrupt signal and indicates the next task’s id along with the CPU it is to run on.Upon detection of this event the following packet is produced.TSW EVT TIMESTAMPCPU NR –TASK ID 1B6B1B2B2B3.3.2Service-Call eventsA service-call is detected whenever software writes to a Service-Call Register in the RTU,i.e.to indicate a service-request.For each CPU in the system there exists one Service-Call Register in the RTU’s register-interface.These registers are connected to the IPU as well.An event of this type produces the following packet.SVC EVT TIMESTAMPCPU NR REG VALUE1B6B1B4B3.3.3Interrupt eventsThe RTU supports handling of external interrupts by associating tasks with the interrupts.When an interrupt is asserted the RTU’s interrupt module tells the scheduler to start the associated task.To detect this event,the interrupt lines are connected to the IPU along with the associated tasks’id.An interrupt event produce the follwing packet. IRQ EVT TIMESTAMP IRQ NR–TASK ID 1B6B1B2B2B3.3.4Software-Probe eventsA software probe is similar to a service-call request in that software writes to registers in the RTU.However,these register are dedicated to MAMon and are connected only to the IPU.Values written to these registers can be used for profiling,measurements and debugging purposes.A software probe event produce the following packet.SWP EVT TIMESTAMP REG NR REG VALUE 1B6B1B4B3.4Performance and FIFO Dimensioning3.4.1Input rateThe rate at which the EDU detects and stores events in the FIFO buffer depends on the system freqency;the higher fre-quency,the higher the input rate to the buffer.The EDU re-quires2clock cycles to store one event in the buffer.Since the currently supported events(see previous section)cannot occur consecutively within2clock cycles,no events will be missed.This implies that the worst condition corresponds to an event occuring every2clock cycles.With a clock freqency of10MHz,the input rate is1occurence per200 ns.It is also assumed that the input rate follows a Poisson statistical distribution,as described in[12].3.4.2Output rateThe output rate for emptying the event FIFO buffer is larg-erly determined by the performance of the host interface communication link,the EPP port in this case.In theory, EPP supports transfer rates up to2MB/s[4].When using a PC running Linux as the MAMon host computer,and a stan-dard bi-directional parallel port interface,we could reach a maximum transfer rate of1.3MB/s.We therefore estimate the time to transfer one event-packet to10s,assuming a transfer involves13byte reads;12for event data plus1for reading the IPU’s status register(to check for event avail-ability).The rate at which events are stored in the database is not considered since it is much faster than the communi-cation bandwidth.3.4.3FIFO buffer dimensionTo eliminate buffer overflow the FIFO buffer must be large enough to handle the worst case inputflow while the MAMon host system is busyflushing the buffer.By ap-plying a queueing analysis(adopted from[12])we can es-timate the required buffer size.This analysis assumes two facts:1)events can arrive concurrently while the buffer is flushed,and2)that the MAMon host system startsflushing the buffer at latest when the buffer is half full.Thefirst as-sumption is fulfilled as the FIFO buffer is dual-ported.The second assumption requires that the host either polls conti-nously for new events,or uses the half-full-buffer interrupt mode.Let be half the FIFO buffer size,the mean input rate, and the transfer time per event-packet.Assuming that the input rate follows the Poisson distribution,then,is defined as the probability that the buffer has arrivals in time(i.e.that half the bufferfills up within).The probability function is,In determining the total buffer size()it is assumed that the probability offilling up half the buffer is at a minimum, for instance0.5%,given that it takes time toflush the first buffer half.That is,Using and,gives70as the best value for.Hence,the FIFO buffer must handle no less than140events.3.5The Monitoring Application FrameworkTo provide the user with a platform for event-based per-formance analysis and debugging,we have developed an integrated framework for monitoring applications.Our goal is not to develop a complete monitoring envrionment,but to show the capabilities with our hardware monitoring ap-proach.The framework is developed mainly in Java and uses an SQL database to store the event histories.Figure8shows this framework’s architecture.At the bottom lies the IPU interface module which is mainly used to transfer event samples from the IPU into the SQL database,and to con-trol the behaviour of the IPU.The IPU interface module runs as a separate process,but is controlled from the Java framework via the Java Native method Interface(JNI).JNI is required becasue this module is written in C/C++as it is strongly dependant on the underlying architecture for com-municating with the EPP interface.The SQL database isrun by the MySQL DBMS().We choose MySQL for its speed and capabilities to handle our amounts of events,and because it is free for educational purposes. The database and IPU interface constitutes the base of our framework.The Java application forms the actual framework which provides an integrated interface to control the monitoring process,to collect events into the database,and to query the event database in various ing this interface we can now easily implement application specific monitoring tools that are plugged into the framework.From/To IPUFigure8.MAMon’s Application FrameworkAn example monitoring tool is the Event Viewer that displays portions of the event history.Such a tool can be useful forfinding and analysing erroneous execution pat-terns.The Event Viewer tool,shown in Figure9,collects events from the database,and displays them along a time-line.Apart from standard functions such as zooming and scrolling,there is also support for time-markers that are used for timing measurements,and search-markers that can be used to locate event conditions and patterns.Another example tool is the Event Query tool(also shown in Figure9)which provides a user-friendly interface to query the database for event conditions and execution patterns.The output from the query may be output textu-ally to screen or to afile,or graphically by linking its results with the Event Viewer tool.The event database is alsosuitable for other post-analysis,such as extraction of performance indexes for use in diagrams and histograms showing task’s execution time, processor utilisation,IPC frequencies,interrupt response times,etc.4Physical Hardware ImplementationIn this section we present some implementation details on a prototype of MAMon for a SARA CompactPCI system (described in Section2.2).Figure9.Screenshot of Event Query&EventViewer tools4.1The Hardware PrototypeThe IPU is implemented together with the Real-Time Unit2on a Xilinx Virtex-1000FPGA[5].All modules are designed in VHDL which is either textually entered or auto-matically generated from state and block diagrams drawn in Renoir(graphical hardware design tool,by Mentor Graph-ics).The FPGA is mounted on a PMC-board and connects to the SARA-systemvia a PCI bus-interface chip(PLX-bridge),see Figure10.The host system of MAMon con-nects to the parallel-port connector(left in Figure10)with a IEEE-1284C cable[4].Because RAM-cells are limited inside the FPGA,a128kB SRAM module(on backside of the board)is used to extend the internal event FIFO buffer.Figure10.PMC-board with a Xilinx Virtex-1000FPGA and PLX-bridge[9]4.2Physical FootprintTable1shows some areafigures from a synthesis to a Xilinx Virtex-1000target.Although thesefigures are target-specific,they could serve as a reference for estimating the 2The RTU in this prototype was synthesised to support128tasks with 64priorities.equivalent area requirements for other silicon technologies. Xilinx’s FPGA technology can be described as matrices of Configurable Logic Blocks(CLBs)where each CLB con-tains two Function Generators(FGs)and two D-Flip-Flops. According to Xilinx,a Virtex-1000FPGA has a capacity of “1million gates”[5].Resource IPU RTU Avail UtilisationCLB Slices18132761228828.13%FGs.36165532457628.13%Flip-Flops25425802457611.53%Table1.Areafigures for a Xilinx V1000FPGA As shown in the table,the IPU makes up only5%of the total number of CLBs for the whole design.What is not shown in thefigures,however,is the area costs for the event FIFO buffer.This is becasue FIFO memory was mapped onto RAM cells built-in the FPGA(called Block-Select RAM). However,calculating the area costs for memory is straight-forward in many technologies.Currently the event FIFO buffer can store16events where each is96bits wide(12 bytes),i.e.1536bits are required.The host interface port,currently implemented as an EPP parallel port,requires15I/O pins;8for data,and7for con-trol.On a chip with limited pinouts it could be preferrable to multiplex these pins with other I/O,or choose an interface with less ports,e.g.a synchronous serial port.Moreover,an additional29I/O pins are used to interface with the external SRAM used to extend the event FIFO buffer.As this mem-ory is optional,this overhead can be removed if the internal event FIFO can befitted on-chip.5Prototype EvaluationThe prototype system was validated in a number of small tests on both single-and multiprocessor targets.With no in-trusion on neither the execution or the timing behaviour of the target system the prototype was able to monitor task-switches,service-calls,and external interrupts.Monitoring of software probes(hybrid monitoring)was also accom-plished but with a minimal intrusion equal to the delay of a32-bit PCI-transfer per probe(@33MHz=30ns).To il-lustrate a proof of concept we present hereunder an example were we analyse a deadlock situation using the monitor. Example:Deadlock DetectionThe program in this example illustrate a typical situation where two tasks need to synchronise before proceeding to a next step,in this case opening a pair of fuel valves.The deadlock occurs due to an in-planted synchronisation error between the two tasks T1and T2which execute on pro-cessors CPU1and CPU2respectively.Figure11shows the pseudo-code for the tasks.The tasks synchronise with mu-tual sending and receiving of messages over the VCB(de-scribed in Section2).Task T1uses the blocking sendwait() call to send a message and wait for the other party to send as well.For a proper synchronisation,task T2should also call sendwait(),but due to a programming error the receive() call was used instead.This results in a deadlock since T1 cannot resume,and T2will get blocked the second time it calls receive().Global VCB Slot_T1;Task T1(){Slot_T1=Connect_to_VCB();LOOP{Compute_X;...Slot_T1.sendwait(slot_T2);Open_valve1();...Close_valve1();}}Global VCB Slot_T2;Task T2(){Slot_T2=Connect_to_VCB();LOOP{Compute_Y;...Slot_T2.receive();//Bug!Open_valve2();...Close_valve2();}}Figure11.Deadlock example in pseudo-codeTo locate the erroneous bug,wefirst monitor the tar-get system and collect the system-level events into the host database.The Event Query tool is then used to perform a filtered search in the event ing predicate dis-juncts and conjuncts in the query we can easilyfind thefirst and last occurences of the tasks of interest.Figure12shows a text-dump from the query tool.Rows1-3shows that T1 starts and attempts to connect to the VCB.Rows4-6shows the similar sequence for T2.The sendwait()call in T1is mapped to the VCB primitives VCB Put and VCB Get seen on rows7-8.After that T1gets blocked,the IDLE task starts on that processor(row9).At row10,T2receives the message from T1without blocking,and later when it at-tempts to receive again at row11it gets blocked too.The same sequence of events can also be depicted by the Event Viewer tool,see Figure13.Horizontal bars indicate execut-ing tasks,and the icons beneath indicate service-calls.6ConclusionsThis paper has described a monitoring system and its im-plementation for non-intrusive monitoring of real-time sys-tems.The monitoring system,called MAMon,integrates a probe component with a hardware Real-Time Kernel in or-der to non-intrusively detect and collect process-level events at the target system.Via a parallel communication link,the。

Features Array•Fast Read Access Time – 70 ns•Automatic Page Write Operation–Internal Address and Data Latches for 64 Bytes•Fast Write Cycle Times–Page Write Cycle Time: 10 ms Maximum (Standard)2 ms Maximum (Option – Ref. AT28HC64BF Datasheet)–1 to 64-byte Page Write Operation•Low Power Dissipation–40 mA Active Current–100µA CMOS Standby Current•Hardware and Software Data Protection•DATA Polling and Toggle Bit for End of Write Detection•High Reliability CMOS Technology–Endurance: 100,000 Cycles–Data Retention: 10 Years•Single 5 V ±10% Supply•CMOS and TTL Compatible Inputs and Outputs•JEDEC Approved Byte-wide Pinout•Industrial Temperature Ranges•Green (Pb/Halide-free) Packaging Option Only1.DescriptionThe AT28HC64B is a high-performance electrically-erasable and programmable read-only memory (EEPROM). Its 64K of memory is organized as 8,192 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 55 ns with power dissipation of just 220 mW. When the device is deselected, the CMOS standby current is less than 100µA.The AT28HC64B is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 64-byte page register to allow writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to 64 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA polling of I/O7. Once the end of a write cycle has been detected, a new access for a read or write can begin.Atmel’s AT28HC64B has additional features to ensure high quality and manufactura-bility. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mecha-nism is available to guard against inadvertent writes. The device also includes anextra 64 bytes of EEPROM for device identification or tracking.20274L–PEEPR–2/3/09AT28HC64B2.Pin Configurations2.128-lead SOIC Top ViewPin Name Function A0 - A12Addresses CE Chip Enable OE Output Enable WE Write Enable I/O0 - I/O7Data Inputs/Outputs NC No Connect DCDon’t Connect2.232-lead PLCC Top ViewNote:PLCC package pins 1 and 17 are Don’t Connect.2.328-lead TSOP Top View30274L–PEEPR–2/3/09AT28HC64B3.Block Diagram4.Device Operation4.1ReadThe AT28HC64B is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the out-puts. The outputs are put in the high-impedance state when either CE or OE is high. This dual line control gives designers flexibility in preventing bus contention in their systems.4.2Byte WriteA low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started, it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of t WC , a read operation will effectively be a polling operation.4.3Page WriteThe page write operation of the AT28HC64B allows 1 to 64 bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write; after the first byte is written, it can then be followed by 1 to 63 additional bytes. Each successive byte must be loaded within 150 µs (t BLC ) of the previous byte. If the t BLC limit is exceeded, the AT28HC64B will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A6 to A12 inputs. For each WE high-to-low transition during the page write operation, A6 to A12 must be the same.The A0 to A5 inputs specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur.4.4DATA PollingThe AT28HC64B features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle, an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at any time during the write cycle.40274L–PEEPR–2/3/09AT28HC64B4.5Toggle BitIn addition to DATA Polling, the AT28HC64B provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling, and valid data will be read. Toggle bit reading may begin at any time during the write cycle.4.6Data ProtectionIf precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. Atmel ® has incorporated both hardware and software features that will protect the memory against inadvertent writes.4.6.1Hardware ProtectionHardware features protect against inadvertent writes to the AT28HC64B in the following ways: (a) V CC sense – if V CC is below 3.8 V (typical), the write function is inhibited; (b) V CC power-on delay – once V CC has reached 3.8 V, the device will automatically time out 5 ms (typical) before allowing a write; (c) write inhibit – holding any one of OE low, CE high or WE high inhib-its write cycles; and (d) noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle.4.6.2Software Data ProtectionA software-controlled data protection feature has been implemented on the AT28HC64B. When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by the user; the AT28HC64B is shipped from Atmel with SDP disabled.SDP is enabled by the user issuing a series of three write commands in which three specific bytes of data are written to three specific addresses (refer to the “Software Data Protection Algorithm” diagram on page 10). After writing the 3-byte command sequence and waiting t WC , the entire AT28HC64B will be protected against inadvertent writes. It should be noted that even after SDP is enabled, the user may still perform a byte or page write to the AT28HC64B. This is done by preceding the data to be written by the same 3-byte command sequence used to enable SDP.Once set, SDP remains active unless the disable command sequence is issued. Power transi-tions do not disable SDP, and SDP protects the AT28HC64B during power-up and power-down conditions. All command sequences must conform to the page write timing specifica-tions. The data in the enable and disable command sequences is not actually written into the device; their addresses may still be written with user data in either a byte or page write operation.After setting SDP, any attempt to write to the device without the 3-byte command sequence will start the internal write timers. No data will be written to the device, however. For the dura-tion of t WC , read operations will effectively be polling operations.4.7Device IdentificationAn extra 64 bytes of EEPROM memory are available to the user for device identification. By raising A9 to 12 V ±0.5 V and using address locations 1FC0H to 1FFFH, the additional bytes may be written to or read from in the same manner as the regular memory array.50274L–PEEPR–2/3/09AT28HC64BNotes:1.X can be VIL or VIH.2.See “AC Write Waveforms” on page 8.3.VH = 12.0 V ±0.5 V.Note:1.I SB1 and I SB2 for the 55 ns part is 40 mA maximum.5.DC and AC Operating RangeAT28HC64B-70AT28HC64B-90AT28HC64B-120Operating Temperature (Case)-40°C - 85°C -40°C - 85°C -40°C - 85°C V CC Power Supply5 V ±10%5 V ±10%5 V ±10%6.Operating ModesMode CE OE WE I/O Read V IL V IL V IH D OUT Write (2)V IL V IH V IL D IN Standby/Write Inhibit V IH X (1)X High ZWrite Inhibit X X V IH Write Inhibit X V IL X Output Disable X V IH XHigh ZChip Erase V ILV H (3)V IL High Z7.Absolute Maximum Ratings*Temperature Under Bias................................-55°C to +125°C *NOTICE:Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliabilityStorage Temperature.....................................-65°C to +150°C All Input Voltages(including NC Pins)with Respect to Ground.................................-0.6 V to +6.25 V All Output Voltageswith Respect to Ground...........................-0.6 V to V CC + 0.6 V Voltage on OE and A9with Respect to Ground..................................-0.6 V to +13.5V8.DC CharacteristicsSymbol Parameter ConditionMinMax Units I LI Input Load Current V IN = 0 V to V CC + 1 V 10µA I LO Output Leakage Current V I/O = 0 V to V CC10µA I SB1V CC Standby Current CMOS CE = V CC - 0.3 V to V CC + 1 V 100(1)µA I SB2V CC Standby Current TTL CE = 2.0 V to V CC + 1 V 2(1)mA I CC V CC Active Current f = 5 MHz; I OUT = 0 mA40mA V IL Input Low Voltage 0.8V V IH Input High Voltage 2.0V V OL Output Low Voltage I OL = 2.1 mA 0.40V V OH Output High VoltageI OH = -400 µA2.4V60274L–PEEPR–2/3/09AT28HC64B10.AC Read Waveforms (1)(2)(3)(4)Notes:1.CE may be delayed up to t ACC - t CE after the address transition without impact on t ACC .2.OE may be delayed up to t CE - t OE after the falling edge of CE without impact on t CE or by t ACC - t OE after an address changewithout impact on t ACC .3.t DF is specified from OE or CE whichever occurs first (C L = 5 pF).4.This parameter is characterized and is not 100% tested.9.AC Read CharacteristicsSymbol ParameterAT28HC64B-70AT28HC64B-90AT28HC64B-120Units MinMax MinMax MinMax t ACC Address to Output Delay 7090120ns t CE (1)CE to Output Delay 7090120ns t OE (2)OE to Output Delay 035040050ns t DF (3)(4)OE to Output Float 035040050ns t OHOutput Hold00ns70274L–PEEPR–2/3/09AT28HC64B11.Input Test Waveforms and Measurement Level12.Output Test LoadNote:1.This parameter is characterized and is not 100% tested.R F 13.Pin Capacitancef = 1 MHz, T = 25°C (1)Symbol Typ Max Units Conditions C IN 46pF V IN = 0 V C OUT 812pFV OUT = 0 V815.AC Write Waveforms15.1WE Controlled15.2CE Controlled14.AC Write CharacteristicsSymbol ParameterMin MaxUnits t AS , t OES Address, OE Setup Time 0ns t AH Address Hold Time 50ns t CS Chip Select Setup Time 0ns t CH Chip Select Hold Time 0ns t WP Write Pulse Width (WE or CE)100ns t DS Data Setup Time 50ns t DH , t OEHData, OE Hold Timens90274L–PEEPR–2/3/09AT28HC64B17.Page Mode Write Waveforms (1)(2)Notes: 1.A6 through A12 must specify the same page address during each high to low transition of WE (or CE).2.OE must be high only when WE and CE are both low.18.Chip Erase Waveformst S = t H = 5 µs (min.)t W = 10 ms (min.)V H = 12.0 V ±0.5 V16.Page Mode CharacteristicsSymbol Parameter MinMax Units t WC Write Cycle Time10ms t WC Write Cycle Time (Use AT28HC64BF))2ms t AS Address Setup Time 0ns t AH Address Hold Time 50ns t DS Data Setup Time 50ns t DH Data Hold Time 0ns t WP Write Pulse Width 100ns t BLC Byte Load Cycle Time 150µs t WPHWrite Pulse Width High50ns100274L–PEEPR–2/3/09AT28HC64B19.Software Data Protection EnableAlgorithm (1)Notes:1.Data Format: I/O7 - I/O0 (Hex);Address Format: A12 - A0 (Hex).2.Write Protect state will be activated at end of writeeven if no other data is loaded.3.Write Protect state will be deactivated at end of writeperiod even if no other data is loaded.4.1 to 64 bytes of data are loaded.20.Software Data Protection DisableAlgorithm (1)Notes:1.Data Format: I/O7 - I/O0 (Hex);Address Format: A12 - A0 (Hex).2.Write Protect state will be activated at end of writeeven if no other data is loaded.3.Write Protect state will be deactivated at end of writeperiod even if no other data is loaded.4. 1 to 64 bytes of data are loaded.21.Software Protected Write Cycle Waveforms (1)(2)Notes:1.A6 through A12 must specify the same page address during each high to low transition of WE (or CE) after the softwarecode has been entered.2.OE must be high only when WE and CE are both low.11AT28HC64BNote:1.These parameters are characterized and not 100% tested. See “AC Read Characteristics” on page 6.23.Data Polling WaveformsNotes:1.These parameters are characterized and not 100% tested.2.See “AC Read Characteristics” on page 6.25.Toggle Bit Waveforms (1)(2)(3)Notes: 1.Toggling either OE or CE or both OE and CE will operate toggle bit.2.Beginning and ending state of I/O6 will vary.3.Any address location may be used, but the address should not vary.22.Data Polling Characteristics (1)Symbol Parameter Min TypMaxUnits t DH Data Hold Time 0ns t OEH OE Hold Time 0ns t OE OE to Output Delay (1)ns t WR Write Recovery Timens24.Toggle Bit Characteristics (1)Symbol Parameter Min TypMaxUnits t DH Data Hold Time 10ns t OEH OE Hold Time 10ns t OE OE to Output Delay (2)ns t OEHP OE High Pulse 150ns t WR Write Recovery Timens12AT28HC64B26.Normalized I CCGraphs13AT28HC64B27.Ordering Information27.1Green Package Option (Pb/Halide-free)t ACC (ns)I CC (mA)Ordering Code Package Operation RangeActive Standby 70400.1AT28HC64B-70TU 28T Industrial (-40°C to 85°C)AT28HC64B-70JU 32J AT28HC64B-70SU 28S 90400.1AT28HC64B-90JU 32J AT28HC64B-90SU 28S AT28HC64B-90TU 28T 120400.1AT28HC64B-12JU 32J AT28HC64B-12SU28SPackage Type32J 32-lead, Plastic J-leaded Chip Carrier (PLCC)28S 28-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)28T28-lead, Plastic Thin Small Outline Package (TSOP)27.2Die ProductsContact Atmel Sales for die sales options.28.Packaging Information 28.132J – PLCC14AT28HC64BAT28HC64B 28.228S – SOIC1528.328T – TSOP16AT28HC64BHeadquarters InternationalAtmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USATel: 1(408) 441-0311 Fax: 1(408) 487-2600Atmel AsiaUnit 1-5 & 16, 19/FBEA Tower, Millennium City 5418 Kwun Tong RoadKwun Tong, KowloonHong KongTel: (852) 2245-6100Fax: (852) 2722-1369Atmel EuropeLe Krebs8, Rue Jean-Pierre TimbaudBP 30978054 Saint-Quentin-en-Yvelines CedexFranceTel: (33) 1-30-60-70-00Fax: (33) 1-30-60-71-11Atmel Japan9F, Tonetsu Shinkawa Bldg.1-24-8 ShinkawaChuo-ku, Tokyo 104-0033JapanTel: (81) 3-3523-3551Fax: (81) 3-3523-7581Product ContactWeb SiteTechnical Support******************Sales Contact/contactsLiterature Requests/literatureDisclaimer: The information in this document is provided in connection with Atmel products. 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.SNNOISERuns periodic AC noise analysis on nonautonomous circuits in a large-signal periodic steady state..SNNOISE output insrc frequency_sweep [N1, +/-1]+ [LISTFREQ=(freq1 [freq2 ... freqN ]|none|all]) [LISTCOUNT=num ]+ [LISTFLOOR=val ] [LISTSOURCES=on|off].HBAC / .SNACRuns periodic AC analysis on circuits operating in a large-signal periodic steady state..HBAC frequency_sweep .SNAC frequency_sweep.HBXF / .SNXFCalculates transfer function from the given source in the circuit to the designated output..HBXF out_var frequency_sweep .SNXF out_var frequency_sweep.PTDNOISECalculates the noise spectrum and total noise at a point in time..PTDNOISE output TIME=[val |meas |sweep ] +[TDELTA=time_delta ] frequency_sweep+[listfreq=(freq1 [freq2 ... freqN ]|none|all)] [listcount=num ]+[listfloor=val ] [listsources=on|off]RF OptionsSIM_ACCURACY=x Sets and modifies the size of the time steps. The higher the value, thegreater the accuracy; the lower the value, the faster the simulation runtime. Default is 1.TRANFORHB=n 1 Forces HB analysis to recognize or ignore specific V/I sources, 0 (default) ignores transient descriptions of V/I sources.HBCONTINUE=n Specifies whether to use the sweep solution from the previous simulation as the initial guess for the present simulation. 0 restarts each simulation in a sweep from the DC solution, 1 (default) uses the previous sweep solution as the initial guess.HBSOLVER=n Specifies a preconditioner for solving nonlinear circuits. 0 invokes the direct solver. 1 (default) invokes the- matrix-free Krylov solver. 2 invokes the two-level hybrid time-frequency domain solver.SNACCURACY=n Sets and modifies the size of the time steps. The higher the value, the greater the accuracy; the lower the value, the faster the simulation runtime. Default is 10.SAVESNINIT=”filename ” Saves the operating point at the end of SN initialization.LOADSNINIT=”filename ” Loads the operating point saved at end of SN initialization.Output Commands.BIASCHK .MEASURE .PRINT .PROBEFor details about all commands and options, see the HSPICE ® Reference Manual: Commands and Control Options.Synopsys Technical Publications 690 East Middlefield Road Mountain View, CA 94043Phone (650) 584-5000 or (800) Copyright ©2017 Synopsys, Inc. All rights reserved.Signal Integrity Commands.LINCalculates linear transfer and noise parameters for a general multi-port network..LIN [sparcalc [=1|0]] [modelname=modelname ] [filename=filename ]+ [format=selem|citi|touchstone|touchstone2] [noisecalc [=1|0]]+ [gdcalc [=1|0]] [dataformat=ri|ma|db]+ [listfreq=(freq1 [freq2 ... freqN ]|none|all)] [listcount=num ]+ [listfloor=val ] [listsources=1|0|yes|no].STATEYEPerforms Statistical Eye Diagram analysis..STATEYE T=time_interval Trf=rise_fall_time [Tr=rise_time ] + [Tf=fall_time ] Incident_port=idx1[, idx2, … idxN ]+ Probe_port=idx1[, idx2, … idxN ] [Tran_init=n_periods ] + [V_low=val ] [V_high=val ] [TD_In=val ] [TD_PROBE=val ]+ [T_resolution=n ] [V_resolution=n ] [VD_range=val ]+ [EDGE=1|2|4|8] [MAX_PATTERN=n ] [PATTERN_REPEAT=n ] + [SAVE_TR=ascii] [LOAD_TR=ascii] [SAVE_DIR=string ]+ [IGNORE_Bits=n ] [Tran_Bit_Seg=n ]+ [MODE=EDGE|CONV|TRAN] [XTALK_TYPE = SYNC|ASYNC|DDP|NO|ONLY]+ [Unfold_Length=n ] [TXJITTER_MODE = 1|2]RF Analysis Commands.ACPHASENOISEHelps interpret signal and noise quantities as phase variables for accumulated jitter for closed-loop PLL analysis..ACPHASENOISE output input [interval ] carrier=freq+ [listfreq=(freq1 [freq2 ... freqN ]|none|all)][listcount=num ]+ [listfloor=val ] [listsources=1|0].HBRuns periodic steady state analysis with the single and multitone Harmonic Balance algorithm..HB TONES=F1[,F2,…,FN ] [SUBHARMS=SH ] [NHARMS=H1[,H2,…,HN ]]+ [INTMODMAX=n ] [SWEEP parameter_sweep ].SNRuns periodic steady state analysis using the Shooting Newton algorithm..SN TRES=Tr PERIOD=T [TRINIT=Ti ] [MAXTRINITCYCLES=integer ]+ [SWEEP parameter_sweep ] [NUMPEROUT=val ].SN TONE=F1 [TRINIT=Ti ] NHARMS=N [MAXTRINITCYCLES=integer ]+ [NUMPEROUT=val ] [SWEEP parameter_sweep ].HBOSC / .SNOSCPerforms analysis on autonomous oscillator circuits..HBOSC TONE=F1 NHARMS=H1+ PROBENODE=N1,N2,VP [FSPTS=NUM,MIN,MA X]+ [SWEEP parameter_sweep ] [SUBHARMS=I ] [STABILITY=-2|-1|0|1|2].SNOSC TONE=F1 NHARMS=H1 [TRINIT=Ti ]+ [OSCTONE=N ] [MAXTRINITCYCLES=N ]+ [SWEEP parameter_sweep ].PHASENOISEInterprets signal / noise quantities as phase variables for accumulated jitter in closed-loop PLL analysis..PHASENOISE output frequency_sweep [method= 0|1|2]+ [listfreq=(freq1 [freq2 ... freqN ]|none|all)] [listcount=num ]+ [listfloor=val ] [listsources=1|0] [carrierindex=int ].HBNOISEPerforms cyclo-stationary noise analysis on circuits in a large-signal periodic steady state..HBNOISE output insrc parameter_sweep [N1, N2, ..., NK ,+/-1]+ [LISTFREQ=(freq1 [freq2 ... freqN ]|none|all]) [LISTCOUNT=num ]+ [LISTFLOOR=val ] [LISTSOURCES=on|off].NOISERuns noise analysis in frequency domain..NOISE v(out ) vin [interval ] [listckt[=1|0]]+ [listfreq=freq1 [freq2 ... freqN ]|none|all]) [listcount=num ]+ [listfloor=val ] [listsources=1|0|yes|no]] [listtype=1|0].ALTERReruns a simulation using different parameters and data from a specified sequence or block. The .ALTER block can contain element commands and .AC, .ALIAS, .DATA, .DC, .DEL LIB, .HDL, .IC (initial condition), .INCLUDE, .LIB, .MODEL, .NODESET, .OP, .OPTION, .PARAM, .TEMP, .TF, .TRAN, and .VARIATION commands..ALTER title_string.DCPerforms DC analyses..DC var1 START=start1 STOP=stop1 STEP=incr1Parameterized Sweep.DC var1 start1 stop1 incr1 [SWEEP var2 type np start2 stop2].DC var1 START=[par_expr1] STOP=[par_expr2] STEP=[par_expr3]Data-Driven Sweep.DC var1 type np start1 stop1 [SWEEP DATA=datanm (Nums )].DC DATA=datanm [SWEEP var2 start2 stop2 incr2].DC DATA=datanm (Nums )Monte Carlo Analysis.DC var1 start1 stop1 incr1 [SWEEP MONTE=MCcommand ].DC MONTE=MCcommand.OPCalculates the operating point of the circuit..OP format_time format_time ... [interpolation].PARAMDefines parameters. Parameters are names that have associated numeric values or functions..PARAM ParamName = RealNumber | ‘AlgebraicExpression’ | DistributionFunction (Arguments ) | str(‘string’) | OPT xxx (initial_guess, low_limit, upper_limit )Monte Carlo Analysis.PARAM mcVar = UNIF(nominal_val , rel_variation [, multiplier ]) | AUNIF(nominal_val , abs_variation [, multiplier ])| GAUSS(nominal_val , rel_variation , num_sigmas [, multiplier ]) | AGAUSS(nominal_val , abs_variation , num_sigmas [, multiplier ]) | LIMIT(nominal_val , abs_variation ).STOREStarts creation of checkpoint files describing a running process during transient analysis..STORE [file=checkpoint_file ] [time=time1]+ [repeat=checkpoint_interval ].TEMPPerforms temperature analysis at specified temperatures..TEMP t1 [t2 t3 ...].TRANPerforms a transient analysis.Single-Point Analysis.TRAN tstep1 tstop1 [START=val ] [UIC]Multipoint Analysis.TRAN tstep1 tstop1 [tstep2 tstop2 ... tstepN tstopN ]+ RUNLVL =(time1 runlvl1 time2 runlvl2...timeN runlvlN )+ [START=val ] [UIC] [SWEEP var type np pstart pstop ]Monte Carlo Analysis.TRAN tstep1 tstop1 [tstep2 tstop2 ... tstepN tstopN ]+ [START=val ] [UIC] [SWEEP MONTE=MCcommand ]Invoking HSPICESimulation Modehspice [-i] input_file [-o [output_file ]] [-hpp] [-mt #num ][-gz] [-d] [-case][-hdl filename ] [-hdlpath pathname ] [-vamodel name ]Distributed-Processing Modehspice [-i] input_file [-o [output_file ]] -dp [#num ][-dpconfig [dp_configuration_file ]] [-dplocation [NFS|TMP][-merge]Measurement Modehspice -meas measure_file -i wavefile -o [output_file ]Help Modehspice [-h] [-doc] [-help] [-v]Argument Descriptions-i input_file Specifies the input netlist file name.-o output_file Name of the output file. HSPICE appends the extension .lis.-hpp Invokes HSPICE Precision Parallel.-mt #num Invokes multithreading and specifies the number of processors. Works best when -hpp is used.-gz Generates compression output on analysis results for these output types: .tr#, .ac#, .sw#, .ma#, .mt#, .ms#, .mc#, and .print*.-d (UNIX) Displays the content of .st0 files on screen while running HSPICE.-case Enable case sensitivity.-hdl filename Specifies a Verilog-A file.-hdlpath pathname Specifies the search path for Verilog-A files.-vamodel name Specifies the cell name for Verilog-A definitions.-dp #num -dpconfig dpconfig_file -dplocation [NFS|TMP] Invokesdistributed processing and specifies number of processes, the configuration file for DP, and the location of the output files.-merge Merge the output files in the distributed-processing mode.-meas measure_file Calculates new measurements from a previous simulation.-h Outputs the command line help message.-doc Opens the PDF documentation set for HSPICE (requires Adobe Acrobat Reader or other PDF document reader).-help Invokes the online help system (requires a Web browser).-v Outputs HSPICE version information.HSPICE is fully integrated with the Synopsys® Custom Compiler™ Simulation and Analysis Environment (SAE). See the Custom Compiler™ Simulation and Analysis Environment User Guide .To use the HSPICE integration to the Cadence® Virtuoso® Analog Design Environment, go to /$INSTALLDIR/interface/ and follow the README instructions.Analysis Commands.ACPerforms AC analyses.Single / Double Sweep.AC type np fstart fstop.AC type np fstart fstop [SWEEP var+ [START=]start [STOP=]stop [STEP=]incr ].AC type np fstart fstop [SWEEP var type np start stop ]Sweep Using Parameters.AC type np fstart fstop [SWEEP DATA=datanm (Nums )].AC DATA=datanm.AC DATA=datanm [SWEEP var [START=]start [STOP=]stop [STEP=]incr ].AC DATA=datanm [SWEEP var type np start stop ]Monte Carlo Analysis.AC type np fstart fstop [SWEEP MONTE=MCcommand ].LSTBInvokes loop stability analysis..LSTB [lstbname ] mode=[single|diff|comm + vsource=[vlstb |vlstbp,vlstbn ]Data-Driven Sweep.TRAN DATA=datanm.TRAN DATA=datanm [SWEEP var type np pstart pstop ].TRAN tstep1 tstop1 [tstep2 tstop2 ... tstepN tstopN ]+ [START=val ] [UIC] [SWEEP DATA=datanm (Nums )]Time Window-based Speed/Accuracy Tuning by RUNLVL.TRAN tstep tstop [RUNLVL=(time1 runlvl1...timeN runlvlN )]Circuit Block-based Speed/Accuracy Tuning by RUNLVL.TRAN tstep tstop+ [INST=inst_exp1 RUNLVL=(time11 runlvl11...time1N runlvl1N )]+ [SUBCKT=subckt_exp2 RUNLVL=(time21 runlvl21...time2N runlvl2N )]Time Window-based Temperature Setting.TRAN tstep tstop [tempvec=(t1 Temp1 t2 Temp2 t3 Temp3...)+[tempstep=val ]].TRANNOISEActivates transient noise analysis to compute the additional noise variables over a standard .TRAN analysis..TRANNOISE output [METHOD=MC] [SEED=val ] [SAMPLES=val ] [START=x ]+ [AUTOCORRELATION=0|1|off|on] [FMIN=val ] [FMAX=val ] [SCALE=val ]+ [PHASENOISE=0|1|2] [JITTER=0|1|2] [REF=srcName ] [PSD=0|1]HSPICE Options.OPTION opt1 [opt2 opt3 …]opt1 opt2 … Specify input control options.General OptionsALTCC=n Enables reading the input netlist once for multiple .ALTER statements. Default is 0.LIS_NEW=x Enables streamlining improvements to the *.lis file. Default is 0. SCALE=x Sets the element scaling factor. Default is 1.POSTTOP=n Outputs instances up to n levels deep. Default is 0.POSTLVL=n Limits data written to the waveform file to the level of nodes specified by n .POST=n Saves results for viewing by an interactive waveform viewer. Default is 0.PROBE=n Limits post-analysis output to only variables specified in .PROBE and .PRINTstatements. Default is 0.RC Reduction OptionsSIM_LA=name Starts linear matrix (RC) reduction to the PACT, PI, or LNE algorithm. Defaultis off.Transient OptionsAUTOSTOP=n Stops transient analysis after calculating all TRIG-TARG, FIND-WHEN, andFROM-TO measure functions. Default is 0.METHOD=name Sets numerical integration method for a transient analysis to GEAR, or TRAP(default), or BDF.RUNLVL=n Controls the speed and accuracy trade-off; where n can be 1 through 6. The higher the value, the greater the accuracy; the lower the value, the faster the simulation runtime. Default is 3.Variability and Monte Carlo Analysis.AC .DC .TRAN .MEASURE .MODEL .PARAM .ACMATCHCalculates the effects of variations on the AC transfer function, with one or more outputs..ACMatch Vm(n1) Vp(n1) Vr(n1) Vi(n1) Vm(n1,n2) Im(Vmeas ).DCMATCHCalculates the effects of variations on the DC operating point, with one or more outputs..DCMatch V(n1) V(n1,n2) I(Vmeas )。

Chapter 24: Using the Standalone SoftwareVENUE Standalone software lets you do all of the following to preconfigure performances, wherever you can use your lap-top:•Learn the basics of the VENUE software interface in prep-aration for working at a full VENUE system. •Assign hardware I/O and routing, and name channels.•Set channel input, EQ, dynamics, pan, and other set-tings. •Create and maintain a library of setups, with access to nearly all parameters available on the control surface. •Store and recall Snapshots, and configure Events.•Use the Filing features to transfer Shows, Shows Folders, and plug-in presets to/from a compatible USB storage de-vice to transfer data between the standalone software and VENUE.Differences Between Standalone Software and a VENUE SystemThe Standalone software is nearly identical to that on a full VENUE system, with the following differences:Audio ThroughputYou cannot play audio through the Standalone software. Real-time audio requires the VENUE hardware.Plug-In EditingWhen a Show is transferred from a complete VENUE system, all plug-ins installed on the D-Show system are visible in the Standalone software as offline (unavailable) plug-ins. You can assign offline plug-ins to racks, and assign plug-in rack routing in the Standalone software, and save the routing in snapshots.Hardware ConfigurationIn the Standalone software, you can simulate the hardware configuration of a destination system from the Devices tab of the Options page.System RequirementsThe following are the minimum system requirements for us-ing the VENUE Standalone software:•Computer running Windows XP Pro or XP HomeEdition O/S, Service Pack 1 (Macintosh not supported)•Minimum 1024 x 768 screen resolution•Minimum 16-bit color graphics, 32-bit recommended •Minimum 256 MB RAM, 512 MB recommended •Minimum 200 MB of available hard disk space, 512 MB recommended •CD-ROM drive for installation (unless installing from web-download)•Available USB 1.1 or 2.0 port and compatible USB storage device (such as a flash disk, key disk or other external hard drive) for file transfer Installation requires Windows Administrator permissions. Once installed, the software can be run under Admin or User accounts.Installing the Standalone SoftwareTo install the VENUE Standalone software:1 Do one of the following:•Download the VENUE Standalone Software Installer from the website ().– or –•Insert your VENUE Software Installer into the CD-ROM drive on your Windows XP-compatible computer.2 Launch the installer and follow the instructions on-screen.The VENUE Standalone software requires no authorization.Removing the Standalone SoftwareTo remove the VENUE Standalone software:1 Launch the Add/Remove Programs Control Panel.2 Choose VENUE , then follow the instructions on-screen.Transferring data must be done to/from a compatible USB storage device such as a USB key disk or other external USB hard drive.You cannot install plug-ins or adjust plug-in parametersunless you are working on the complete VENUE system.Simulating a VENUE ConfigurationYou can use the Standalone software to simulate a VENUE sys-tem with any number of input and outputs. The correspond-ing inputs and outputs become available in the Patchbay, al-lowing you to prepare a show that can transfer directly to the destination system.To simulate a VENUE system:1 Launch the Standalone software.2 Go to the Options page and click the Devices tab.3 Right-click the console graphic and choose the type of con-sole you will be working with.4 Right-click an I/O graphic and choose the type of I/O (as available) and specify the number of Input and Output cards on the destination system.Transfer and Filing Quick StartThe basic steps for using the Standalone software and data transfer are as follows:•Save data to disk, then transfer it to an external USB storage device.•Transfer data from the USB device, then load the data. Save and Transfer Data from aVENUE SystemTo save and transfer data from the complete system:1 Connect a USB storage device to a VENUE USB port.2 Use the Save tab of the Filing page to save VENUE data to disk.3 Go to the Filing page and click the Transfer tab.4 Do one of the following to select the type of data to transfer:•To transfer all data, click the Console icon.•To transfer Console Settings, click the Settings icon.•To transfer Show Folders, click the Show Folders icon.•To transfer individual Shows, click the Shows icon.•To transfer Preset Folders, click the Preset Folders i con.•To transfer Presets for individual items, click the Built-In icon or the Plug-In i con and choose a processor, plug-in or Input Channel Presets item from the pop-up menu, orclick the Scope Sets icon.5 In the left column, select the items you want to transfer from VENUE to the portable storage device.6 Click the Transfer button.Adding Stage Rack inputs and outputsFor complete instructions on transferring data, see Chapter20, “Shows and File Management.”Transferring Show files from VENUETransfer and Load Data to theStandalone Software1 Connect the USB storage device to your laptop. Make sure the drive is mounted before proceeding.2 Launch the VENUE standalone software.3 Go to the Filing page and click the Transfer tab.4 Make sure your USB disk is available in the list at right.5 Click the Console, Settings, Show Folders, Shows, Preset Fold-ers, Built-In, Plug-In or Scope Set selectors to select the type of data you want to transfer.6 Click the Transfer button. The data is transferred from the USB device to the appropriate VENUE data folders on the lap-top.7 If you chose Console, data is automatically loaded and ap-plied. If you chose any other data type, go to the Filing page and click the Load tab, and load the newly transferred data into the Standalone software.Creating and Editing Shows and PresetsUse the techniques explained throughout this guide to assign routing, rename channels, and to configure other parameters. Then do the following to save and transfer your work to a complete system.To save and transfer VENUE data from the standalone software to the complete system:1 Connect a USB storage device to an available USB port on your laptop.2 Using the Save tab of the Filing page, save data to disk.3 Go to the Filing page and click the Transfer tab, and transfer saved data to a compatible USB storage device.4 Connect the USB storage device to an available USB port on the complete system.5 Use the Transfer tab of the Filing page to transfer the VENUE data from the USB storage device.6 Use the Load tab of the Filing page to load the transferred data.CD TransferThe VENUE system provides a CD-ROM drive that can also be used as a source device for VENUE data transfer. (You cannot write data to the FOH Rack CD-ROM drive; it is read-only.)To use a CD for transfer:1 Using the Standalone software on a laptop or other com-puter, create and save a show.2 Locate the VENUE data folder on the system drive.3 Copy that folder and its contents to a CD-ROM. Make sure the folder is at the root level of the CD-ROM.4 Burn or write the disc as a Windows-compatible CD-ROM.5 Insert the CD-ROM into a VENUE CD-ROM drive.6 In the Filing screen, select the CD-ROM drive as the source for file transfer.7 When the transfer is complete, eject the CD-ROM.Transferring a Scope Set for the standalone softwareClickLeaving a disc in the CD-ROM drive of a VENUE systemcan slow down the response of some software screens, so itis recommended that you not leave any disc in the drive dur-ing a performance. This only applies to a VENUE CD-ROMdrive (not the laptop on which you’re running the stand-alone software).Exporting System Information and Patchbay InformationWith Standalone software, a complete system description and/or the contents of each Patchbay page can be exported to a text file. These can be useful for generating an input list (line list) directly from the system. For example, build and custom-ize the Patchbay for an upcoming show, then export and print the channel names list for use during sound check. To print a system description:1 Go to the Options > System tab.2 Click the Info button and follow the on-screen instructionsto print a complete system description.For more information, see “VENUE System Information Ex-port” on page 110. To export Patchbay names:1 Go to the Patchbay page you want to export.2 Click the Export Patch List icon in the upper right corner ofthe screen.The Patchbay names appear in an open HTML file that you can save and print, or open in an HTML-compatible applica-tion for formatting or other modification. For more informa-tion, see “Patch List Export” on page 111.Export Patch List buttonClick to export as HTML。

ViewPAC3VP-23W6/VP-25W6/VH-23W6/VH-25W6ViewPAC-2000 Series3VP-25W6VP-23W6 VH-25W6VH-23W6FeaturesHighlight InformationRuntime InduSoft Web Studio InsideISaGRAF Ver .3 SoftLogic Inside (IEC 61131-3) PXA270 CPU (32-bit & 520 MHz) 128 MB SDRAM & 96 MB Flash IP65 Compliant Front Panel3.5”/5.7” TFT LCD and Rubber KeypadAudio with Microphone-In and Earphone-Out 3 I/O Expansion Slots for VP-23W6/25W6 One or two 10/100M Ethernet Ports 2 or 3 Serial Ports (RS-232, RS-485) DCON Bundle Driver is ProvidedProtocol Support: MODBUS, OPC DDE, SNMP …etc. Supports IEC 61131-3 Standard PLC Programming LanguagesHost Application via Regular Web Browser Operating Temperature: -20 ~ +70 °CSoftwareHardwareWindows CE .NET 5.0 Operating System FTP Server VCEP SoftwareBuilt-in OPC Server: QuickerProvides Library for eVC, C# or VB .NET InduSoft Web Studio v6.1 InsideFull-Featured WinCE-based run-time environment Conform to Industry Standards: OPC, DDE, SNMP . Full-Featured web Thin Client solution ISaGRAF Ver .3 SoftLogicEasy Integrating to HMI/SACDA/MMI Support CAN/CANopen (via I-7530W) Support Ebus Data ExchangeSupport Modbus Master & Slave Protocols Support FRnet I/O (via I-8172W) Support Wireless Communication & SMS Development Software InduSoft Web Studio ISaGRAF Ver .3 SoftLogicVisual Studio .NET 2003/2005/2008 and eVCPXA270 CPU (32-bit & 520 MHz)IP65 Compliant Front Panel3.5”/2.7” TFT LCD (5.7” LCD is with Touch Panel) Rubber Keypad with 24/6 KeysAudio with Microphone-In and Earphone-Out 3 Slots for High Pro fi le I/O Modules (VP Series) 64-bit Hardware Serial Number for Software Protection Built-in Flash Disk (31 MB)Dual Battery Backup SRAM (512 KB) Rich I/O Expansion Ability Ethernet RS-232/422/485 FRnetCAN BusOperating Temperature: -20 ~ +70 °CIntroductionApplicationsVP-23W6/25W6 and VH-23W6/25W6 series are the new generation Windows CE .NET 5.0based InduSoft and ISaGRAF PACs of ICP DAS. ViewPAC combines WinPAC, color graphic display and keypad in one unit. It is equipped with a PXA270 CPU (520 MHz), various connectivity (USB, Ethernet, RS-232/485), 3 I/O slots, 3.5”/5.7” TFT LCD and a rubber keypad. ViewPAC has hard real-time capability, small core size, fast boot speed, interrupt handling at a deeper level and achievable deterministic control by running Windows CE .NET 5.0 operating system.InduSoft Web Studio is a powerful, integrated collection of automation tools that includes all the building blocks needed to develop modern Human Machine Interfaces (HMI), Supervisory Control and Data Acquisition (SCADA) systems, and ViewPAC applications. ISaGRAF is the most powerful SoftLogic package on the market. ISaGRAF is a PLC-like software and it supports IEC 61131-3 standard PLC programming languages ( LD, FBD, SFC, ST , IL, FC), and can run the application generated by the workbench on any ISaGRAF PACs.AudioAudioET-7000ET-7000CAN/CANopen DevicesI-7530CAN busRS-232I/O SlotsI-8K/I-87K High Pro fi le SeriesFR-2000I-8172WFR I/O ModuleM-7000M-7000I-7000I-7000ET-7000ET-7000RU-87PnRU-87PnRS-485RS-485Slot FRnetEthernetEthernetVH-2000VP-2000I-8KE4-MTCPI-8KE8-MTCP I-8KE4-MTCPI-8KE8-MTCP NS-205NS-205CAN/CANopen DevicesI-7530CAN busRS-232ViewPAC3VP-23W6/VP-25W6/VH-23W6/VH-25W6ViewPAC-2000 SeriesViewPAC3VP-23W6/VP-25W6/VH-23W6/VH-25W6ViewPAC-2000 Series3Protocols (some protocols need optional devices)Modbus TCP/IP Master Link to max. 100 devices that support Standard Modbus TCP/IP Slave protocol (FAQ-113)Modbus RTU/ASCII Master Support Multi-port. Max. 10 ports: COM2, 3 and COM5 ~ 14 (Expansion boards must be plugged in slot 0 ~ 3)Modbus RTU Slave Max. 5 Ports: one of COM2/3, COM5 ~ 8.Modbus TCP/IP Slave Yes, up to 32 connections.Web HMI ProtocolEthernet Ports for connecting PC running Internet ExplorerI-7000 & I-87K RS-485 Remote I/O One of COM2 or COM3 I-7000 I/O modules, I-87K base + I-87K Serial I/O boards and RU-87Pn + I-87K High Pro fi le I/O boards as Remote I/O. Max. 255 modules for one controller .M-7000 Series Modbus I/O Max. 10 RS-485 ports (COM2, 3, 5 ~ 14) can support M-7000 I/O. Each port can connect up to 32 M-7000 Modules.Modbus TCP/IP I/O Support ICP DAS Ethernet I/O: I-8KE4-MTCP and I-8KE8-MTCP .FRnet I/O Max. 3 pcs. I-8172W boards in slot 0 to 2 to connect to FRnet I/O modules. Each I-8172w board can connect up to 256 DI plus 256 DO channels.Send Email Support functions to send email with one attached fi le via Ethernet port.EbusTo exchange data between ISaGRAF Ethernet PAC via Ethernet port. (LAN1 Port only)SMS: Short Message Service COM3 or COM5 can link to a GSM Modem to support SMS. User can request data/control the controller by cellular phone. The controller can also send data & alarms to user’s cellular phone.Optional GSM Modems: GTM-201-RS232 (850/900/1800/ 1900 GSM/ GPRS External Modem)User-De fi ned Protocol COM2, 3 and COM5 ~ COM14 by Serial communication function blocks MMICON/LCDCOM3 or COM5 supports ICP DAS’s MMICON.UDP Server & UDP Client :Exchange Message & Auto-Report Support UDP Server and UDP Client protocol to send/receive message to/from PC/HMI or other devices.TCP Client :Exchange Message & Auto-Report Support TCP Client protocol to send/receive message to/from PC/HMI or other devices which support TCP server protocol. Ex: automatically report data to InduSoft’s RXTX driver , or to connect a location camera.CAN/CANopenCOM3 or COM5 ~ COM14 can connect one I-7530 (Converter: RS-232 to CAN) to support CAN/CANopen devices and sensors. One VP-2xW7 supports max.10 RS-232 ports to connect max.10 I-7530.Counter , Encoder , FrequencyPWM OutputHigh Speed PWM ModuleI-8088W , 8-ch. PWM outputs, 10 Hz ~ 500 kHz (non-continuous), duty: 0.1 ~ 99.9%DO Moudle as PWM8-ch. max. 250 Hz max. For Off=2 & On=2 ms. Output square curve: Off: 2 ~ 32766 ms, On: 2 ~ 32766 ms.Optional DO Boards: I-8037W , 8041W , 8041AW , 8042W , 8050W , 8054W , 8055W , 8056W , 8057W , 8060W , 8063W , 8064W , 8068W , 8069W (Relay Output boards can not generate fast square pulse)Counter, Encoder, FrequencyParallel DI Counter8-ch. max. for 1 controller . Counter val: 32-bit. 250 Hz max. Min. ON & OFF width must > 2 ms. Optional DI Boards: I-8040W , 8040PW , 8042W , 8048W...Serial DI Counter Counter input: 100 Hz max. Counter value: 0 ~ 65535 (16-bit). Optional Serial I-87K DI Boards: I-87040W , 87046W , 87051W , 87052W , 87053W , 87054W , 87055W , 87058W , 87059W , 87063W.Remote DI CounterAll I-7K/I-87K DI modules support counters. 100 Hz max. Value: 0 ~ 65535High Speed CounterI-8084W: 250 kHz max. 32 bit I-87082W: 100 kHz max. 32 bit;I-87088W: 500 kHz max. 32 bitEncoderI-8093W : 3-axis Encoder Module, max. 1M Hz for quadrant input mode, max. 4 MHz for pulse/direction and cw/ccw input mode. (FAQ-112)I-8084W: 250 kHz max. , 4-ch encoder , can be dir/pulse, or up/down or A/B phase (Quad. mode), No support Encoder Z-index. (FAQ-100)FrequencyI-87082W: 2-ch, 1 Hz ~ 100 kHz;I-87088W: 8-ch, 0.1 Hz ~ 500 kHz;I-8084W: 8-ch, 1 Hz ~ 250 kHz;MotionMotion ControlWith one I-8091W (2-axis) or two I-8091W (4-axis), only one I-8091W can do X-Y dependent motion ISaGRAF Speci fi cationsViewPAC3VP-23W6/VP-25W6/VH-23W6/VH-25W6ViewPAC-2000 Series RS-232EthernetRS-485Appearance.G..G.RS-232EthernetRS-485LAN2• Elegant Graphics • Multi-Language• Database (Access, Excel, SQL, Oracle…)• Recipes and Reports• Online and History Alarm / Event / Trend• Various Communication Driver (DCON, Modbus, OPC, DDE, TCP/IP …)• Remote Web Client Control & Security• ActiveX (GSM / SHM / COM /WEB provided by ICP DAS)• System Redundancy • Online Con fi guration and debugging • Others (VBScript, E-mail, FTP , SNMP ...)ViewPAC3VP-23W6/VP-25W6/VH-23W6/VH-25W6ViewPAC-2000 Series123456789DCD TxD DTR RxD GNDRTS DSR CTS RI D+D-123456789DCD TxD DTR RxD GNDRTS DSR CTS RI D+D-123456789DCDTxD DTR RxD GNDRTS DSR CTS RIRecommended Panel Cut-Out Left Side View Right Side View Top View Bottom View Back View Front View Front View Dimensions (Unit: mm)Pin AssignmentsCOM2: RS-485COM1: RS-232COM3: RS-232COM3: RS-232COM2: RS-485Left Side View Right Side View Top ViewBottom ViewBack View Front ViewFront ViewRecommended Panel Cut-OutViewPAC3VP-23W6/VP-25W6/VH-23W6/VH-25W6ViewPAC-2000 Series Accessories。

Features•Single 2.7V - 3.6V Supply•Fast Read Access Time – 200 ns •Automatic Page Write Operation –Internal Address and Data Latches for 64 Bytes –Internal Control Timer •Fast Write Cycle Times–Page Write Cycle Time: 10 ms Maximum –1- to 64-byte Page Write Operation •Low Power Dissipation –15 mA Active Current–20 µA CMOS Standby Current•Hardware and Software Data Protection •DATA Polling for End of Write Detection •High Reliability CMOS Technology –Endurance: 10,000 Cycles –Data Retention: 10 Years•JEDEC Approved Byte-wide Pinout•Commercial and Industrial Temperature RangesDescriptionThe A T28BV256 is a high-performance Electrically Erasable and Programmable Read Only Memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufac-tured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 200 ns with power dissipation of just 54 mW. When the device is deselected, the CMOS standby current is less than 200 µA.PLCC – Top ViewPin ConfigurationsPin Name Function A0 - A14Addresses CE Chip Enable OE Output Enable WE Write Enable I/O0 - I/O7Data Inputs/Outputs NC No Connect DCDon’t ConnectPDIP , SOIC – Top ViewNote:1.Note: PLCC package pins 1 and 17are DON’T CONNECT.TSOP – Top View2AT28BV2560273H–PEEPR–10/04The AT28BV256 is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 64-byte page register to allow writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to 64 bytes of data are inter-nally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control write cycle has been detected a new access for a read or w rite c an begin.Atmel’s AT28BV256 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 64 bytes of EEPROM for device identifi-cation or tracking.Block DiagramAbsolute Maximum Ratings*Temperature under Bias ................................-55°C to +125°C *NOTICE:Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliabilityStorage Temperature.....................................-65°C to +150°C All Input Voltages (including NC Pins)with Respect to Ground...................................-0.6V to +6.25V All Output Voltageswith Respect to Ground.............................-0.6V to V CC + 0.6V Voltage on OE and A9with Respect to Ground...................................-0.6V to +13.5V3AT28BV2560273H–PEEPR–10/04Device OperationREAD:high, the data stored at the memory location determined by the address pins is asserted on This dual-line control gives designers flexibility in preventing bus contention in their system.BYTE WRITE:been started, it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of t WC , a read operation will effectively be a polling operation.PAGE WRITE: The page write operation of the AT28BV256 allows 1 to 64 bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 63 additional bytes. Each successive byte must be written within 150 µs (t BLC ) of the previous byte. If the t BLC limit is exceeded the AT28BV256 will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the during the page write operation, A6 - A14 must be the same.The A0 to A5 inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur.During a byte or page write cycle, an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been com-begin at anytime during the write cycle.TOGGLE BIT:determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle.DATA PROTECTION: If precautions are not taken, inadvertent writes may occur during transi-tions of the host system power supply. Atmel has incorporated both hardware and software features that will protect the memory against inadvertent writes.HARDWARE PROTECTION: Hardware features protect against inadvertent writes to the AT28BV256 in the following ways: (a) V CC power-on delay – once V CC has reached 1.8V (typ-ical) the device will automatically time out 10 ms (typical) before allowing a write; (b) write SOFTWARE DATA PROTECTION: A software-controlled data protection feature has been implemented on the AT28BV256. Software data protection (SDP) helps prevent inadvertent writes from corrupting the data in the device. SDP can prevent inadvertent writes during power-up and power-down as well as any other potential periods of system instability.The AT28BV256 can only be written using the software data protection feature. A series of three write commands to specific addresses with specific data must be presented to the device before writing in the byte or page mode. The same three write commands must begin each write operation. All software write commands must obey the page mode write timing4AT28BV2560273H–PEEPR–10/04specifications. The data in the 3-byte command sequence is not written to the device; the address in the command sequence can be utilized just like any other location in the device.Any attempt to write to the device without the 3-byte sequence will start the internal write tim-ers. No data will be written to the device; however, for the duration of t WC , read operations will effectively be polling operations.DEVICE IDENTIFICATION: An extra 64 bytes of EEPROM memory are available to the user for device identification. By raising A9 to 12V ± 0.5V and using address locations 7FC0H to 7FFFH the additional bytes may be written to or read from in the same manner as the regular memory array.Notes:1.X can be V IL or V IH .2.Refer to AC programming waveforms.3.V H = 12.0V ± 0.5V .DC and AC Operating RangeAT28BV256-20AT28BV256-25Operating Temperature (Case)Com.0°C - 70°C 0°C - 70°C Ind.-40°C - 85°C -40°C - 85°C V CC Power Supply2.7V -3.6V2.7V -3.6VOperating ModesMode CE OE WE I/O Read V IL V IL V IH D OUT Write (2)V IL V IH V IL D IN Standby/Write Inhibit V IH X (1)X High ZWrite Inhibit X X V IH Write Inhibit X V IL X Output Disable X V IH X High Z Chip Erase V ILV H (3)V ILHigh Z DC CharacteristicsSymbol Parameter ConditionMinMax Units I LI Input Load Current V IN = 0V to V CC + 1V 10µA I LO Output Leakage Current V I/O = 0V to V CC10µA I SB V CC Standby Current CMOS CE = V CC - 0.3V to V CC + 1V Com.20µA Ind.50µA I CC V CC Active Current f = 5 MHz; I OUT = 0 mA15mA V IL Input Low Voltage 0.6V V IH Input High Voltage 2.0V V OL Output Low Voltage I OL = 1.6 mA 0.3V V OHOutput High VoltageI OH = -100 µA2.0V5AT28BV2560273H–PEEPR–10/04AC Read Waveforms (1)(2)(3)(4)Notes:1.ACC - t CE after the address transition without impact on t ACC .2.OE may be delayed up to t CE - t OE after the falling edge of CE without impact on t CE or by t ACC - t OE after an address changewithout impact on t ACC .3.t DF is specified from OE or CE whichever occurs first (C L = 5 pF).4.This parameter is characterized and is not 100% tested.AC Read CharacteristicsSymbol ParameterAT28BV256-20AT28BV256-25Units MinMax MinMax t ACC Address to Output Delay 200250ns t CE (1)CE to Output Delay 200250ns t OE (2)OE to Output Delay 0800100ns t DF (3)(4)CE or OE to Output Float055060ns t OHOutput Hold from OE, CE or Address, whichever occurred first00ns6AT28BV2560273H–PEEPR–10/04Input Test Waveforms and Measurement LevelOutput Test LoadNote:1.This parameter is characterized and is not 100% tested.R F Pin Capacitancef = 1 MHz, T = 25°C (1)Symbol Typ Max Units Conditions C IN 46pF V IN = 0V C OUT 812pFV OUT = 0V7AT28BV2560273H–PEEPR–10/04Note:1.NR = No Restriction.AC Write WaveformsWE ControlledCE ControlledAC Write CharacteristicsSymbol ParameterMin MaxUnits t AS , t OES Address, OE Set-up Time 0ns t AH Address Hold Time 50ns t CS Chip Select Set-up Time 0ns t CH Chip Select Hold Time 0ns t WP Write Pulse Width (WE or CE)200ns t DS Data Set-up Time 50ns t DH , t OEH Data, OE Hold Time 0nst DV Time to Data Valid NR(1)8AT28BV2560273H–PEEPR–10/04Programming Algorithm (1)(2)(3)Notes:1.Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex).2.Data protect state will be re-activated at the end of program cycle.3. 1 to 64 bytes of data are loaded.Software Protected Program Cycle Waveforms (1)(2)(3)Notes:1.A0 - A14 must conform to the addressing sequence for the first three bytes as shown above.2.A6 through A14 must specify the same page address during each high to low transition of WE (or CE) after the softwarecode has been entered.3.OE must be high only when WE and CE are both low.Page Mode CharacteristicsSymbol Parameter MinMax Units t WC Write Cycle Time 10ms t AS Address Set-up Time 0ns t AH Address Hold Time 50ns t DS Data Set-up Time 50ns t DH Data Hold Time 0ns t WP Write Pulse Width 200ns t BLC Byte Load Cycle Time 150µs t WPHWrite Pulse Width High100ns9AT28BV2560273H–PEEPR–10/04Notes:1.These parameters are characterized and not 100% tested.2.See “AC Read Characteristics” on page 5.Notes:1.These parameters are characterized and not 100% tested.2.See “AC Read Characteristics” on page 5.Toggle Bit WaveformsNotes:1.2.Beginning and ending state of I/O6 will vary.3.Any address location may be used but the address should not vary.(1)Symbol Parameter Min TypMaxUnits t DH Data Hold Time 0ns t OEH OE Hold Time 0ns t OE OE to Output Delay (2)ns t WR Write Recovery TimensToggle Bit Characteristics (1)Symbol Parameter Min TypMaxUnits t DH Data Hold Time 10ns t OEH OE Hold Time 10ns t OE OE to Output Delay (2)ns t OEHP OE High Pulse 150ns t WR Write Recovery Time0ns10AT28BV2560273H–PEEPR–10/0411AT28BV2560273H–PEEPR–10/04Note: 1.See Valid Part Numbers table below.Ordering Information (1)t ACC (ns)I CC (mA)Ordering Code Package Operation Range Active Standby 200150.02A T28BV256-20JC A T28BV256-20PC A T28BV256-20SC A T28BV256-20TC 32J 28P628S 28T Commercial (0° to 70°C)150.02A T28BV256-20JI A T28BV256-20PI A T28BV256-20SI A T28BV256-20TI 32J 28P628S 28T Industrial (-40° to 85°C)150.02A T28BV256-20TU A T28BV256-20JU 32J Green 28T Green Industrial (-40° to 85°C)250150.02A T28BV256-25JC A T28BV256-25PC A T28BV256-20SC A T28BV256-25TC 32J 28P628S 28T Commercial (0° to 70°C)150.02A T28BV256-25JI A T28BV256-25PI A T28BV256-20SI A T28BV256-25TI32J 28P628S 28TIndustrial (-40° to 85°C)Valid Part NumbersThe following table lists standard Atmel products that can be ordered.Device Numbers Speed Package and Temperature Combinations AT28BV25620JC, JI, PC, PI, SC, SI, TC, TI, TU, JU AT28BV25625JC, JI, PC, PI, SC, SI, TC, TIDie ProductsReference Section: Parallel EEPROM Die ProductsPackage Type32J 32-lead, Plastic J-leaded Chip Carrier (PLCC)28P628-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)28S 28-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)28T28-lead, Plastic Thin Small Outline Package (TSOP)12AT28BV2560273H–PEEPR–10/04Packaging Information32J – PLCC13AT28BV2560273H–PEEPR–10/0428P6 – PDIP14AT28BV2560273H–PEEPR–10/0428S – SOIC15AT28BV2560273H–PEEPR–10/0428T – TSOP0273H–PEEPR–10/04Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABIL ITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBIL ITY OF SUCH DAMAGES. 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FEATURE OVERVIEWUsing TRACE32 for IEC 62304TRACE32 for IEC 62304 at a Glance• TRACE32 Tool Qualification Support-Kit streamlines TRACE32 tool qualification effort and costs.• TRACE32 TQSK is fully featured, field proven and ready to cover new use casesand requirements.• TRACE32 TQSK Customer Interface provides full support and service around tool qualification.• All test suites run in the target environment and are fully multicore aware.• Test Suite Coverage includes statement, decision, condition, function and call coverage, as well as MC/DC.• TRACE32 Instruction Simulator, TRACE32 Debug and Trace Tools, USB Debug and Trace provide comprehensive tool support throughout all project phases.Website-LinksTRACE32 Trusted Tools for Functional Safety /trusted_tools.htmlTQSK Customer Portal /register_tqsk.htmlTRACE32 Code Coverage /coverage.htmlTRACE32 Instruction Set Simulator /sim.htmlThe TRACE32 Tool Qualification Support-Kit (TQSK) provides everything needed to qualify use in safety-related software projects.Figure 1: The 2-stage qualification processCertification ArtifactsDocumentsTest SuiteTool Verification and Validation Supplement for Integration toOperational EnvironmentTest Suite DocumentsTest ReportTesting in Operational EnvironmentTest Report Testing inTSSTCTest Suite Simulator TriCore(paid)DSMDeveloper SafetyManualTSCTest Suite Coverage(free)TSDTest Suite Debug(free)$$TSSATest Suite Simulator Arm(paid)Test Suite SimulatorUpon customer request, Lauterbach also provides test suites for its Arm and TriCore Instruction Set Simulators. A qualified instruction set simulator is an accepted test environment in the software module testing phase of the project (see also figure 3) and offers the following advantages:• Product software qualification can start before product hardware is available.• The qualification of the product software can be well organized even in a distributed team, becauseeverything necessary is purely software-based.• If bottlenecks occur during this phase due to a lack of development hardware or debug/trace tools, additional test benches can be easily equipped with simulators.Test Suite DebugThe Test Suite Debug includes all basic debugging functionality such as target configuration, programming onchip and NOR flashes, loading programs, setting breakpoints and reading/writing of memory and variables.Figure 3: TRACE32 tool use in code coverage qualification。