Heteroepitaxial growth of high-K gate oxides on silicon insights from first-principles calc

第 32 卷第 10 期Vol.32，No.10129-1402023 年 10 月草业学报ACTA PRATACULTURAE SINICA李想，张梦，刘春增，等. 等离子体处理对紫云英种子萌发和生理特性的影响. 草业学报， 2023， 32（10）： 129−140.LI Xiang，ZHANG Meng，LIU Chun-zeng，et al. Effects of dialectric barrier discharge plasma treatment on seed germination and physiological characteristics of Astragalus sinicus. Acta Prataculturae Sinica， 2023， 32（10）： 129−140.等离子体处理对紫云英种子萌发和生理特性的影响李想1，张梦2，刘春增2，朱益飞3，叶晓馨1*（1.安徽大学资源与环境工程学院，安徽合肥 230601；2.河南省农业科学院植物营养与资源环境研究所，河南郑州 450002；3.空军工程大学航空工程学院，陕西西安 710038）摘要：为打破紫云英种子硬实，提高种子活力和发芽一致性，本研究以赣紫75-3-51和信紫1号为供试材料，采用室内发芽试验探讨了不同剂量等离子体处理（7、8、9 kV电压分别处理1、3、5、10 min）对紫云英种子活力、幼苗生长、抗氧化酶活性以及渗透调节物质含量的影响，以期为紫云英种子播前处理技术提供参考。

结果表明：等离子体处理对2种紫云英种子的发芽率和发芽势没有显著影响，但提高了紫云英种子活力。

不同品种紫云英对等离子体处理的响应存在差异。

等离子体处理对赣紫75-3-51生长存在低促高抑的现象，幼苗鲜重以及胚芽长度均随处理时间增加呈单峰曲线变化。

信紫1号幼苗鲜重在高剂量（9 kV处理10 min）等离子体处理条件下显著降低，较对照降低了20.5%。

摘 要凝固组织对铸件的性能有重要影响，对凝固组织的控制研究，过去一般采用物理实验的方法，浪费了大量的人力和物力，实验周期长，使得该方法在实际应用中的范围受到了一定限制。

随着金属凝固理论的日益完善以及计算机技术在材料科学、冶金学上应用的迅猛发展，使得计算机技术对凝固组织进行准确的模拟成为可能。

本文建立了有限元（Finite Element）和元胞自动机法（Cellular Automaton）相结合的宏微观耦合的CA-FE模型，采用有限元法（FE）计算宏观温度场，元胞自动机法（CA）计算微观凝固组织形成，与宏观传热进行耦合。

在微观计算中，形核计算采用了基于高斯分布的连续形核模型，生长计算采用了扩展的KGT模型，使其适用范围由二元合金扩展至多元合金。

应用CA-FE模型模拟了Al-Si合金的三维凝固组织，并进行了热态验证实验，应用修正的数学模型模拟并分析了原始成分、形核参数、浇注条件和铸模对凝固组织的影响。

研究结果表明：（1）模拟结果能够较为准确地反映出等轴晶和柱状晶的分布位置、比例和大小，并能较好描述凝固过程中晶粒生长情况，说明CA-FE模型是模拟凝固组织的有效模型；（2）降低原始成分Si含量以及提高过冷度是有利于柱状晶的发展，而增大形核密度是有利于等轴晶的发展，且能细化晶粒；（3）提高浇注温度，凝固组织中柱状晶增多，且晶粒明显变得粗大，而铸模外界冷却强度对铸件凝固组织的影响不大；（4）增大铸模厚度和使用冷却能力强的铸模都将使凝固组织中柱状晶比例增大，当使用冷却能力差的硅砂模时，凝固组织没有柱状晶而全为等轴晶。

关键词：有限元；元胞自动机法；数值模拟；凝固组织；等轴晶；柱状晶AbstractSolidification structure has an important influence on the performance of casting. In the past, the method of physical experiment was applied to the research of controling the solidification structure generally, however, a great deal of time and efforts should be put while using this method. so it is limited in the practical application. With the improvement of metal solidification theory and the rapid development of computer technology used in materials science and metallurgy, it has become possible to simulate the solidification structure accurately with computer technology.The CA-FE model was built through coupling the finite element and cellular automaton method. The finite element method was used to calculate macro temperature, and the cellular automaton method was used to simulate solidification microstructure with coupling the macro temperature calculation. In microstructure simulation, the nucleation adopts the continuous nucleation model based on Gaussian distribution, and the growth adopt the extended KGT model which fit complex alloy expanded from binary alloy. The three-dimensional solidification structures of Al-Si alloy was simulated by CA-FE model with hot verification test. In addition, the effects of primitive composition, nucleation parameters, casting conditions and the mold on solidification structures were analysised.The results show as follows:(1) The simulated results can accurately reflect the distribution, proportion, size of equiaxed grain and columnar grain，and can describe the grain growth well in the solidification process, so the CA-FE model is a effective model to simulate the solidification structure.(2) Reducing primitive composition of Si element and increasing undercooling are conducive to the development of columnar grains, but increasing nucleation density is conducive to the development of equiaxed grains, and can fine grains.(3) Raising the casting temperature, the proportion of columnar grain will increase, and the grains become coarse obviously，but the effect of the cooling intensity outside the mold on solidification structure is slight.(4) Enlarging the thickness of the mold or using the mold with strong cooling capacity, the proportion of columnar grain will increase. While using the Silica Sand mold with weak cooling capacity, the solidification structure were composed with all equiaxed grains and without columnar grain.Key words：finite element; cellular automaton; numerical simulation; solidification structure;equiaxed grain; columnar grain目 录第一章文献综述 (1)1.1 引言 (1)1.2 凝固组织的形成与控制 (2)1.2.1 铸件的凝固组织 (2)1.2.2 凝固组织的形成及影响因素 (3)1.2.3 凝固组织对铸件性能的影响 (4)1.2.4 凝固组织的控制 (5)1.3 凝固组织模拟的研究方法 (7)1.3.1 确定性方法(Deterministic Method) (7)1.3.2 随机性（概率）方法( Stochastic Method) (8)1.3.3 相场法(Phase field Method) (10)1.3.4 三种方法的对比 (11)1.4 凝固组织数值模拟的国内外研究进展 (12)1.4.1 国外研究 (12)1.4.2 国内研究 (15)1.4.3 存在问题及今后发展趋势 (16)1.5 本文所研究的主要工作 (17)第二章铸件凝固过程宏微观耦合模型 (19)2.1 宏观温度场计算模型 (19)2.1.1 热传递的基本方式 (19)2.1.2 热传导微分方程 (20)2.1.3 瞬态温度场的有限元解法 (21)2.2 微观动力学模型 (23)2.2.1 形核模型 (23)2.2.2 枝晶尖端动力学模型 (26)2.3 耦合计算模型 (29)2.3.1 耦合计算流程 (29)2.3.2 凝固潜热处理 (31)2.3.3 固相分数的确定 (32)2.4 本章小结 (33)第三章数学模型的计算与验证 (34)3.1 实验 (34)3.1.1 实验材料 (34)3.1.2 实验设备 (34)3.1.3 实验步骤 (35)3.1.4 实验结果 (35)3.2 数值模拟过程 (35)3.2.1 网格划分 (35)3.2.2 热物性参数 (35)3.2.3 初始条件 (36)3.2.4 边界条件 (37)3.2.5 生长系数 (37)3.2.6 形核参数 (38)3.3 模拟结果及分析 (38)3.3.1 模拟结果 (38)3.3.2 柱状晶生长 (40)3.3.3 中心等轴晶生长 (42)3.4 本章小结 (43)第四章 AL-SI合金凝固组织的数值模拟与分析 (44)4.1 原始成分对凝固组织的影响 (44)4.2 形核参数对凝固组织的影响 (45)4.2.1 过冷度对凝固组织的影响 (45)4.2.2 形核密度对凝固组织的影响 (46)4.3 浇注条件对凝固组织的影响 (47)4.3.1 浇注温度对凝固组织的影响 (47)4.3.2 外界冷却强度对凝固组织的影响 (49)4.4 铸模对凝固组织的影响 (50)4.4.1 铸模厚度对凝固组织的影响 (50)4.4.2 铸模材料对凝固组织的影响 (52)4.5 本章小结 (53)第五章：结论 (54)参考文献 (55)致谢 (58)附录：发表的论文 (59)第一章文献综述1.1 引言众所周知，决定铸件产品机械性能的最本质因素是铸件内部晶粒在宏观上的几何形态，即铸件的凝固组织结构，包括晶粒的形貌、大小、取向和分布等情况。

Semiconductor Manufacturing Technology半导体制造技术Instructor’s ManualMichael QuirkJulian SerdaCopyright Prentice HallTable of Contents目录OverviewI. Chapter1. Semiconductor industry overview2. Semiconductor materials3. Device technologies—IC families4. Silicon and wafer preparation5. Chemicals in the industry6. Contamination control7. Process metrology8. Process gas controls9. IC fabrication overview10. Oxidation11. Deposition12. Metallization13. Photoresist14. Exposure15. Develop16. Etch17. Ion implant18. Polish19. Test20. Assembly and packagingII. Answers to End-of-Chapter Review QuestionsIII. Test Bank (supplied on diskette)IV. Chapter illustrations, tables, bulleted lists and major topics (supplied on CD-ROM)Notes to Instructors:1)The chapter overview provides a concise summary of the main topics in each chapter.2)The correct answer for each test bank question is highlighted in bold. Test bankquestions are based on the end-of-chapter questions. If a student studies the end-of-chapter questions (which are linked to the italicized words in each chapter), then they will be successful on the test bank questions.2Chapter 1Introduction to the Semiconductor Industry Die:管芯 defective:有缺陷的Development of an Industry•The roots of the electronic industry are based on the vacuum tube and early use of silicon for signal transmission prior to World War II. The first electronic computer, the ENIAC, wasdeveloped at the University of Pennsylvania during World War II.•William Shockley, John Bardeen and Walter Brattain invented the solid-state transistor at Bell Telephone Laboratories on December 16, 1947. The semiconductor industry grew rapidly in the 1950s to commercialize the new transistor technology, with many early pioneers working inSilicon Valley in Northern California.Circuit Integration•The first integrated circuit, or IC, was independently co-invented by Jack Kilby at Texas Instruments and Robert Noyce at Fairchild Semiconductor in 1959. An IC integrates multiple electronic components on one substrate of silicon.•Circuit integration eras are: small scale integration (SSI) with 2 - 50 components, medium scale integration (MSI) with 50 – 5k components, large scale integration (LSI) with 5k to 100kcomponents, very large scale integration (VLSI) with 100k to 1M components, and ultra large scale integration (ULSI) with > 1M components.1IC Fabrication•Chips (or die) are fabricated on a thin slice of silicon, known as a wafer (or substrate). Wafers are fabricated in a facility known as a wafer fab, or simply fab.•The five stages of IC fabrication are:Wafer preparation: silicon is purified and prepared into wafers.Wafer fabrication: microchips are fabricated in a wafer fab by either a merchant chip supplier, captive chip producer, fabless company or foundry.Wafer test: Each individual die is probed and electrically tested to sort for good or bad chips.Assembly and packaging: Each individual die is assembled into its electronic package.Final test: Each packaged IC undergoes final electrical test.•Key semiconductor trends are:Increase in chip performance through reduced critical dimensions (CD), more components per chip (Moore’s law, which predicts the doubling of components every 18-24 months) andreduced power consumption.Increase in chip reliability during usage.Reduction in chip price, with an estimated price reduction of 100 million times for the 50 years prior to 1996.The Electronic Era•The 1950s saw the development of many different types of transistor technology, and lead to the development of the silicon age.•The 1960s were an era of process development to begin the integration of ICs, with many new chip-manufacturing companies.•The 1970s were the era of medium-scale integration and saw increased competition in the industry, the development of the microprocessor and the development of equipment technology. •The 1980s introduced automation into the wafer fab and improvements in manufacturing efficiency and product quality.•The 1990s were the ULSI integration era with the volume production of a wide range of ICs with sub-micron geometries.Career paths•There are a wide range of career paths in semiconductor manufacturing, including technician, engineer and management.2Chapter 2 Characteristics of Semiconductor MaterialsAtomic Structure•The atomic model has three types of particles: neutral neutrons（不带电的中子）, positively charged protons（带正电的质子）in the nucleus and negatively charged electrons（带负电的核外电子） that orbit the nucleus. Outermost electrons are in the valence shell, and influence the chemical and physical properties of the atom. Ions form when an atom gains or loses one or more electrons.The Periodic Table•The periodic table lists all known elements. The group number of the periodic table represents the number of valence shell electrons of the element. We are primarily concerned with group numbers IA through VIIIA.•Ionic bonds are formed when valence shell electrons are transferred from the atoms of one element to another. Unstable atoms (e.g., group VIIIA atoms because they lack one electron) easily form ionic bonds.•Covalent bonds have atoms of different elements that share valence shell electrons.3Classifying Materials•There are three difference classes of materials:ConductorsInsulatorsSemiconductors•Conductor materials have low resistance to current flow, such as copper. Insulators have high resistance to current flow. Capacitance is the storage of electrical charge on two conductive plates separated by a dielectric material. The quality of the insulation material between the plates is the dielectric constant. Semiconductor materials can function as either a conductor or insulator.Silicon•Silicon is an elemental semiconductor material because of four valence shell electrons. It occurs in nature as silica and is refined and purified to make wafers.•Pure silicon is intrinsic silicon. The silicon atoms bond together in covalent bonds, which defines many of silicon’s properties. Silicon atoms bond together in set, repeatable patterns, referred to asa crystal.•Germanium was the first semiconductor material used to make chips, but it was soon replaced by silicon. The reasons for this change are:Abundance of siliconHigher melting temperature for wider processing rangeWide temperature range during semiconductor usageNatural growth of silicon dioxide•Silicon dioxide (SiO2) is a high quality, stable electrical insulator material that also serves as a good chemical barrier to protect silicon from external contaminants. The ability to grow stable, thin SiO2 is fundamental to the fabrication of Metal-Oxide-Semiconductor (MOS) devices. •Doping increases silicon conductivity by adding small amounts of other elements. Common dopant elements are from trivalent, p-type Group IIIA (boron) and pentavalent, n-type Group VA (phosphorus, arsenic and antimony).•It is the junction between the n-type and p-type doped regions (referred to as a pn junction) that permit silicon to function as a semiconductor.4Alternative Semiconductor Materials•The alternative semiconductor materials are primarily the compound semiconductors. They are formed from Group IIIA and Group VA (referred to as III-V compounds). An example is gallium arsenide (GaAs).•Some alternative semiconductors come from Group IIA and VIA, referred to as II-VI compounds. •GaAs is the most common III-V compound semiconductor material. GaAs ICs have greater electron mobility, and therefore are faster than ICs made with silicon. GaAs ICs also have higher radiation hardness than silicon, which is better for space and military applications. The primary disadvantage of GaAs is the lack of a natural oxide.5Chapter 3Device TechnologiesCircuit Types•There are two basic types of circuits: analog and digital. Analog circuits have electrical data that varies continuously over a range of voltage, current and power values. Digital circuits have operating signals that vary about two distinct voltage levels – a high and a low.Passive Component Structures•Passive components such as resistors and capacitors conduct electrical current regardless of how the component is connected. IC resistors are a passive component. They can have unwanted resistance known as parasitic resistance. IC capacitor structures can also have unintentional capacitanceActive Component Structures•Active components, such as diodes and transistors can be used to control the direction of current flow. PN junction diodes are formed when there is a region of n-type semiconductor adjacent to a region of p-type semiconductor. A difference in charge at the pn junction creates a depletion region that results in a barrier voltage that must be overcome before a diode can be operated. A bias voltage can be configured to have a reverse bias, with little or no conduction through the diode, or with a forward bias, which permits current flow.•The bipolar junction transistor (BJT) has three electrodes and two pn junctions. A BJT is configured as an npn or pnp transistor and biased for conduction mode. It is a current-amplifying device.6• A schottky diode is formed when metal is brought in contact with a lightly doped n-type semiconductor material. This diode is used in faster and more power efficient BJT circuits.•The field-effect transistor (FET), a voltage-amplifying device, is more compact and power efficient than BJT devices. A thin gate oxide located between the other two electrodes of the transistor insulates the gate on the MOSFET. There are two categories of MOSFETs, nMOS (n-channel) and pMOS (p-channel), each which is defined by its majority current carriers. There is a biasing scheme for operating each type of MOSFET in conduction mode.•For many years, nMOS transistors have been the choice of most IC manufacturers. CMOS, with both nMOS and pMOS transistors in the same IC, has been the most popular device technology since the early 1980s.•BiCMOS technology makes use of the best features of both CMOS and bipolar technology in the same IC device.•Another way to categorize FETs is in terms of enhancement mode and depletion mode. The major different is in the way the channels are doped: enhancement-mode channels are doped opposite in polarity to the source and drain regions, whereas depletion mode channels are doped the same as their respective source and drain regions.Latchup in CMOS Devices•Parasitic transistors can create a latchup condition(???????) in CMOS ICs that causes transistors to unintentionally（无心的） turn on. To control latchup, an epitaxial layer is grown on the wafer surface and an isolation barrier（隔离阻障）is placed between the transistors. An isolation layer can also be buried deep below the transistors.Integrated Circuit Productsz There are a wide range of semiconductor ICs found in electrical and electronic products. This includes the linear IC family, which operates primarily with anal3og circuit applications, and the digital IC family, which includes devices that operate with binary bits of data signals.7Chapter 4Silicon and Wafer Preparation8z Semiconductor-Grade Silicon•The highly refined silicon used for wafer fabrication is termed semiconductor-grade silicon (SGS), and sometimes referred to as electronic-grade silicon. The ultra-high purity of semiconductor-grade silicon is obtained from a multi-step process referred to as the Siemens process.Crystal Structure• A crystal is a solid material with an ordered, 3-dimensional pattern over a long range. This is different from an amorphous material that lacks a repetitive structure.•The unit cell is the most fundamental entity for the long-range order found in crystals. The silicon unit cell is a face-centered cubic diamond structure. Unit cells can be organized in a non-regular arrangement, known as a polycrystal. A monocrystal are neatly arranged unit cells.Crystal Orientation•The orientation of unit cells in a crystal is described by a set of numbers known as Miller indices.The most common crystal planes on a wafer are (100), (110), and (111). Wafers with a (100) crystal plane orientation are most common for MOS devices, whereas (111) is most common for bipolar devices.Monocrystal Silicon Growth•Silicon monocrystal ingots are grown with the Czochralski (CZ) method to achieve the correct crystal orientation and doping. A CZ crystal puller is used to grow the silicon ingots. Chunks of silicon are heated in a crucible in the furnace of the puller, while a perfect silicon crystal seed is used to start the new crystal structure.• A pull process serves to precisely replicate the seed structure. The main parameters during the ingot growth are pull rate and crystal rotation. More homogeneous crystals are achieved with a magnetic field around the silicon melt, known as magnetic CZ.•Dopant material is added to the melt to dope the silicon ingot to the desired electrical resistivity.Impurities are controlled during ingot growth. A float-zone crystal growth method is used toachieve high-purity silicon with lower oxygen content.•Large-diameter ingots are grown today, with a transition underway to produce 300-mm ingot diameters. There are cost benefits for larger diameter wafers, including more die produced on a single wafer.Crystal Defects in Silicon•Crystal defects are interruptions in the repetitive nature of the unit cell. Defect density is the number of defects per square centimeter of wafer surface.•Three general types of crystal defects are: 1) point defects, 2) dislocations, and 3) gross defects.Point defects are vacancies (or voids), interstitial (an atom located in a void) and Frenkel defects, where an atom leaves its lattice site and positions itself in a void. A form of dislocation is astacking fault, which is due to layer stacking errors. Oxygen-induced stacking faults are induced following thermal oxidation. Gross defects are related to the crystal structure (often occurring during crystal growth).Wafer Preparation•The cylindrical, single-crystal ingot undergoes a series of process steps to create wafers, including machining operations, chemical operations, surface polishing and quality checks.•The first wafer preparation steps are the shaping operations: end removal, diameter grinding, and wafer flat or notch. Once these are complete, the ingot undergoes wafer slicing, followed by wafer lapping to remove mechanical damage and an edge contour. Wafer etching is done to chemically remove damage and contamination, followed by polishing. The final steps are cleaning, wafer evaluation and packaging.Quality Measures•Wafer suppliers must produce wafers to stringent quality requirements, including: Physical dimensions: actual dimensions of the wafer (e.g., thickness, etc.).Flatness: linear thickness variation across the wafer.Microroughness: peaks and valleys found on the wafer surface.Oxygen content: excessive oxygen can affect mechanical and electrical properties.Crystal defects: must be minimized for optimum wafer quality.Particles: controlled to minimize yield loss during wafer fabrication.Bulk resistivity(电阻系数): uniform resistivity from doping during crystal growth is critical. Epitaxial Layer•An epitaxial layer (or epi layer) is grown on the wafer surface to achieve the same single crystal structure of the wafer with control over doping type of the epi layer. Epitaxy minimizes latch-up problems as device geometries continue to shrink.Chapter 5Chemicals in Semiconductor FabricationEquipment Service Chase Production BayChemical Supply Room Chemical Distribution Center Holding tank Chemical drumsProcess equipmentControl unit Pump Filter Raised and perforated floorElectronic control cablesSupply air ductDual-wall piping for leak confinement PumpFilterChemical control and leak detection Valve boxes for leak containment Exhaust air ductStates of Matter• Matter in the universe exists in 3 basic states (宇宙万物存在着三种基本形态): solid, liquid andgas. A fourth state is plasma.Properties of Materials• Material properties are the physical and chemical characteristics that describe its unique identity.• Different properties for chemicals in semiconductor manufacturing are: temperature, pressure andvacuum, condensation, vapor pressure, sublimation and deposition, density, surface tension, thermal expansion and stress.Temperature is a measure of how hot or cold a substance is relative to another substance. Pressure is the force exerted per unit area. Vacuum is the removal of gas molecules.Condensation is the process of changing a gas into a liquid. Vaporization is changing a liquidinto a gas.Vapor pressure is the pressure exerted by a vapor in a closed container at equilibrium.Sublimation is the process of changing a solid directly into a gas. Deposition is changing a gas into a solid.Density is the mass of a substance divided by its volume.Surface tension of a liquid is the energy required to increase the surface area of contact.Thermal expansion is the increase in an object’s dimension due to heating.Stress occurs when an object is exposed to a force.Process Chemicals•Semiconductor manufacturing requires extensive chemicals.• A chemical solution is a chemical mixture. The solvent is the component of the solution present in larger amount. The dissolved substances are the solutes.•Acids are solutions that contain hydrogen and dissociate in water to yield hydronium ions. A base is a substance that contains the OH chemical group and dissociates in water to yield the hydroxide ion, OH-.•The pH scale is used to assess the strength of a solution as an acid or base. The pH scale varies from 0 to 14, with 7 being the neutral point. Acids have pH below 7 and bases have pH values above 7.• A solvent is a substance capable of dissolving another substance to form a solution.• A bulk chemical distribution (BCD) system is often used to deliver liquid chemicals to the process tools. Some chemicals are not suitable for BCD and instead use point-of-use (POU) delivery, which means they are stored and used at the process station.•Gases are generally categorized as bulk gases or specialty gases. Bulk gases are the relatively simple gases to manufacture and are traditionally oxygen, nitrogen, hydrogen, helium and argon.The specialty gases, or process gases, are other important gases used in a wafer fab, and usually supplied in low volume.•Specialty gases are usually transported to the fab in metal cylinders.•The local gas distribution system requires a gas purge to flush out undesirable residual gas. Gas delivery systems have special piping and connections systems. A gas stick controls the incoming gas at the process tool.•Specialty gases may be classified as hydrides, fluorinated compounds or acid gases.Chapter 6Contamination Control in Wafer FabsIntroduction•Modern semiconductor manufacturing is performed in a cleanroom, isolated from the outside environment and contaminants.Types of contamination•Cleanroom contamination has five categories: particles, metallic impurities, organic contamination, native oxides and electrostatic discharge. Killer defects are those causes of failure where the chip fails during electrical test.Particles: objects that adhere to a wafer surface and cause yield loss. A particle is a killer defect if it is greater than one-half the minimum device feature size.Metallic impurities: the alkali metals found in common chemicals. Metallic ions are highly mobile and referred to as mobile ionic contaminants (MICs).Organic contamination: contains carbon, such as lubricants and bacteria.Native oxides: thin layer of oxide growth on the wafer surface due to exposure to air.Electrostatic discharge (ESD): uncontrolled transfer of static charge that can damage the microchip.Sources and Control of Contamination•The sources of contamination in a wafer fab are: air, humans, facility, water, process chemicals, process gases and production equipment.Air: class number designates the air quality inside a cleanroom by defining the particle size and density.Humans: a human is a particle generator. Humans wear a cleanroom garment and follow cleanroom protocol to minimize contamination.Facility: the layout is generally done as a ballroom (open space) or bay and chase design.Laminar airflow with air filtering is used to minimize particles. Electrostatic discharge iscontrolled by static-dissipative materials, grounding and air ionization.Ultrapure deiniozed (DI) water: Unacceptable contaminants are removed from DI water through filtration to maintain a resistivity of 18 megohm-cm. The zeta potential represents a charge on fine particles in water, which are trapped by a special filter. UV lamps are used for bacterial sterilization.Process chemicals: filtered to be free of contamination, either by particle filtration, microfiltration (membrane filter), ultrafiltration and reverse osmosis (or hyperfiltration).Process gases: filtered to achieve ultraclean gas.Production equipment: a significant source of particles in a fab.Workstation design: a common layout is bulkhead equipment, where the major equipment is located behind the production bay in the service chase. Wafer handling is done with robotic wafer handlers. A minienvironment is a localized environment where wafers are transferred on a pod and isolated from contamination.Wafer Wet Cleaning•The predominant wafer surface cleaning process is with wet chemistry. The industry standard wet-clean process is the RCA clean, consisting of standard clean 1 (SC-1) and standard clean 2 (SC-2).•SC-1 is a mixture of ammonium hydroxide, hydrogen peroxide and DI water and capable of removing particles and organic materials. For particles, removal is primarily through oxidation of the particle or electric repulsion.•SC-2 is a mixture of hydrochloric acid, hydrogen peroxide and DI water and used to remove metals from the wafer surface.•RCA clean has been modified with diluted cleaning chemistries. The piranha cleaning mixture combines sulfuric acid and hydrogen peroxide to remove organic and metallic impurities. Many cleaning steps include an HF last step to remove native oxide.•Megasonics(兆声清洗) is widely used for wet cleaning. It has ultrasonic energy with frequencies near 1 MHz. Spray cleaning will spray wet-cleaning chemicals onto the wafer. Scrubbing is an effective method for removing particles from the wafer surface.•Wafer rinse is done with overflow rinse, dump rinse and spray rinse. Wafer drying is done with spin dryer or IPA(异丙醇) vapor dry (isopropyl alcohol).•Some alternatives to RCA clean are dry cleaning, such as with plasma-based cleaning, ozone and cryogenic aerosol cleaning.Chapter 7Metrology and Defect InspectionIC Metrology•In a wafer fab, metrology refers to the techniques and procedures for determining physical and electrical properties of the wafer.•In-process data has traditionally been collected on monitor wafers. Measurement equipment is either stand-alone or integrated.•Yield is the percent of good parts produced out of the total group of parts started. It is an indicator of the health of the fabrication process.Quality Measures•Semiconductor quality measures define the requirements for specific aspects of wafer fabrication to ensure acceptable device performance.•Film thickness is generally divided into the measurement of opaque film or transparent film. Sheet resistance measured with a four-point probe is a common method of measuring opaque films (e.g., metal film). A contour map shows sheet resistance deviations across the wafer surface.•Ellipsometry is a nondestructive, noncontact measurement technique for transparent films. It works based on linearly polarized light that reflects off the sample and is elliptically polarized.•Reflectometry is used to measure a film thickness based on how light reflects off the top and bottom surface of the film layer. X-ray and photoacoustic technology are also used to measure film thickness.•Film stress is measured by analyzing changes in the radius of curvature of the wafer. Variations in the refractive index are used to highlight contamination in the film.•Dopant concentration is traditionally measured with a four-point probe. The latest technology is the thermal-wave system, which measures the lattice damage in the implanted wafer after ion implantation. Another method for measuring dopant concentration is spreading resistance probe. •Brightfield detection is the traditional light source for microscope equipment. An optical microscope uses light reflection to detect surface defects. Darkfield detection examines light scattered off defects on the wafer surface. Light scattering uses darkfield detection to detectsurface particles by illuminating the surface with laser light and then using optical imaging.•Critical dimensions (CDs) are measured to achieve precise control over feature size dimensions.The scanning electron microscope is often used to measure CDs.•Conformal step coverage is measured with a surface profiler that has a stylus tip.•Overlay registration measures the ability to accurately print photoresist patterns over a previously etched pattern.•Capacitance-voltage (C-V) test is used to verify acceptable charge conditions and cleanliness at the gate structure in a MOS device.Analytical Equipment•The secondary-ion mass spectrometry (SIMS) is a method of eroding a wafer surface with accelerated ions in a magnetic field to analyze the surface material composition.•The atomic force microscope (AFM) is a surface profiler that scans a small, counterbalanced tip probe over the wafer to create a 3-D surface map.•Auger electron spectroscopy (AES) measures composition on the wafer surface by measuring the energy of the auger electrons. It identifies elements to a depth of about 2 nm. Another instrument used to identify surface chemical species is X-ray photoelectron spectroscopy (XPS).•Transmission electron microscopy (TEM) uses a beam of electrons that is transmitted through a thin slice of the wafer. It is capable of quantifying very small features on a wafer, such as silicon crystal point defects.•Energy-dispersive spectrometer (EDX) is a widely used X-ray detection method for identifying elements. It is often used in conjunction with the SEM.• A focused ion beam (FIB) system is a destructive technique that focuses a beam of ions on the wafer to carve a thin cross section from any wafer area. This permits analysis of the wafermaterial.Chapter 8Gas Control in Process ChambersEtch process chambers••The process chamber is a controlled vacuum environment where intended chemical reactions take place under controlled conditions. Process chambers are often configured as a cluster tool. Vacuum•Vacuum ranges are low (rough) vacuum, medium vacuum, high vacuum and ultrahigh vacuum (UHV). When pressure is lowered in a vacuum, the mean free path(平均自由行程) increases, which is important for how gases flow through the system and for creating a plasma.Vacuum Pumps•Roughing pumps are used to achieve a low to medium vacuum and to exhaust a high vacuum pump. High vacuum pumps achieve a high to ultrahigh vacuum.•Roughing pumps are dry mechanical pumps or a blower pump (also referred to as a booster). Two common high vacuum pumps are a turbomolecular (turbo) pump and cryopump. The turbo pump is a reliable, clean pump that works on the principle of mechanical compression. The cryopump isa capture pump that removes gases from the process chamber by freezing them.。

基于人工神经网络和遗传算法的普鲁兰酶重组大肠杆菌高密度发酵工艺优化迟 雷，王静雨，侯俊超，魏佳佳，魏 涛，胡晓龙，何培新*（郑州轻工业大学食品与生物工程学院，河南 郑州450000）摘 要：基于人工神经网络和遗传算法，对重组大肠杆菌（Escherichia coli ）BL 21表达热稳定普鲁兰酶的高密度发酵工艺进行优化。

在5 L 的发酵罐中，通过比较不同发酵温度、pH 值及培养基碳氮比（C /N ，mol /mol ）对细胞量和产物产量的影响，确定最佳发酵工艺。

结果表明，诱导前适合细胞生长的发酵条件为发酵温度34.4 ℃、pH 6.87、培养基C /N 6.1；诱导后适合产物表达的发酵条件为发酵温度32.5 ℃、pH 6.69、培养基C /N 5.3，最终获得细胞质量浓度56.5 g /L ，重组蛋白产量3.21 g /L ，酶活力为268.3 U /mL 。

关键词：重组普鲁兰酶；神经网络；遗传算法；高密度发酵Artificial Neural Network-Genetic Algorithm-Based Optimization of High Cell Density Cultivation ofRecombinant Escherichia coli for Producing PullulanaseCHI Lei, WANG Jingyu, HOU Junchao, WEI Jiajia, WEI Tao, HU Xiaolong, HE Peixin *(School of Food and Bioengineering, Zhengzhou University of Light Industry, Zhengzhou 450000, China)Abstract: In this study, the high cell density cultivation of recombinant Escherichia coli BL 21 for the production of a novel thermostable pullulanase was optimized using artificial neural network and genetic algorithm. The effects of culture temperature, medium pH, and carbon-to-nitrogen (C /N) molar ratio were tested in a 5 L bioreactor. The results suggested that the optimal culture conditions before the induction phase were as follows: temperature 34.4 ℃, pH 6.87 and C /N ratio 6.1, and the optimal culture conditions after induction were 32.5 ℃, pH 6.69 and 5.3 C /N ratio. The maximum biomass, protein concentration and pullulanase activity obtained under these conditions were 56.5 g /L, 3.21 g /L and 268.3 U /mL, respectively.Keywords: recombinant pullulanase; neural network; genetic algorithm; high cell density cultivation DOI:10.7506/spkx1002-6630-20200101-006中图分类号：Q815 文献标志码：A 文章编号：1002-6630（2021）10-0073-06引文格式：迟雷, 王静雨, 侯俊超, 等. 基于人工神经网络和遗传算法的普鲁兰酶重组大肠杆菌高密度发酵工艺优化[J]. 食品科学, 2021, 42(10): 73-78. DOI:10.7506/spkx1002-6630-20200101-006. CHI Lei, WANG Jingyu, HOU Junchao, et al. Artificial neural network-genetic algorithm-based optimization of high cell density cultivation of recombinant Escherichia coli for producing pullulanase[J]. Food Science, 2021, 42(10): 73-78. (in Chinese with English abstract) DOI:10.7506/spkx1002-6630-20200101-006. 收稿日期：2020-01-01基金项目：国家自然科学基金青年科学基金项目（31801535）；河南省重大科技专项（181100211400）；河南省教育厅科技创新人才项目（18HASTIT040）；郑州轻工业大学博士科研启动基金项目（2013BSJJ004）第一作者简介：迟雷（1983—）（ORCID: 0000-0002-7824-2785），男，副教授，博士，研究方向为发酵工程。

1032023.19 / Urban and Rural Planning and Design 城乡规划·设计益主体涉及广、建设项目数量多、开发建设周期长，其前瞻谋划和规划实施工作在新时期高质量发展要求下面临更大的挑战，也更迫切需要对工作转型方向与制度创新路径进行探索。

近年来，各地城市结合自身实际开展了丰富的城市重点地区建设实践，在规划建设管理各个环节已积累了较为成熟的经验，但由于规划决策与行为的分散性，各阶段参与主体缺乏整体统筹意识，大多呈现碎片化多头推进状态，造成实际推进效果与城市高品质建设预期仍有差距。

在此背景下，基于我国现有的规划体系特征及广州在重点功能片区的规划探索实践，思考并总结有效适用于城市重点地区全流程规划建设管理的工作路径要点，对当前城市建设发展具有重要的现实意义。

2当前城市重点地区规划建设中的重难点研判城市重点地区，通常指城市战略规划、国民经济和社会发展规划等确定必须重点推进城市规划的建设开发区域，包括重要的城市商业商务区、产业功能集聚区及特色发展地区等。

城市重点地区在城市发展战略中一般被赋予了更高的发展定位、更高的空间品质、更高的建设效率的期许，其规划建设管理因高强度空间开发、高运转建设周期、多维度主体诉求及财务成本压力叠加面临严峻的挑战。

2.1空间维度：高效集约的空间资源利用土地是重要的生产资料，城市重点地区的土地更具有稀缺性。

有限的土地资源、高昂的再开发成本，驱使城市空间向高强度、高密度方向演进，间接导致人、地、产等客观要素及技术逻辑的矛盾高度集聚在有限的土地载体上。

由于单位面积更小的土地承载更多的空间发展需求，需在有限的空间里处理好自然资源、历史文脉与现代开发之间的矛盾，对跨专业设计协调及后期建设施工管理等方面带来新的更大的挑战。

如商务区内部小街区、密路网的摘要 研究探讨了在新时期城市建设由高增量转向高质量发展的背景下，城市重点地区规划建设环节中存在的难点和痛点，如高效集约的空间资源利用、精明紧凑的开发建设周期、多元复杂的利益主体诉求、理想空间范式与现实经济性的平衡取舍考量等，并基于广州市重点功能片区的规划实践，指出建立伴随式与成长型的地区规划、空间组织与开发建设机制的意义，进而从顶层设计、详细规划、城市设计、土地开发等环节，总结提出全生命周期管理视角下的规划建设工作要点，以期为超大、特大城市重点地区的高质量发展提供路径指引与模式借鉴。

高速生长CVD金刚石单晶及应用王启亮，吕宪义，成绍恒，张晴，李红东*，邹广田(吉林大学超硬材料国家重点实验室，长春 130012 )Email: hdli@摘要：本文简要地介绍了近年来国内外CVD金刚石单晶的高速生长和应用进展。

我们的实验中，采用微波等离子体化学气相沉积（CVD）方法，同质外延高速生长金刚石单晶，通过改变反应腔压强、反应气氛（在CH4/H2中引入氮气N2、二氧化碳CO2、氧气O2、）等，调制单晶生长速率、质量、颜色、表面粗糙度、光谱等特性。

利用高温氢等离子体进行退火，可使金刚石单晶的颜色有了很大的改善。

我们研制了CVD金刚石单晶刀具，用于金属材料的曲面镜面加工。

关键词：高速生长；CVD；金刚石单晶；退火；金刚石工具High-rate Growth of CVD Single-crystal Diamond and Application WANG Qi-liang, LV Xian-yi, CHENG Shao-heng, ZHANG-Qing,LI Hong-dong*, ZOU Guang-tian(State Key Laboratory of Superhard Materials, Jilin University, Changchun 130012) Abstract: In this paper, we briefly review the resent great improvements achieved for the high rate growth and applications of CVD single-crystal diamonds (SCDs). We have investigated the high rate homoepitaxial growth of SCDs dependent on reaction pressure, atmosphere (introducing the gaseous N2, O2, and/or CO2in H2/CH4) by microwave plasma CVD. The growth rate, the quality, color, surface roughness, and photoluminescence properties are efficiently controlled. Annealing by hydrogen plasma, the color of the SCDs has been great improved. We developed a CVD SCD cutter using for the curved mirror face polishing of metallic material.Keywords: High-rate growth; CVD; Single-crystal diamond; Annealing; Diamond cutter1 引言金刚石是已知自然界中最硬的材料，具有很多优异的特性，如：宽带隙、低的介电常数、室温下最高的热导率、极低的热膨胀系数和极佳的化学稳定性等等，是一种非常重要的功能材料，在微电子、光电子、生物医学、机械、航空航天和核能等高新技术领域中具有很好的应用前景，特别是金刚石单晶，由于其缺陷少、品质高，在某些应用领域具有不可替代的作用。

··凝固过程中，固-液界面的生长形貌是影响合金组织性能以及缺陷形成的重要因素。

Al-Si 合金具有优异的铸造性能，良好的力学性能及其他物理化学性能，是研究和应用最为广泛的铸造铝合金，占铝铸件产量的85%~90%，且适用于各种铸造方法。

大多数的铸造缺陷往往出现在合金凝固的最后阶段，而铝硅共晶体是铝硅合金凝固最后阶段的主要组织，铝硅共晶体的生长形态是影响合金性能的重要因素。

20世纪60年代，Kim 和Heine [1]对变质和未变质共晶铝硅合金的凝固模式进行了研究，发现变质合金中共晶体倾向于从铸件表层向中心生长，而未变质合金中共晶体在熔体中沿任意方向生长。

A.K.Dahle 等[2-7]对铝硅合金共晶凝固形核与生长进行了大量研究，发现未变质A356合金中有独立形核的共晶团且大部分α-Al 共晶体和树枝状α-Al 晶体取向一致，说明先析出α-Al 相是共晶体有效形核核心；另外还发现未变质工业铝硅合金中共晶体的形核是充分的，而未变质高纯铝硅合金中只有很少共晶团形成。

加入Sr 后，工业铝硅合金中形核率降低，而对高纯铝硅合金无明显影响。

蔡惠民和孙伟成等[8-10]对共晶凝固的机制及组织形态进行了研究，发现凝固条件不同得到的硅晶体形貌差别很大。

然而，他们的研究重点都是共晶组织的微观形成机制，探讨共晶组织中α-Al 相和Si 相的生长形态和相互关系，而没有当成一个整体来研究共晶体的生长形态。

铝硅合金凝固后期往往是共晶体的凝固过程，也是合金中微孔大量形成的阶段，本文研究了不同凝固条件下共晶体的生长形态，这将对研究铝合金中微孔的形成有重大的理论意义和应用价值。

由于凝固过程中固液界面形貌演化是一个涉及热量、质量和动量传输，以及界面动力学和毛细作用效应的自由边界问题，这一问题的复杂性造成目前在试验研究和理论分析上存在许多障碍，故在一黄婉如，廖恒成，吴申庆，孙国雄（东南大学材料科学与工程学院，江苏南京211189）摘要：对Al-13Si-0.2Sr-0.35Mg 合金进行了一系列单向凝固实验，研究了界面前沿温度梯度G L 和生长速度R 对铝硅合金共晶生长形态的影响。

第32卷第4期航空航天医学杂志2021年4月453 .综述.N G F通过激活PI3K/A k t信号通路在视网膜M iille r细胞增殖和分化中的作用谢敏刘涛*[摘要]PI3K/A kt信号通路是信号转导网络的重要组成部分，参与了诸多重要的生理过程和对环境变化的应 激反应。

大量的研究表明神经生长因子（NGF)和Miiller细胞的活性在黄斑裂孔的修复中起重要作用。

Muller细胞（又称放射状胶质细胞）是神经视网膜的主要肢质细胞，跨越整个视网膜厚度，在支持神经元存活和信息处理 方面发挥着丰富的关键作用，负责视网膜的结构稳定。

激活的Muller•细胞可合成和分泌大量NGF，N G F与其受 体酪氨酸激酶（TrkA)可以介导下游PI3K/Akt信号通路的激活，促进Miiller细胞的增殖以及向感光细胞的分化。

因此，研究旨在针对NGF对PI3K/A k t信号通路在视网膜Miiller细胞中的作用作一综述。

[关键词]神经生长因子；Miiller细胞去分化；Miiller细胞增殖；PI3K/A k t信号通路[中图分类号]R774.5 [文献标识码]A [文章编号]2095 -1434.2021.04.040Model NGF by Activating PI3K/Akt Signaling Pathway in the Role of Retinal Muller Cells Proliferation and Differentiation/XIE Min, LIU Tao//(A r/ r an Medical College Graduate)L Abstract」The PI3K/Akt signaling pathway is an important part of the signal transduction network, and it participates in many important physiological processes and stress responses to environmental changes. A large number of studies have shown that the activity of nerve growth factor ( NGF) and Muller cells play an important role in the repair of macular holes. Muller cells (also known as radial glial cells) are the main glial cells of the neural retina, span the entire thickness of the retina, play a rich key role in supporting neuron survival and information processing, and are responsible for the structural stability of the retina. Activated Muller cells can synthesize and secrete a large amount of NGF. NGF anrl its receptor tyrosine kinase ( TrkA) can mediate the activation of the downstream PI3K/Akt signaling pathway, promote the proliferation of Muller cells and the differentiation into photoreceptor cells. Therefore, this study aims to review the effects of NGF on the PI3K/Akt signaling pathway in Miiller cells of the retina.[Key words ] Nerve Growth Factor；Muller Cell Dedifferentiation；Muller Cell Proliferation；PI3K/Akt Signaling Pathway特发性黄斑裂孔（idiopathic macular hole,IMH)是指发 病原因不明的黄斑区视网膜神经上皮层组织缺损，表现为 视力下降、视物变形和中央暗点:|]，该病年发病率为每10 万人中7.8例目前治疗IM H的常规术式为玻璃体切 除联合内界膜剥除术。