瑞萨用户手册附加文档

WizPro200Nx（有数量控制功能） 编程器使用说明(For 瑞萨系列MCU)版本 1.01本烧写器支持的芯片：1.1Renesas Flash MCU R8C系列、M32C系列MCU，支持序列号功能。

序列号为4个字节长度，其在Flash中存放的地址可由用户通过PC应用程序随意设定，同时序列号的初始值和累加量也由用户自己随意设定；2特点：2.1支持瑞萨(Renesas) R8Cxx系列MCU，包括：R8Cxxx、M16Cxx、M32Cxx系列等；2.2支持UART编程接口；2.3支持3.3V和5.0V接口电平；2.4支持裸片烧写或在板烧写（In-Circuit-Program、On-Board-Program）；2.5支持脱机烧写，烧写时无需连接电脑，方便生产线使用；2.6USB通讯接口，方便连接电脑的连接；2.7自动编程优化，编程速度快；2.8支持序列号的设定，地址任意选择；2.9支持烧写数量控制功能（针对方案开发公司该功能可以控制客户烧写的芯片数量，而保证方案公司的利益；2.10操作简单，单键触发，蜂鸣器和LED提示烧写的结果；2.11支持USB在线升级Firmware，便于器件的更新和扩展；2.12可整合成1拖n的烧写平台，满足大批量生产的需要；3外观接口图：4指示灯和蜂明器：2.1 电源指示灯：编程器接通电源后指示灯点亮，表示电源正常；2.2 状态指示灯（红色和蓝色LED灯）：2.2.1：编程器通过USB连接到电脑时，打开编程器的PC软件时蓝色和红色的LED灯点亮，同时蜂鸣器响2次长声；2.2.2 编程器下载程序后接上电源时：¾红色和蓝色指示灯交替闪烁：表示系统正进行内部数据校验；¾红色灯亮同时蜂鸣器响2次长声：表示系统内部数据校验失败，须连接电脑重新下载 程序才可正常烧写；¾蓝色灯亮同时蜂鸣器响1次长声；表示系统内部数据校验成功，可以开始烧写芯片；¾蜂鸣器长响1声（约1秒钟）：说明编程器内部的Firmware有问题，需到我司网站下载 最新的Firmware或联络我司（我司网址：）2.2.3 编程器完成校验后开始编程时：¾蓝色红色指示灯交替闪烁，表示编程器正在对目标芯片进行编程器；¾红色灯亮同时蜂鸣器响3次短声：表示对目标芯片编程器失败，请作相应检查；¾蓝色灯亮同时蜂鸣器响1次长声：表示对目标芯片编程成功；5按键和接口说明：5.1白色按键：编程器按键，按一下按键系统就开始对目标芯片编程；5.2电源接口：接9～12V DC Adapter,>300mA即可，随机配有一个DC电源适配器；5.3USB接口：用于进行下载程序或在线编程以及编程器内部数据的更新和设定；5.4编程接口：用于对MCU进行编程，排线中箭头指向的一端的为第一脚，注意排线的插入方向（有防呆设计）。

CXD5602 User ManualContentsContents (2)Figure Contents (7)Table Contents (14)1Introduction (40)1.1Introduction (40)1.2Notation (40)1.2.1Notation of numerical value (40)2CXD5602 Outline (42)2.1Introduction (42)2.2Features (42)2.3Block Diagram (45)2.4Architecture Overview (46)2.5CPU Processor (47)2.5.1Application Processor (47)2.5.2System and I/O Processor (47)2.6Memory Mapping (49)2.6.1Memory Map of Each Block (50)2.6.2Main Memory (51)2.6.3System Memory (52)2.6.4Backup Memory (52)2.7Clock and Reset (52)2.7.1Overview (52)2.7.2Clock Architecture (55)2.8Power Management (57)2.8.1Overview (57)2.8.2Power Domain (57)2.8.3Power Supply States (60)3Function Details (62)3.1I/O Configuration (62)3.1.1Outline (62)3.1.2Function List (62)3.1.3Switching between HOST I/F Select Function and SWD Function (63)3.1.4Pin Multiplexer (64)3.2General Purpose Input/Output (GPIO) (95)3.2.1Outlines and Features (95)3.2.2Function List (95)3.2.3Function Specification Outlines (96)3.2.4Detailed Function and Control Specification (98)3.3Interrupt (121)3.3.1Overview and Features (121)3.3.2Register Descriptions (122)3.4PMU (Power Management Unit) (125)3.4.1Features and Overview (125)3.4.2Register List (135)3.4.3Register Descriptions (137)3.4.4Power Supply Control Flow (149)3.4.5Power Supply Control Example (163)3.5Clock and Reset (Clock Reset Generator) (167)3.5.1Overview (167)3.5.2Clock Scheme for CRG (167)3.5.3Analog Circuits (169)3.5.4Clock Setting Confirmation (172)3.5.5Power Domain Reset (175)3.5.6Reset by WDT (176)3.6RTC (179)3.6.1Outlines and Features (179)3.6.2Clock Input (180)3.6.3Function List (181)3.6.4Function Block Diagrams (181)3.6.5Detailed Function and Control Specification (184)3.7I2C (222)3.7.1Overview (222)3.7.2Features (225)3.7.3Functional description (226)3.7.4List of Registers (250)3.8DMAC (278)3.8.1Overview and Features (278)3.8.2Function Descriptions (278)3.8.3SDMAC (280)3.8.4HDMAC (283)3.8.5SYDMAC (285)3.8.6SYSUBDMAC (286)3.8.7ADMAC (287)3.8.8IDMAC (289)3.9SCU (Sensor Control Unit) (301)3.9.1SCU Overview and Features (301)3.9.2SCU Block Diagram (303)3.9.3Memory Map (304)3.9.4Clock Control (307)3.9.5Power Supply Control (313)3.9.6Interrupt (313)3.9.7MATH_PROC processing (318)3.9.8FIFO (328)3.9.9Sequencers (334)3.9.10DMA (356)3.9.11PWM (358)3.9.12SCU Register Details (369)3.9.13SCU Control Sequence (870)3.9.14Error Handling (914)3.9.15Restrictions (915)3.10SPI (930)3.10.1Overview and Features (930)3.10.2SPI0 (932)3.10.3SPI3 (933)3.10.4SPI4 (934)3.10.5SPI5 (936)3.10.6List of Registers (937)3.11UART (949)3.11.1Overview and Features (949)3.11.2UART1 (950)3.11.3UART2 (952)3.11.4List of Registers (953)3.12GNSS (965)3.13APP (967)3.13.1Function Overview (967)3.13.2Power Supply Control (970)3.13.3Clock Reset Control (971)3.13.4Description of APP_DSP Function (982)3.14SYSIOP Clock and Reset Control (1007)3.14.1Function Overiew (1007)3.14.2Power Supply Control (1010)3.14.3Clock and Reset Control (1011)3.15Audio Codec (1029)3.15.1Audio Codec Overview and Features (1029)3.15.2Audio Codec Block Diagram (1030)3.15.3Clock Supply (1035)3.15.4Standalone Operation (without the CXD5247) (1035)3.15.5External Interfaces (1036)3.15.6Details of Audio Codec Control Registers (1038)3.15.7Status Register (1083)3.15.8Interrupt Flag (1087)3.15.9Audio Codec Control Register List (1090)3.15.10Control Sequence (1106)3.16SDIO (1112)3.17eMMC (1112)3.18USB (1112)3.18.1Overview (1113)3.18.2Configuration Parameters (1118)3.18.3Theory of Operation (1124)3.18.4DMA Mode (1124)3.18.5Slave-Only Mode (1128)3.18.6Control and Status Registers (1131)3.18.7Slave-Only Operation (1172)3.18.8DMA Operation (1181)3.18.9Application Bus Protocol (Slave-Only Mode) (1201)3.18.10Application Bus Protocol (DMA Mode) (1203)3.18.11Software Implementation Guidelines (1205)3.18.12USB Programming (1211)3.18.13Multiple RxFIFO Controllers (1233)3.19CIS I/F (1238)3.202D Graphics (1238)3.21ADC (1239)3.21.1ADC Overview (1239)3.21.2ADC Block Diagram (1240)3.21.3Memory Map (1240)3.21.4Power Supply Control (1241)3.21.5Clock Control (1242)3.21.6Reset Control (1245)3.21.7Interrupt (1245)3.21.8FIFO writing Process (1245)3.21.9Gain Control (1246)3.21.10Performance Estimation (1248)3.21.11Synchronization Function with PWM (1249)3.21.12ADC Control Register Details (1249)3.21.13ADC Control Sequence (1285)3.21.14Restrictions (1285)3.21.15Error Handling (1286)4Appendix (1287)4.1Words and Terms (1287)4.1.1Words and Terms Used in This User Manual (1287)4.2Reference (1289)Revision History (1290)Figure ContentsFigure Block Diagram-1 CXD5602 Block Diagram (45)Figure Memory Mapping-2 Memory Map of the SYSIOP, GNSS, and APP (49)Figure Clock and Reset-3 Clock Diagram (56)Figure Power Management-4 Power Domain Layers (57)Figure Power Management-5 CXD5602 Power Domain (58)Figure Power Management-6 Changes of Power Supply States (61)Figure I/O Configuration-7 Switching between HOST I/F Function and SWD Function (63)Figure I/O Configuration-8 Visualized Function inside IOCELL Controlled by IOCELL Control Register (75)Figure I/O Configuration-9 Examples of Assigning Roles to the Pin (P1r_02) (79)Figure I/O Configuration-10 PMIC_INT Signal Routes (MODE=1) (81)Figure I/O Configuration-11 PMIC_INT Signal Routes (MODE=2 Open Drain) (82)Figure I/O Configuration-12 RTC_IRQ_OUT Signal Routes (MODE=2 Open Drain) (83)Figure I/O Configuration-13 SDIO CLK Input Schematic (91)Figure I/O Configuration-14 SDIO WP/CD Input Control Register Schematic (92)Figure General Purpose Input/Output (GPIO)-15 GPIO Overview Block Diagram (96)Figure General Purpose Input/Output (GPIO)-16 Diagram of GPIO Event Detect Block (97)Figure General Purpose Input/Output (GPIO)-17 Output Signal Route in the I/O Function Controlled by GPIO Parameter (100)Figure General Purpose Input/Output (GPIO)-18 Input Signal Route in the I/O Function Controlled by GPIO Parameter (101)Figure General Purpose Input/Output (GPIO)-19 GPIO Pin Selection (102)Figure General Purpose Input/Output (GPIO)-20 External Interrupt Selection (106)Figure General Purpose Input/Output (GPIO)-21 Event Detection Control (109)Figure General Purpose Input/Output (GPIO)-22 Event Detection Timing Diagram (112)Figure General Purpose Input/Output (GPIO)-23 Connection Diagram of Event Detection and SYSCPU or DSP (117)Figure General Purpose Input/Output (GPIO)-24 Time Interval for a Signal to be able to Detect an Event Again (PMU_WAKE_TRIG_NOISECUTEN0:0) (120)Figure Interrupt-25 Interrupt Connection Diagram (121)Figure PMU (Power Management Unit)-26 PMU and the Power Domain Layers (125)Figure PMU (Power Management Unit)-27 Individual Power Supply Control within the Power Domains (127)Figure PMU (Power Management Unit)-28 Power Supply Control within the Power Domain (PWD_APP Main Memory) (128)Figure PMU (Power Management Unit)-29 Changes of Power Supply States (130)Figure PMU (Power Management Unit)-30 Overall Block Diagram of the PMU (133)Figure PMU (Power Management Unit)-31 PMU Clock System (134)Figure PMU (Power Management Unit)-32 Sleep/Wakeup Control Flow of the Application Processor (166)Figure Clock and Reset (Clock Reset Generator)-33 CRG Control Area within Overall Clock Scheme (168)Figure Clock and Reset (Clock Reset Generator)-34 CRG Clock Scheme (168)Figure RTC-35 RTC0/1 Power Supply Framework (179)Figure RTC-36 Clock Resources of RTC (181)Figure RTC-37 RTC Block Diagram (182)Figure RTC-38 RTC (Time Update) Block Diagram (183)Figure I2C-39 I2C0/I2C1 Clock and Reset System (223)Figure I2C-40 I2C2 Clock and Reset System (224)Figure I2C-41 Master/Slave and Transmitter/Receiver Relationships (227)Figure I2C-42 Data transfer on the I2C Bus (228)Figure I2C-43 START and STOP Condition (229)Figure I2C-44 7-bit Address Format (230)Figure I2C-45 10-bit Address Format (230)Figure I2C-46 Master-Transmitter Protocol (231)Figure I2C-47 Master-Receiver Protocol (231)Figure I2C-48 START BYTE Transfer (232)Figure I2C-49 IC_DATA_CMD Register if IC_EMPTYFIFO_HOLD_MASTER_EN = 0 (233)Figure I2C-50 Master Transmitter Tx FIFO Becomes Empty if IC_EMPTYFIFO_HOLD_MASTER_EN=0 (233)Figure I2C-51 Master Receiver Tx FIFO Becomes Empty if IC_EMPTYFIFO_HOLD_MASTER_EN=0 (234)Figure I2C-52 IC_DATA_CMD Register if IC_EMPTYFIFO_HOLD_MASTER_EN = 1 (234)Figure I2C-53 Master Transmitter Tx FIFO Empties/STOP Generation if IC_EMPTYFIFO_HOLD_MASTER_EN=1 (235)Figure I2C-54 Master Receiver Tx FIFO Empties/STOP Generation if IC_EMPTYFIFO_HOLD_MASTER_EN=1 (235)Figure I2C-55 Master Transmitter Restart Bit of IC_DATA_CMD is set (IC_EMPTYFIFO_HOLD_MASTER_EN=1) (236)Figure I2C-56 Master Receiver Restart Bit of IC_DATA_CMD is set (IC_EMPTYFIFO_HOLD_MASTER_EN=1) (236)Figure I2C-57 Master Transmitter Stop Bit of IC_DATA_CMD Set/Tx FIFO Not Empty (IC_EMPTYFIFO_HOLD_MASTER_EN=1) (236)Figure I2C-58 Master Transmitter First Byte Loaded into Tx FIFO Allowed to Empty, Restart Bit Set (IC_EMPTYFIFO_HOLD_MASTER_EN=1) (237)Figure I2C-59 Master Receiver Stop Bit of IC_DATA_CMD Set/Tx FIFO Not Empty (IC_EMPTYFIFO_HOLD_MASTER_EN=1) (237)Figure I2C-60 Master Receiver First Command Loaded After Tx FIFO Allowed to Empty, Restart Bit Set (IC_EMPTYFIFO_HOLD_MASTER_EN=1) (237)Figure I2C-61 Multiple Master Arbitration (238)Figure I2C-62 Multi-Master Clock Synchronization (239)Figure I2C-63 Spike Suppression Example (242)Figure I2C-64 Impact of SCL Rise Time and Fall Time on Generated SCL (244)Figure I2C-65 IC_SDA_HOLD Register (247)Figure I2C-66 IC_SDA_RX_HOLD >= 3 (248)Figure I2C-67 IC_SDA_RX_HOLD = 2 (248)Figure I2C-68 DW_apb_i2c Master Implementing tHD; DAT with IC_SDA_HOLD = 3 (249)Figure DMAC-69 SDMAC Overview of Added Functions (280)Figure DMAC-70 SDMAC Clock and Reset System (282)Figure DMAC-71 HDMAC Overview of Added Functions (283)Figure DMAC-72 HDMAC Clock and Reset System (284)Figure DMAC-73 SYDMAC Clock and Reset System (285)Figure DMAC-74 SYSUBDMAC Clock and Reset System (287)Figure DMAC-75 ADMAC Clock and Reset System (288)Figure DMAC-76 IDMAC Function Block Diagram (289)Figure DMAC-77 IDMAC Clock and Reset System (300)Figure SCU (Sensor Control Unit)-78 Block Function Overview (303)Figure SCU (Sensor Control Unit)-79 Memory Mapping from the Upper CPUs; the CPU in the SYSIOP and the CPU in the GNSS; (hereinafter in the Chapter on SCU, referred as “upper CPUs”) (304)Figure SCU (Sensor Control Unit)-80 Memory Mapping within the SCU as seen from the Upper CPUs (305)Figure SCU (Sensor Control Unit)-81 Memory Mapping as seen from the Internal Sequencer (306)Figure SCU (Sensor Control Unit)-82 Memory Mapping as seen from the HOSTIFC (306)Figure SCU (Sensor Control Unit)-83 Clock System (309)Figure SCU (Sensor Control Unit)-84 Interrupt Connections (314)Figure SCU (Sensor Control Unit)-85 Decimation Partition Data Path (319)Figure SCU (Sensor Control Unit)-86 Normal Sensor Partition Data Path (319)Figure SCU (Sensor Control Unit)-87 Preprocessing Data Flow (320)Figure SCU (Sensor Control Unit)-88 Decimation Processing Data Flow (321)Figure SCU (Sensor Control Unit)-89 Data Flow within the Math Function (322)Figure SCU (Sensor Control Unit)-90 2 2nd Order IIR Filter Combinations (323)Figure SCU (Sensor Control Unit)-91 2nd Order IIR Filter Internal Data Flow (324)Figure SCU (Sensor Control Unit)-92 Normalization Processing Data Flow (324)Figure SCU (Sensor Control Unit)-93 Excess Detection Operation (by a Comparator and an Excess Detector) . 325 Figure SCU (Sensor Control Unit)-94 Excess Detection Operation (Two-step Cascade Connection) (326)Figure SCU (Sensor Control Unit)-95 FIFO Block Diagram (334)Figure SCU (Sensor Control Unit)-96 Sequencer Overall Image (336)Figure SCU (Sensor Control Unit)-97 Sequencer Process Flow (Example) (336)Figure SCU (Sensor Control Unit)-98 Overall Data Flow (excluding Data Duplication Function) (337)Figure SCU (Sensor Control Unit)-99 Startup Control (338)Figure SCU (Sensor Control Unit)-100 External Bus Transaction Generation (339)Figure SCU (Sensor Control Unit)-101 External Data Capture (340)Figure SCU (Sensor Control Unit)-102 Sensor Data Flow when Capturing External Data (341)Figure SCU (Sensor Control Unit)-103 Data Normalization (Example) (342)Figure SCU (Sensor Control Unit)-104 Data Stacked in the FIFO (Image) (343)Figure SCU (Sensor Control Unit)-105 Sequencer Data Flow (350)Figure SCU (Sensor Control Unit)-106 Sequencer Completed (352)Figure SCU (Sensor Control Unit)-107 Sequencer Suspended (352)Figure SCU (Sensor Control Unit)-108 MATH_PROC Parameter Change (Example) (353)Figure SCU (Sensor Control Unit)-109 Error Notification (Example) (355)Figure SCU (Sensor Control Unit)-110 DMA Handshake Signal Connections (357)Figure SCU (Sensor Control Unit)-111 PWM Output Mode using ADC Timing as a Reference (361)Figure SCU (Sensor Control Unit)-112 ADC Data Capture Mode using the PWM Output Timing as a Reference (364)Figure SCU (Sensor Control Unit)-113 Processing Block Overview (412)Figure SCU (Sensor Control Unit)-114 Filter Overview (414)Figure SCU (Sensor Control Unit)-115 Excess Detection Overview (450)Figure SCU (Sensor Control Unit)-116 I2C Master Control (Example) (918)Figure SCU (Sensor Control Unit)-117 Basic Startup Timing (919)Figure SCU (Sensor Control Unit)-118 Delay at Start (Example) (919)Figure SCU (Sensor Control Unit)-119 Time Stamp Fluctuation by the Presence/Absence of HPADC Execution (924)Figure SCU (Sensor Control Unit)-120 Counter Basic Operation (925)Figure SCU (Sensor Control Unit)-121 1 One-to-One Connection (Example) (926)Figure SCU (Sensor Control Unit)-122 One-to-N Connection (Example) (927)Figure SPI-123 SPI0 Clock and Reset System (933)Figure SPI-124 SPI3 Clock and Reset System (934)Figure SPI-125 SPI4 Clock and Reset System (935)Figure SPI-126 SPI5 Clock and Reset System (936)Figure SPI-127 Mode0, single transfer (939)Figure SPI-128 Mode0, continuous transfer (939)Figure SPI-129 Mode1, single and continuous transfers (940)Figure SPI-130 Mode2, single transfer (941)Figure SPI-131 Mode2, continuous transfer (941)Figure SPI-132 Mode3, single and continuous transfers (942)Figure UART-133 UART1 Clock and Reset System (951)Figure UART-134 UART2 Clock and Reset System (952)Figure APP-135 Application Domain Clock System (972)Figure APP-136 Application Domain Reset System (973)Figure APP-137 APP_DSP Block Diagram (983)Figure APP-138 WDTRES Connection (990)Figure APP-139 Address Map (994)Figure APP-140 Input-Output Addresses of Address Converter (995)Figure APP-141 Address Conversion Operation Scheme (996)Figure APP-142 Example of Address Conversion: Conversion of Bit Assignment for ADSP0 (999)Figure APP-143 Example of Address Conversion: Conversion Address Map for ADSP0 and ADSP1 (999)Figure APP-144 Success Case 1 of Exclusive Access (1001)Figure APP-145 Success Case 2 of Exclusive Access (1001)Figure APP-146 Failure Case 1 of Exclusive Access (1002)Figure APP-147 Failure Case 2 of Exclusive Access (1002)Figure APP-148 Failure Case 3 of Exclusive Access (1002)Figure SYSIOP Clock and Reset Control-149 SYSIOP Clock Configuration Diagram (1012)Figure SYSIOP Clock and Reset Control-150 SYSIOP Reset Configuration Diagram (1026)Figure 3.15-1 Audio Codec Block Diagram (1030)Figure 3.15-2 I2S Signal Path (1031)Figure 3.15-3 Mic Signal Path (1032)Figure 3.15-4 SP Signal Path (1034)Figure 3.15-5 Serializer Timing Chart (1035)Figure 3.15-6 I2S Format 24bit (1036)Figure 3.15-7 Left Justified 24bit (1037)Figure 3.15-8 CXD5247 Interface (SP) (MIC) (1037)Figure 3.15-9 DMIC Timing (1038)Figure 3.15-10 Internal Signal Selector Overview Diagram (1040)Figure 3.15-11 Characterstics of the Band Limiting Filter (HI_RES_MODE:1'b1, SRC{1,2}:2'b10) (1053)Figure 3.15-12 Characterstics of the Band Limiting Filter (HI_RES_MODE:1'b1, SRC{1,2}:2'b01) (1054)Figure 3.15-13 Volume Control Overview Diagram (1055)Figure 3.15-14 Example of ALC_TARGET Control (ALC_KNEE:7'h00) (1056)Figure 3.15-15 Example of ALC_KNEE Control (ALC_TARGET:6'h00) (1057)Figure 3.15-16 The HP Output Signal in Normal Mode (fs = 48 kHz) with ALC function OFF and Input Signal Level: -6 dB/-26 dB (1059)Figure 3.15-17 The HP Output Signal in Normal Mode (fs = 48 kHz) with ALC function ON, SPC_ALC_RELEASE = 0x000100, ALC_ALG = 1'b0, and Input Signal Level -6 dB/-26 dB (1059)Figure 3.15-18 The HP Output Signal in Normal Mode (fs = 48 kHz) with SPC function ON, SPC_ALC_ATTACK = 0x000100, and Input Signal Level -6 dB/-26 dB (1060)Figure 3.15-19 AWEIGHT Filter Characteristics (Hi-Res Mode) (1061)Figure 3.15-20 AWEIGHT Filter Chracteristics (Normal Mode) (1061)Figure 3.15-21 Order of Processing DEQ, ALC, and Clear Stereo (HI_RES_MODE:1'b1, ALC_REC:1'b0) (1062)Figure 3.15-22 Order of Processing DEQ, ALC, and Clear Stereo (HI_RES_MODE:1'b1, ALC_REC:1'b1) 1062Figure 3.15-23 Order of Processing DEQ, ALC, and Clear Stereo (HI_RES_MODE:1'b0, ALC_REC:1'b0) (1062)Figure 3.15-24 Order of Processing DEQ, ALC, and Clear Stereo (HI_RES_MODE:1'b0, ALC_REC:1'b1) (1063)Figure 3.15-25 Order of Processing DEQ, SPC, and Clear Stereo (1063)Figure 3.15-26 Decimation Filter Peripheral Overview (1064)Figure 3.15-27 Characteristics of 1/2-band Decimation Filter (1065)Figure 3.15-28 Characteristics of 1/4-band Decimation Filter (1066)Figure 3.15-29 Characteristics of 1/8-band Decimation Filter (1066)Figure 3.15-30 BUS MASTER(MIC) Block (1071)Figure 3.15-31 Bit Configuration by Transfer Mode (when writing to the SRAM) (1072)Figure 3.15-32 BUS MASTER (I2S0/I2S1) Block (1072)Figure 3.15-33 Bit Configuration by Transfer Mode (when writing to the SRAM) (1073)Figure 3.15-34 Bit Configuration by Transfer Mode (when reading from the SRAM) (1073)Figure 3.15-35 Mic Signal Upload Flow (Example) (1108)Figure 3.15-36 I2S0 Signal Upload Flow (Example) (1109)Figure USB-37 UDC-AHB Subsystem Architecture (1114)Figure USB-38 Clock Boundary (1117)Figure USB-39 IN Transaction Flow in DMA Mode (1125)Figure USB-40 OUT Transaction Flow in DMA Mode (Without Thresholding) (1127)Figure USB-41 IN Transaction Flow in Slave-Only Mode (1129)Figure USB-42 OUT Transaction Flow in Slave-Only Mode (1130)Figure USB-43 Memory Map (Processor Viewpoint) (1166)Figure USB-44 UDC-AHB Subsystem Architecture (1173)Figure USB-45 External RAM Write/Read Transfer (1177)Figure USB-46 FIFO Confirm Mechanism (1177)Figure USB-47 RxFIFO Implementation (1179)Figure USB-48 Descriptor Memory Structure (1182)Figure USB-49 SETUP Data Memory Structure (1183)Figure USB-50 OUT Data Memory Structure (1184)Figure USB-51 IN Data Memory Structure (1186)Figure USB-52 Control/Bulk-IN Transaction in Packet-Per-Buffer With Descriptor Update Mode (1192)Figure USB-53 Control/Bulk-IN Transaction in Packet-Per-Buffer Without Descriptor Update Mode (1193)Figure USB-54 OUT Transaction in Packet-Per-Buffer Mode With Descriptor Update (1194)Figure USB-55 OUT Transaction in Packet-Per-Buffer Mode Without Descriptor Update (1195)Figure USB-56 DMA Processing OUT Packets in Buffer Fill Mode (1196)Figure USB-57 DMA Processing OUT Packets in Packet-Per-Buffer With Descriptor Update Mode With Threshold Enabled (1198)Figure USB-58 Byte Ordering (Endianness) Conversion (1199)Figure USB-59 OUT Transaction Flow in DMA Mode Without Thresholding Enabled (1235)Figure USB-60 OUT Transaction Flow in DMA Mode With Thresholding Enabled (1236)Figure USB-61 OUT Transaction Flow in Slave-Only Mode (1237)Figure ADC-62 Block Diagram ADCIF module and around ADC macro circuits (1240)Figure ADC-63 Memory Map inside the ADCIF (1241)Figure ADC-64 Schematic Diagram of the Clock Control (1243)Figure ADC-65 Data Flow of the ADC (1245)Figure ADC-66 HPADC Gain Control Overview (1247)Table ContentsTable Notation-1 Notation of Numerical Value (40)Table Memory Mapping-2 Memory Mapping of the SYSIOP Block (SYS Window) (50)Table Memory Mapping-3 Memory Mapping of the APP Block (APP Window) (51)Table Power Management-4 Power Supply States (60)Table I/O Configuration-5 Function List (62)Table I/O Configuration-6 HOST I/F Decided in Accordance with Pin SYSTEM{0,1} (63)Table I/O Configuration-7 List of Registers for Controlling Pin Multiplexer (64)Table I/O Configuration-8 List of Registers for Controlling IOCELL (64)Table I/O Configuration-9 List of Registers for AUDIO and SDIO Control (67)Table I/O Configuration-10 Overview of Registers for Selecting a Role of the I/O Pins Belonging to SYS Group (68)Table I/O Configuration-11 Table of Role Selection for I/O Pins Belonging to SYS Group (69)Table I/O Configuration-12 Overview of Registers for Selecting a Role of the I/O Pins Belonging to APP Group (71)Table I/O Configuration-13 Table of Role Selection for the I/O Pins Belonging to APP Group (72)Table I/O Configuration-14 Overview of Registers to Select Function of IOCELL (74)Table I/O Configuration-15 Correspondence Table of IOCELL Control Registers and Controllable I/O Pins (76)Table I/O Configuration-16 Overview of Registers for Selecting Output Function of I2S (77)Table I/O Configuration-17 Overview of Register for Selecting PDM_CLK Output Function (77)Table I/O Configuration-18 Overview of Registers for Selecting Input Value to SDIO (78)Table General Purpose Input/Output (GPIO)-19 Function List (95)Table General Purpose Input/Output (GPIO)-20 GPIO Control Register (98)Table General Purpose Input/Output (GPIO)-21 Correspondence of GPIO Control Registers to I/O Pins (99)Table General Purpose Input/Output (GPIO)-22 IO Pin Selection (SYS Group) (103)Table General Purpose Input/Output (GPIO)-23 Correspondence of I/O Pins to Setting Values (SYS Group) (104)Table General Purpose Input/Output (GPIO)-24 I/O Pin Selection (APP Group) (104)Table General Purpose Input/Output (GPIO)-25 Correspondence of I/O Pins to Setting Values (APP Group) (105)Table General Purpose Input/Output (GPIO)-26 External Interrupt Selection (107)Table General Purpose Input/Output (GPIO)-27 I/O Pins That Can be Used for Event Detection (110)Table General Purpose Input/Output (GPIO)-28 Event Detection Setting for I/O Pins (112)Table General Purpose Input/Output (GPIO)-29 Status of Event Detection (115)Table General Purpose Input/Output (GPIO)-30 Registers to Clear the Status of the Event Detections (116)Table General Purpose Input/Output (GPIO)-31 Time Interval for a Signal to be Able to Detect an Event Again (1*) (119)Table Interrupt-32 List of Interrupt Registers of Application Processor (122)Table Interrupt-33 Interrupt Factor Registers of Application Processor (122)Table PMU (Power Management Unit)-34 Power Supply States (129)Table PMU (Power Management Unit)-35 The Setting of the Power Supply in “Reset” State and After Changing to “Normal” State (130)Table PMU (Power Management Unit)-36 PMU Register List (135)Table PMU (Power Management Unit)-37 Power Supply Control Settings (Power Domain) (137)Table PMU (Power Management Unit)-38 Power Supply Status (Power Domain) (138)Table PMU (Power Management Unit)-39 Power Supply Control Settings (SRAM) (139)Table PMU (Power Management Unit)-40 Power Supply Status (SRAM) (141)Table PMU (Power Management Unit)-41 Power Supply Control Settings (Analog Circuit) (143)Table PMU (Power Management Unit)-42 Power Supply Status (Analog Circuit) (144)Table PMU (Power Management Unit)-43 Power Supply Control Request (145)Table PMU (Power Management Unit)-44 Interrupt (145)Table PMU (Power Management Unit)-45 Power Supply Setting Check (146)Table PMU (Power Management Unit)-46 Power Supply Setting Check Items (147)Table PMU (Power Management Unit)-47 Power Supply Control Setting Values (149)Table PMU (Power Management Unit)-48 Parameter Setting for Each Mode (155)Table PMU (Power Management Unit)-49 Current Adjustment Setting (156)Table PMU (Power Management Unit)-50 SYSPLL Division Ratio Setting (158)Table Clock and Reset (Clock Reset Generator)-51 RCOSC Block Status Registers (169)Table Clock and Reset (Clock Reset Generator)-52 XOSC Block Status Register (170)Table Clock and Reset (Clock Reset Generator)-53 SYSPLL Frequency Confirmation (171)Table Clock and Reset (Clock Reset Generator)-54 SYSPLL Block Status Registers (171)Table Clock and Reset (Clock Reset Generator)-55 Clock Switching Status Registers (172)Table Clock and Reset (Clock Reset Generator)-56 Clock Enable Status Registers (174)Table Clock and Reset (Clock Reset Generator)-57 Power Domain and the Reset Control Registers (175)Table Clock and Reset (Clock Reset Generator)-58 Reset Registers of the Power Domain (176)Table Clock and Reset (Clock Reset Generator)-59 WDT Reset Control Registers (177)Table RTC-60Clock Resource of RTC (180)Table RTC-61 Clock Enable of RTC (180)Table RTC-62 Function List (181)Table RTC-63 Register List of Counter Value Write Control System (184)Table RTC-64 Register List of Time Counter Value Read Control System (184)Table RTC-65 Register List of Alarm Control System (185)Table RTC-66 Register List of Time Update Confirming System (186)Table RTC-67 List of External Alarm Output and Time Synchronization Register (186)Table RTC-68 Alarm Occurrence Condition (206)Table RTC-69 Examples of Setting Synchronizing Internal RTC with External RTC Synchronization Setting .. 218Table I2C-70 I2C List (222)Table I2C-71 XOSC (26 MHz), High Performance Mode (225)Table I2C-72 XOSC (26 MHz), Low Power Mode (225)Table I2C-73 IC_CON (252)Table I2C-74 IC_TAR (254)Table I2C-75 IC_SAR (254)Table I2C-76 IC_HS_MADDR (254)Table I2C-77 IC_DATA_CMD (255)Table I2C-78 IC_SS_SCL_HCNT (256)Table I2C-79 IC_SS_SCL_LCNT (256)Table I2C-80 IC_FS_SCL_HCNT (257)Table I2C-81 IC_FS_SCL_LCNT (257)Table I2C-82 IC_HS_SCL_HCNT (258)Table I2C-83 IC_HS_SCL_LCNT (258)Table I2C-84 IC_INTR_STAT (259)Table I2C-85 IC_INTR_MASK (259)Table I2C-86 IC_RAW_INTR_STAT (260)Table I2C-87 IC_RX_TL (262)Table I2C-88 IC_TX_TL (262)Table I2C-89 IC_CLR_INTR (263)Table I2C-90 IC_CLR_RX_UNDER (263)Table I2C-91 IC_CLR_RX_OVER (263)Table I2C-92 IC_CLR_TX_OVER (263)Table I2C-93 IC_CLR_RD_REQ (264)Table I2C-94 IC_CLR_TX_ABRT (264)Table I2C-95 IC_CLR_RX_DONE (264)Table I2C-96 IC_CLR_ACTIVITY (264)Table I2C-97 IC_CLR_STOP_DET (265)Table I2C-98 IC_CLR_START_DET (265)Table I2C-99 IC_CLR_GEN_CALL (265)Table I2C-100 IC_ENABLE (265)Table I2C-101 IC_STATUS (267)Table I2C-102 IC_TXFLR (268)Table I2C-103 IC_RXFLR (268)Table I2C-104 IC_SDA_HOLD (269)Table I2C-105 IC_TX_ABRT_SOURCE (269)Table I2C-106 IC_SLV_DATA_NACK_ONLY (271)Table I2C-107 IC_DMA_CR (271)Table I2C-108 IC_DMA_TDLR (271)。

5/17/11關於這本使用手冊當閱讀操作說明時，請遵守這些指導方針：w c Q R&警告：請務必小心遵守，以免身體受傷。

注意：請務必遵守，以免損害設備。

請務必遵守這個禁止符號的指示，以免造成身體受傷，或是設備損壞。

附註：包含有關使用本產品的重要資訊和提示。

指示可以找到詳細說明的頁數。

3版權注意事項No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without the prior written permission of Seiko Epson Corporation. The information contained herein is designed only for use with this product. Epson is not responsible for any use of this information as applied to other printers.Neither Seiko Epson Corporation nor its affiliates shall be liable to the purchaser of this product or third parties for damages, losses, costs, or expenses incurred by the purchaser or third parties as a result of accident, misuse, or abuse of this product or unauthorized modifications, repairs, or alterations to this product, or (excluding the U.S.) failure to strictly comply with Seiko Epson Corporation掇 operating and maintenance instructions.Seiko Epson Corporation shall not be liable for any damages or problems arising from the use of any options or any consumable products other than those designated as Original Epson Products or Epson Approved Products by Seiko Epson Corporation.Seiko Epson Corporation shall not be held liable for any damage resulting from electromagnetic interference that occurs from the use of any interface cables other than those designated as Epson Approved Products by Seiko Epson Corporation.EPSON® is a registered trademark, and Exceed Your Vision and EPSON ME are trademarks of Seiko Epson Corporation.PRINT Image Matching™ and the PRINT Image Matching logo are trademarks of Seiko Epson Corporation. Copyright © 2001 Seiko Epson Corporation. All rights reserved. SDHC™ is a trademark.Memory Stick, Memory Stick Duo, Memory Stick PRO, Memory Stick PRO Duo, Memory Stick PRO-HG Duo, Memory Stick Micro, MagicGate Memory Stick, and MagicGate Memory Stick Duo are trademarks of Sony Corporation.xD-Picture Card™ is a trademark of Fuji Photo Film Co., Ltd.General Notice: Other product names used herein are for identification purposes only and may be trademarks of their respective owners. Epson disclaims any and all rights in those marks.45/17/11重要的安全說明565/17/11保護您的個人資料本產品可讓您將名字和電話號碼儲存在產品的記憶體中，即使關閉若您要將本產品轉送他人或是丟棄，請使用下列選單，清除記憶體中的資料。

RL78族集成开发环境从CA78K0R转至CCRL的使用指南（编码篇）瑞萨电子（中国）有限公司2016/3/1 Rev.1.00前言▪本篇资料中，记述了使用C编译器CA78K0R创建的RL78族MCU的工程或者源码转至使用C编译器CC-RL的源码的差异。

▪本篇资料以用于RL78族的C编译器CA78K0R和CC-RL作为对象进行说明。

对象版本如下：▪CA78K0R V1.20或更高▪CC-RL V1.01.00目录▪编译器语言第04页▪汇编语言第20页▪函数调用接口第24页▪过渡支援功能第26页▪FAQ 第47页编译器语言编译器语言语言规格上的差异具体请参照编译器用户手册进行修改。

编译器语言语言规格上的差异具体请参照编译器用户手册进行修改。

编译器语言编译器语言▪枚举型说明符的差异内部表现形式因枚举范围的不同而变化。

▪CA78K0R的场合（优先顺序）范围：-128 ~ 127 → signed char范围： 0 ~ 255 → unsigned char范围： -32768 ~ 32767 → signed int▪CC-RL的场合（优先顺序）•指定-signed_char •不指定-signed_char范围： -128 ~ 127（包括0 ~ 127）→char 范围： -128 ~ 127 → signed char范围： 0 ~ 255 → unsigned char 范围： 0 ~ 255（包括0 ~ 127）→char范围：上述以外→ signed short 范围：上述以外→ signed short具体请参照编译器用户手册进行修改。

编译器语言包含头文件的差异具体请参照编译器用户手册进行修改。

编译器语言翻译限制的差异※ CA78K0R列，适用于V1.50及更新的版本。

具体请参照编译器用户手册进行修改。

编译器语言翻译限制的差异※ CA78K0R列，适用于V1.50及更新的版本。

具体请参照编译器用户手册进行修改。

REXA电动执行机构XPAC安装与操作手册安全注意事项电击危险：执行机构的工作电压为危险电压等级。

设备的安装与调试只能由具有资质的安装和维护人员来完成。

对位：应确保执行机构驱动轴与阀杆的轴心重合，轴心线不重合将会对执行机构和驱动设备造成损害，还有可能对安装人员造成伤害。

避免突然启动：在安装执行机构时，应切断执行机构的电源。

当供电情况下，执行机构可能会对控制信号立刻做出反应。

不经意的操作可能会对执行机构和驱动装置造成损害，或者对安装人员造成伤害。

特别提示：控制盒在加工过程种可能留有残屑，上电之前应彻底的清洁控制盒中的金属屑。

液压油：REXA执行机构或驱动器的标准用油为Castrol Syntec SAE 5W-50机油。

特殊用油将会标注在标牌上。

采用其它液体可能会引起设备的损坏。

绷紧状态下的弹簧：E、R或U 型的REXA执行机构中有一个绷紧的弹簧。

在拆卸之前，如果没有消除弹簧弹力，可能会对维护人员造成严重的伤害。

请与REXA厂家联系以便获得执行机构的装卸操作说明书。

释放内部压力：在断电（装置故障）或者电机停转的情况下，液压缸内仍然封存液压。

在断开任何液压管路连接器之前，必须释放掉内部液压。

打开出现故障的动力模块上的液压缸旁通阀（3/”六角型的），或关掉出现故障部件弹簧上的电磁阀的电源。

16参见故障排除与维修手册的3.M2部分。

蓄能器故障选项：A1、A2、A3或A4型REXA执行机构中有一个可冲放的高压氮储能器。

这类执行机构能自动地为蓄能器冲氮。

不按照安装操作说明进行正确安装可能会对维护人员造成严重的伤害或者会损害设备。

NPT插塞及管线的连接：装配时，所有NPT插塞及管线连接螺纹上必须采用Loctite767密封胶或等效密封胶以保证其水密性。

引言：REXA Xpac的执行机构和驱动器为电液压驱动设备。

这类设备由一个位于控制盒内的设定好的微处理器来控制并由动力模块中的液动系统来操作；其适用于100%占空比工作，Xpac适用于各种自动控制应用。

ARM® ARM926EL-S Based32-bit MicroprocessorRDK-N9H20Demo Board User ManualThe information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based system design. Nuvoton assumes no responsibility for errors or omissions.All data and specifications are subject to change without notice.For additional information or questions, please contact: Nuvoton Technology Corporation.Table of Contents1OVERVIEW (3)1.1Brief Introduction to RDK-N9H20 Demo Board (4)1.2PCB key parts description (4)1.3System Circuitry design notes (6)1.3.1Main Clock (6)1.3.2RTC Clock (6)1.3.3RESET (7)1.3.4Power-on Setting (7)1.3.5Power Desing Notes (8)2PCB Layout Design Note (10)2.1USB (10)2.2Signal integrity, SI (11)2.3Power supply and power filter design consideration (12)2.3.1DDR MVDD & Core Power 1.8V Design (12)2.3.2I/O 3.3V Power Design (13)2.4Main Clock 12MHz Design Suggestion (14)2.5RESET Layout Suggestion (15)3RDK-N9H20 demo board use description (16)3.1System start up (16)3.2USB Port (18)3.3Communication Interface (UART0) uses (18)3.4LCD Interface (18)4Test Report (19)Power consumption (19)4.14.2ESD Test Report (19)EFT Test Result (19)4.34.4EMI Test Result (20)5RDK-N9H20 demo board SCHEMATIC (22)5.1N9H20 Schematic (22)LCD Schematic (23)5.25.3Power Schematic (24)6REVISION HISTORY (25)1 OVERVIEWThe RDK-N9H20 is a general demo board installed the N9H20K51N chip which integrated 32MBDDR2 memory, users can verify emWin GUI application program easily.The demo board includes one Micro USB connector for USB 2.0 high speed device controller forcommunication with PC, and the board also has a debugging UART port for system programmingor debugging.About display, the RDK-N9H20 demo board included one 4.3”LCD which the resolution is480x272 with RGB-24bits and embedded the 4-wires resistive type touch panel.For system booting, the RDK-N9H20 demo board supports one SPI-NOR Flash or one NANDFlash for selection depended on user demand.NUTINY-SDK-NUC505 USER MANUALFigure 1-1 RDK-N9H20 demo boardBrief Introduction to RDK-N9H20 Demo Board1.1RDK-N9H20 demo board applied to HMI application, the purpose is for user have a reference design with emWin GUI accelerator platform. Thus that customers do not have to modify or only make simple changes could get a completed HMI hardware product quicklyThe following figures show the RDK-N9H20 demo board, in which the PCB integrated Nuvoton N9H20K51N 32-bit microcontroller with CPU core ARM926EJ-S, speed runs up at 192MHz, with 16KB I-cache, 16 KB D-cache and MMU, 8KB SRAM and 12KB IBR(Internal Boot ROM) for booting sources from USB ,SPI-NOR Flash or NAND Flash selectable.1.2PCB key parts descriptionThe PCB key parts are shown as the figureFigure 1-2 RDK-N9H20 PCB components sideNUTINY-SDK-NUC505 USER MANUALSystem Circuitry design notes1.31.3.1 Main ClockThe system clock circuit is formed by the feedback circuit inside the chip and the external 12MHzcrystal oscillation circuit. Recommended crystal connection mode and device parameters as shown in the figure below.Note: The chosen capacitance needs to match the load capacitance of the crystal oscillator1.3.2RTC ClockN9H20K51N integrates the RTC function, the board needs to provide the RTC with the clock circuit, the recommended Crystal connection mode and the device parameters as shown in the figure below.NUTINY-SDK-NUC505 USER MANUAL1.3.3 RESETThe nRST signal of the N9H20K51N is the reset signal input pin, and the required reset effective signal is a low-level pulse.In order to stabilize the system robustness, it is recommended to use the following circuitry to implement reset signal. The RDK-N9H20 demo board reset circuity and related passive device parameters as shown in the following figure.1.3.4 Power-on SettingThe power-on setting value is used to configure the chip to enter a specific state after power-up or reset. The power-on setting value will be kept in power-on setting control register for reference. The following is the RDK-N9H20 demo board power-on setting circuitry and functions description.1.3.4.1RDK-N9H20 demo board power-on setting description1.3.5 Power Desing NotesRDK-N9H20 demo board power supply design have the below considerations●For system core power (1.8V) design, it is recommended to select DC-DC part and the outputcapacity have 1A or above is better.●For IO power (3.3V), in RDK-N9H20 demo board also uses DC-DC part, the concern is for LCDpowered●Power up sequence, the I/O (3.3V) power should be equal or fast than the core (1.8V) powerand time gap between should control under within 500uS as the figure shown.●Power-down sequence, the Core (2.8V) power should be equal or fast than the I/O (3.3V) power.NUTINY-SDK-NUC505 USER MANUALNote. ● Yellow line is I/O (3.3V) ● Blue line is core (1.8V) ● Purple line is nRST signal2 PCB LAYOUT DESIGN NOTE.RDK-N9H20 demo board is a 2-layers PCB and single component side design, for getting good performance and system quality have some suggestions as the below please follow.USB2.1USB differential Line have 3 conditions as far as possible: 1, equal length; 2, equal width and 3, EquidistantTo do 90ohm ±10% impedance control. The double-layer plate can be controlled by the way of the impedance, that is, the differential line to do the GND shielding processing.The RDK-N9H20 demo board USB eys diagram result as the below fugureSignal integrity, SI2.2Due to 2- layers PCB does not have a separate GND plane, and to ensure the connectivity and integrity of the GND plane, the following requirements must be observed: ●The Bottom layer as far as possible or less device, to ensure the bottom surface of the GND integrity. Especially at the bottom of the main chip.,the RDK-N9H20 demo board that GND process at the bottom of main chip is shown in the following figure.● If that is possible please place more via holes to GND to ensure that the top surface and the bottom surface of the GND copper skin connectivity.● Ensure that there is no island of GND copper skin, as far as possible to ensure that as much as possible to connect the copper, so that the signal return path as short as possible.● High-speed signal line under the bottom surface, as far as possible to ensure the complete GND plane, do not have to walk through the line.●For critical signals, such as crystal oscillator, System Reset, I²C, USB, etc., need to be processed with shield GND all the way. The good shield GND process can guarantee the continuity of the impedance, anti-interference, and prevent EMI radiation.The following fugure is the LCD_CLK signle connectivity with shield GND processPower supply and power filter design consideration2.32.3.1 DDR MVDD & Core Power 1.8V DesignAbout filter capacitance material and placement quantityCapacity material recommended to use X7R material, placing quantity suggest that the corresponding chip should have at least one 104pF capacitors at the each supply pin, and some special entrances suggest placing the 104 pF+10 uF combination.Detail please refer to RDK-N9H20 schematic diagram for details.The layout pattern and the filter capacitance placement are shown in the image below.NUTINY-SDK-NUC505 USER MANUAL2.3.2 I/O 3.3V Power DesignAbout filter capacitance material and placement quantityCapacity material recommended to use X7R material, placing quantity suggest that the corresponding chip should have at least one 104pF capacitors at the each supply pin, and some special entrances suggest placing the 104 pF+10 uF combination.Detail please refer to RDK-N9H20 schematic diagram for details.The layout pattern and the filter capacitance placement are shown in the image below.2.4Main Clock 12MHz Design SuggestionThe 12MHz oscillator is the heart of the N9H20 chip and should be preferred in layout. Layout Basic principles: As close as possible to the chip pin, trace lines shoud be straight doesn’t be bent, and important thing is that XTAL part at the bottom has a complete GND plane.PCB layout skill was shown as below figure.NUTINY-SDK-NUC505 USER MANUALRESET Layout Suggestion2.5For system ESD capability and stability, the RESET signal design and layout traces routing are worth a comprehensive consideration to do that best protection.Schematic details please refer to the schematic diagram of the RDK-N9H20, about the PCB layout was shown as below figure.3 RDK-N9H20 DEMO BOARD USE DESCRIPTIONThe RDK-N9H20 demo board is powered by DC +5V and is accessed by the CON3 pin-1 (+5V) and the pin-4 (GND).The demo board system block as the figure.3.1System start upMode switching by Normal/USB recovery mode jumper (i.e. R64 install or not) as the be low figure ●R64 pin un-install: Normal operation for NAND or SPI FLASH booting●R64 pin installation: USB booting for code programming through writer tool of PC utility.NUTINY-SDK-NUC505 USER MANUAL3.2USB PortThe USB interface on the board is mainly used for burning the update program, this interface does not have the power supply capability. When using, please choose to connect with this interface USB extension cable connected with the PC and then power supply through the system supply port.CON33.3Communication Interface (UART0) usesCON3 interface is combined with UART0 serial port and +5V power supply, serial port level is standard TTL, communication baud rate is 115200bps.The development period can be used for debug, which can be used for data interaction after the product.3.4LCD InterfaceHMI-H9H20 demo board supports LCD interface with a 40-pin FPC connector, it is apply to 4.3” LCD resolution 480x272 RGB 24-bits and embedded 4-wires resistive type touch panel, the touch panel is connectivity with N9H20 ADC directly.4 TEST REPORT4.1Power consumptionCondition : CPU@192MHz , emWin demo code is running●Non-OS+emWin + 4.3 LCD：5V@335mA●Non-OS+emWin without LCD: 5V@98mA4.2ESD Test Report●Contact (PCB GND & LCD metal ）：+/- 4KV pass●Air (LCD touch panel）：+/- 8KV pass●Coupling (Horizontal & Vertical) ：+/- 4KV passNUTINY-SDK-NUC505 USER MANUAL 4.3EFT Test Result●EFT±4000V 5.0KHz passEMI Test Result4.4EN55032 Test Result : PassNUTINY-SDK-NUC505 USER MANUALNUTINY-SDK-NUC505 USER MANUAL5 RDK-N9H20 DEMO BOARD SCHEMATIC 5.1N9H20 SchematicNUTINY-SDK-NUC505 USER MANUALLCD Schematic5.2Power Schematic 5.36 REVISION HISTORY2018.09.25 1.00 Initially issued.Important NoticeNuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, “Insecure Usage”.Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life.All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claims to Nuvoton as a result of customer’s Insecure Us age, customer shall indemnify the damages and liabilities thus incurred by Nuvoton.。

2010.09瑞萨电子M C U 型号速查手册QzROM 低功耗720、740工具R8C族及工具M16C R32C M16C族工具SuperH族及工具安全MCU 芯片封装说明78K V85078K、V850工具QzROM 13720族、740族开发工具介绍4低功耗6R8C族及其开发工具介绍23M16C族29M16C族R32C34M16C族开发工具介绍36SuperH RISC engine族及其开发工具介绍45安全MCU 78芯片封装说明5078K 65V8507578K、V850微控制器开发工具介绍瑞萨电子MCU 型号速查手册QzROM1QzROM 低功耗720、740工具78K、V850工具R8C族及工具SuperH族及工具M16C族工具安全MCU 78K V850芯片封装说明M16C R32C2QzROMM16C R32CM16C族工具安全MCU78K V850芯片封装说明720、740工具78K、V850工具QzROM低功耗R8C族及工具SuperH族及工具3720族、740族开发工具QzROM 低功耗720、740工具78K、V850工具R8C族及工具SuperH族及工具M16C族工具安全MCU 78K V850芯片封装说明M16C R32CM16C R32CM16C族工具安全MCU78K V850芯片封装说明720、740工具78K、V850工具QzROM低功耗R8C族及工具SuperH族及工具5低功耗QzROM 低功耗720、740工具78K、V850工具R8C族及工具SuperH族及工具M16C族工具安全MCU 78K V850芯片封装说明M16C R32C6R8C族1x系列R 5F 21254S D X X X S P U 010*********瑞萨新MCU代码器件区分ex)F:闪存瑞萨R8C族代码瑞萨R8C群代码ex)R8C/1B, R8C/25存储器变化(仅R8C系列)0:2KB 1:4KB 2:8KB 3:12KB 4:16KB5:24KB 6:32KB 7:48KB 8:64KBA:96KB C:128KB(-):标准版本S :低电压版本A :R8C/3x的新增功能代码2ex) J -40~85℃ 汽车K -40~125℃ 汽车D -40~85℃ 工业N或无标记 -20~85℃ 消费类电子ROM型号(仅用于出厂编程的MCU)FP:LQFP, SP:LSSOP, NP:QFNFA:LQFP, DD:SDIP, LG:FLGAU0:无铅产品，盘装或管装出货W4:无铅产品，卷带出货无标记:含铅产品，盘装或管装出货T4:含铅产品，卷带出货ES:工程样品12345678910R8C族MCU命名规则QzROM 低功耗720、740工具78K、V850工具R8C族及工具SuperH族及工具M16C族工具安全MCU 78K V850芯片封装说明M16C R32C7R8C族1x系列QzROM 低功耗720、740工具78K、V850工具R8C族及工具SuperH族及工具M16C族工具安全MCU 78K V850芯片封装说明M16C R32C8R8C族1x系列注：① R8C/1x芯片的ROM类型均为Flash。

To our customers,Old Company Name in Catalogs and Other DocumentsOn April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding.Renesas Electronics website: April 1st, 2010Renesas Electronics CorporationIssued by: Renesas Electronics Corporation ()Send any inquiries to /inquiry.Notice1. All information included in this document is current as of the date this document is issued. Such information, however, issubject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rightsof third parties by or arising from the use of Renesas Electronics products or technical information described in this document.No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others.3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation ofsemiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information.5. When exporting the products or technology described in this document, you should comply with the applicable export controllaws and regulations and follow the procedures required by such laws and regulations. You should not use RenesasElectronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.6. 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The quality grade of each Renesas Electronics product is “Standard” unless otherwiseexpressly specified in a Renesas Electronics data sheets or data books, etc.“Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots.“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically designed for life support.“Specific”: Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcareintervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.8. 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Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of RenesasElectronics.12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in thisdocument or Renesas Electronics products, or if you have any other inquiries.(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.用户须知U19582CA1V0IF00 (1/28)2007-5-11Yoshinari Ando，统括经理开发工具解决方案部通用MCU系统事业部MCU营业本部NEC Electronics Corporation78K0 系列集成调试器ID78K0-QB V3.00操作注意事项使用产品前请先阅读本文档。

SMH-50/50/50-150-XL 硬体操作说明书匯出日期：2023-10-19修改日期：2021-04-19•••••••••••••••••••••••目录序言适用机型硬体规格说明外观介绍外形尺寸驱动器规格搬运与安装搬运安装环境条件与注意事项配线与信号周边装置接线图驱动器的连接器与端子说明各式配线图串列向量配线图新代编码器外接类比温感配线图多台四合一串联说明回生电阻选用简易回生电阻选择详细回生电阻选择KTY84温感器与过温度保护功能安装驱动器参数设定版本号编修日期编修内容作者审查核准V1.22022-6-30修正为SMD-34B-50150-xx 硬体操作说明书带电池盒乃维V1.12020-7-23刪去電容吸收能量Ec黃揚程V1.02018/10/04新增SMD-34B-50150-xx 硬体操作说明书杨娟HomePageSYNTEC伺服操作说明书文件资讯文件履历文件资讯文件履历1 序言感谢您长期对本公司产品的使用与支持。

本公司伺服团队不断致力於各项产品的研发，期许本公司产品与服务能给使用者带来最大的效益。

新代高性能驱动器系列产品为本公司最新推出之伺服驱动器，本产品使用高品质之元件与材料，并经过严格测试，采用精密向量控制，具有高精确度、高稳定性、高效率之特性。

本使用说明内容包括驱动器的硬体规格、安装、配线与讯号，能提供给使用者最正确的指引与操作，为充分发挥产品应有的优异性能与维护人员及设备的安全，在使用前请详细阅读本使用手册，并且妥善保存，以备日後调校与保养时使用，若有任何疑虑，请与本公司联络，本公司专业人员将竭诚为您服务。

2 适用机型本操作手册适用於新代 3KWX3+18.5KW四合一驱动器3 硬体规格3.1 说明每部驱动器在出厂前均经过详细品管检查与防撞包装处理，请使用者收到产品後应先检查外观有无撞击损伤，并将外盒与产品上之序号做比对是否一致，若有不符，请第一时间与本公司联络。

型号说明3.2 外观介绍SMH-50/50/50-150-XL驱动器功能模块说明A外供电源输入接点连接380V~440V三相交流电(RST) B马达驱动电源输出接点连接马达侧提供马达电源(UVW)由右至左分别为第一至第四轴C煞车电阻接点煞车电阻接点(P-B)D MIII串行通讯接孔连接上位控制器(MIII讯号)连接串行驱动器 (MIII讯号) E Mini USB接孔连接个人计算机调机使用F I/O讯号端口外接电池端口连接I/O设备(急停、警示灯…等)连接绝对型编码器供电电池G STO讯号端口STO接口，2组安全输入，1组安全功能回授H编码器回授接孔由上至下分别为第一至第四埠。

maxon motor ag Brünigstrasse 220 P.O.Box 263 CH-6072 Sachseln （瑞士） 电话：+41 41 666 15 00 传真：+41 41 666 16 50 出版日期 2018年11月ESCON 伺服控制器使用说明书maxon motor control ESCON 50/5伺服控制器订货号 409510使用说明书文件编号: rel8440maxon motor control A-2文件编号:rel8440ESCON 伺服控制器出版日期:2018年11月ESCON 50/5使用说明书© 2018 maxon motor. 如有修改恕不另行通知。

1概述31.1本手册的介绍 . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.2设备介绍 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.3安全规程 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52技术规格72.1技术数据 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.2标准 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103设置113.1适用的一般规定 . . . . . . . . . . . . . . . . . . . . . . . . . . 113.2电源的设计 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123.3连接 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.4电位器 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263.5状态显示 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274接线294.1有刷直流电机 . . . . . . . . . . . . . . . . . . . . . . . . . . . 304.2无刷电子换向电机 . . . . . . . . . . . . . . . . . . . . . . . . . 335备件35目录请首先认真阅读下文！本说明供合格的专业技术人员阅读参考。

]LE910Cx/ME910C1/ML865C1/NE910C1A-GPS Application Note80529NT11738A Rev. 2 – 2019-11-221 7SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICENOTICEWhile reasonable efforts have been made to assure the accuracy of this document, Telit assumes no liability resulting from any inaccuracies or omissions in this document, or from use of the information obtained herein. The information in this document has been carefully checked and is believed to be reliable. However, no responsibility is assumed for inaccuracies or omissions. Telit reserves the right to make changes to any products described herein and reserves the right to revise this document and to make changes from time to time in content hereof with no obligation to notify any person of revisions or changes. Telit does not assume any liability arising out of the application or use of any product, software, or circuit described herein; neither does it convey license under its patent rights or the rights of others.It is possible that this publication may contain references to, or information about Telit products (machines and programs), programming, or services that are not announced in your country. Such references or information must not be construed to mean that Telit intends to announce such Telit products, programming, or services in your country. COPYRIGHTSThis instruction manual and the Telit products described in this instruction manual may be, include or describe copyrighted Telit material, such as computer programs stored in semiconductor memories or other media. Laws in the Italy and other countries preserve for Telit and its licensors certain exclusive rights for copyrighted material, including the exclusive right to copy, reproduce in any form, distribute and make derivative works of the copyrighted material. Accordingly, any copyrighted material of Telit and its licensors contained herein or in the Telit products described in this instruction manual may not be copied, reproduced, distributed, merged or modified in any manner without the express written permission of Telit. Furthermore, the purchase of Telit products shall not be deemed to grant either directly or by implication, estoppel, or otherwise, any license under the copyrights, patents or patent applications of Telit, as arises by operation of law in the sale of a product.COMPUTER SOFTWARE COPYRIGHTSThe Telit and 3rd Party supplied Software (SW) products described in this instruction manual may include copyrighted Telit and other 3rd Party supplied computer programs stored in semiconductor memories or other media. Laws in the Italy and other countries preserve for Telit and other 3rd Party supplied SW certain exclusive rights for copyrighted computer programs, including the exclusive right to copy or reproduce in any form the copyrighted computer program. Accordingly, any copyrighted Telit or other 3rd Party supplied SW computer programs contained in the Telit products described in this instruction manual may not be copied (reverse engineered) or reproduced in any manner without the express written permission of Telit or the 3rd Party SW supplier. Furthermore, the purchase of Telit products shall not be deemed to grant either directly or by implication, estoppel, or otherwise, any license under the copyrights, patents or patent applications of Telit or other 3rd Party supplied SW, except for the normal non-exclusive, royalty free license to use that arises by operation of law in the sale of a product.USAGE AND DISCLOSURE RESTRICTIONSI. License AgreementsThe software described in this document is the property of Telit and its licensors. It is furnished by express license agreement only and may be used only in accordance with the terms of such an agreement.II. Copyrighted MaterialsSoftware and documentation are copyrighted materials. Making unauthorized copies is prohibited by law. No part of the software or documentation may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language or computer language, in any form or by any means, without prior written permission of Telit III. High Risk MaterialsComponents, units, or third-party products used in the product described herein are NOT fault-tolerant and are NOT designed, manufactured, or intended for use as on-line control equipment in the following hazardous environments requiring fail-safe controls: the operation of Nuclear Facilities, Aircraft Navigation or Aircraft Communication Systems, Air Traffic Control, Life Support, or Weapons Systems (High Risk Activities"). Telit and its supplier(s) specifically disclaim any expressed or implied warranty of fitness for such High Risk Activities.IV. TrademarksTELIT and the Stylized T Logo are registered in Trademark Office. All other product or service names are the property of their respective owners.V. Third Party RightsThe software may include Third Party Right software. In this case you agree to comply with all terms and conditions imposed on you in respect of such separate software. In addition to Third Party Terms, the disclaimer of warranty and limitation of liability provisions in this License shall apply to the Third Party Right software.TELIT HEREBY DISCLAIMS ANY AND ALL WARRANTIES EXPRESS OR IMPLIED FROM ANY THIRD PARTIES REGARDING ANY SEPARATE FILES, ANY THIRD PARTY MATERIALS INCLUDED IN THE SOFTWARE, ANY THIRD PARTY MATERIALS FROM WHICH THE SOFTWARE IS DERIVED (COLLECTIVELY “OTHER CODE”), AND THE USE OF ANY OR ALL THE OTHER CODE IN CONNECTION WITH THE SOFTWARE, INCLUDING (WITHOUT LIMITATION) ANY WARRANTIES OF SATISFACTORY QUALITY OR FITNESS FOR A PARTICULAR PURPOSE.NO THIRD PARTY LICENSORS OF OTHER CODE SHALL HAVE ANY LIABILITY FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND WHETHER MADE UNDER CONTRACT, TORT OR OTHER LEGAL THEORY, ARISING IN ANY WAY OUT OF THE USE OR DISTRIBUTION OF THE OTHER CODE OR THE EXERCISE OF ANY RIGHTS GRANTED UNDER EITHER OR BOTH THIS LICENSE AND THE LEGAL TERMS APPLICABLE TO ANY SEPARATE FILES, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.APPLICABILITY TABLE PRODUCTSME910C1 SERIESNE910C1 SERIESML865C1 SERIESLE910C1/C4 SERIESCONTENTSNOTICE 2COPYRIGHTS (2)COMPUTER SOFTWARE COPYRIGHTS (2)USAGE AND DISCLOSURE RESTRICTIONS (3)I.License Agreements (3)II.Copyrighted Materials (3)III.High Risk Materials (3)IV.Trademarks (3)V.Third Party Rights (3)APPLICABILITY TABLE (4)CONTENTS (5)1.INTRODUCTION (6)2.BACKGROUND INFORMATION (9)A Brief GPS Introduction (9)GNSS – Global Navigation Satellite System (10)Time to First Fix (TTFF) (10)3.GNSS SOLUTION (11)Standalone GNSS (11)A-GPS – Secure User Plane Location (SUPL) – Ms-Based (12)4.GLOSSARY AND ACRONYMS (17)5.DOCUMENT HISTORY (18)1. INTRODUCTIONThe present document provides the reader with a guideline concerning the use of the Assisted GPS (A-GPS) provided by the Telit’s Modules of the ME910 family.1.1. ScopeThe Application Note covers the Secure User Plane Location (SUPL) standard created by the OMA standardization body.1.2. AudienceThis document is intended for those users that need to develop applications dealing with LoCation Service (LCS).1.3. Contact Information, SupportFor general contact, technical support services, technical questions and report documentation errors contact Telit Technical Support at:•*****************•*********************•*****************Alternatively, use:/supportFor detailed information about where you can buy the Telit modules or for recommendations on accessories and components visit:Our aim is to make this guide as helpful as possible. Keep us informed of your comments and suggestions for improvements.Telit appreciates feedback from the users of our information.1.4. Text ConventionsDanger –This information MUST be followed or catastrophic equipmentfailure or bodily injury may occur.Caution or Warning – Alerts the user to important points about integrating themodule, if these points are not followed, the module and end user equipmentmay fail or malfunction.Tip or Information –Provides advice and suggestions that may be usefulwhen integrating the module.All dates are in ISO 8601 format, i.e. YYYY-MM-DD.1.5. Related Documents•[1] ME910C1 Quick Start Guide, 80529NT11661A•[2] ME910C1/NE910C1/ML865C1 AT Commands Reference Guide, 80529ST10815A•[3] LE910Cx AT Command Reference Guide 80502ST10950A2. BACKGROUND INFORMATIONA Brief GPS IntroductionThe detailed description of the GPS system is beyond the scope of this document.The reader that is interested in deepening this topic should refer to the dedicated literature; hereafter only the basic concepts are mentioned. GPS system is based on a constellation of 24 satellites distributed equally among six circular orbital planes; the height of the orbits is about 20200 km. Orbits in this height are referred to as medium earth orbit (MEO).Each satellite moves along a known orbit and is equipped with an atomic clock: GPS receivers use the time information regularly transmitted by the satellites and the time elapsed for receiving this signal from each satellite to calculate their positional information.Figure 2-1 ECEF coordinate system [source: https://]Telit GPS receivers use as default the geodetic reference (datum) WGS-84, an ECEF (Earth Centered, Earth Fixed) coordinate system that consists in an ellipsoid approximating the total mass of the Earth, as shown in Fig. 2-1.WGS-84 provides a worldwide common grid system that may be translated into local coordinate systems or map datums. Many reference ellipsoids are used throughout the world: a specific reference is chosen to minimize the local differences between the geoidand the ellipsoid separation or other mapping distortions. Local map datums are a best fit to the local shape of the earth and are not valid worldwide.GNSS – Global Navigation Satellite SystemIn addition to the GPS constellation, other satellite navigation systems are currently in operation or under development. The working principles of these systems are analogous to the GPS’ ones presented in the previous section.When the system has global coverage, it may be termed Global Navigation Satellite System (GNSS).Galileo (European Union), BeiDou (China), GPS (USA), GLONASS (Russia) are the GNSSs currently in operation, although Galileo and Beidou are not yet fully operational. Furthermore, additional regional navigation and augmentation systems are under development (QZSS, NAVIC, etc.).Time to First Fix (TTFF)One of the parameters characterizing the performance of a GNSS receiver is the Time to First Fix (TTFF). TTFF indicates the time required for a GNSS device to get and process adequate satellite signals and data to provide accurate positional information (a “fix”). GNSS receivers use the following sets of data to provide accurate position •Satellite signals,•Timing information (e.g. GPS time),•Almanac data,•Ephemeris data.If a GNSS device has been turned off for a long period of time the acquired information can expire and, when it is turned on again, it will take longer to re-acquire these data sets, resulting in a longer "Time to First Fix". One way to speed up the TTFF is to use the Assisted-GPS (A-GPS) Positioning Technique.A-GPS is based on the use of a data connection (e.g. a cellular network) to provide predicted satellite information from an A-GPS server to the GNSS receiver. With the help of this data, the receiver is usually able to achieve a positional fix faster than using live-data only. Although the term “A-GPS” is commonly used, the server-based data can refer to other constellations as well (e.g. GLONASS predictions).A "cold" start indicates the scenario in which the GNSS receiver must get all data in order to start navigation and may take up to several minutes.A "warm" start indicates the scenario in which the GNSS has most of the data it needs in memory, and will start quickly, a minute or less.A “hot” start refers to the scenario in which the receiver has all the data from the satellites (time, almanac, ephemeris) and only needs to calculate the positional solution. The fix is usually acquired in few seconds.In other words, the use of A-GPS allows the device to start in a condition similar to “warm” and “hot”, hence speeding up the TTFF.3. GNSS SOLUTIONStandalone GNSSStandalone (or autonomous) GNSS mode is a feature that allows the GNSS receiver, installed on the cellular module, to perform First Fixing activity without assistance data coming from the network. The GNSS receiver estimates position directly from satellites (GPS, GLONASS, etc.) in line of sight.To set up the GNSS receiver in standalone mode the user should go through the following steps provided as example. It should be noted that, although modern cellular modules integrate a GNSS receiver rather than a GPS one, the AT commands still refer to GPS for legacy reasons.Switch off/on the module and restore the default GNSS parameters in order to start from a known GNSS setting.AT$GPSRSTOKDelete the GPS information stored in NVM. It is the history buffer interfacing the GPS receiver to the module. This action is not mandatory; it should be performed only if you need to clean the buffer:AT$GPSNVRAM=15,0OKCheck that after history buffer cleaning no GPS information is availableAT$GPSACP$GPSACP:OKStart the GNSS receiver in standalone mode:AT$GPSP=1OKFor enabling unsolicited messages of GNSS data in NMEA format, refer to [2]. In this example, only RMC sentence is enabled:AT$GPSNMUN=3,0,0,0,0,1,0OKThis command enables the GNSS data stream format and reserve the AT interface port for the NMEA stream only.After a time-interval depending from the environmental characteristic of the location where the GNSS receiver operates (outside, inside, city, etc.), the continuous streaming of RMC sentences becomes populated.To stop the NMEA stream enter the following escape sequence:+++Figure 3-1 Enabling the NMEA stream, RMC sentence onlyFor enabling additional NMEA sentences containing information on other constellations (e.g. GLONASS or GALILEO), refer to the following commands described in [2]:AT$GPSGLOAT$GPSNMUNAT$GPSNMUNEXFinally, for polling the current location:AT$GPSACP$GPSACP:152324.000,4542.8396N,01344.2874E,3.00,310.0,3,000.00,0.00,0.00,200412,05OKA-GPS – Secure User Plane Location (SUPL)As mentioned in previous sections, Assisted GPS mode is a feature that allows the GNSS receiver to perform its First Fix faster using assistance data, usually provided over the cellular network.The LE910Cx/ME910C1/ML865C1/NE910C1 series supports the following type of A-GPS •Secure User Plane Location (SUPL) was proposed by OMA3.2.1.1. MS-Based modeIn MS-Based mode, the module requires assistance data to the SLP Server. The A-GPS receiver, installed on the module, receives the signals from the visible satellites and with the help of the data received from the SLP Server calculates its position.For the MS-Based mode, an example is provided below. It should be noted that in this configuration an example of SUPL Server is provided: however, it is responsibility of the user to select the appropriate server fitting their needs.The following assumptions have been made:•the module is powered off;•the GNSS antenna is connected and placed in sight of satellites (must be able to receive GNSS signal);•cellular antenna is connected;•SIM card is inserted;•APN is already set.Firstly, turn on the cellular module.If required, delete the GNSS information stored in NVM. It is the history buffer between the GNSS device and the module. This action is not mandatory and should be performed only if cleaning the buffer is needed:AT$GPSR=0AT$GPSNVRAM=15,0Check that after history buffer cleaning no GNSS information are available (command response should be empty and have no location information)AT$GPSACP$GPSACP:Set the SUPL version support to 2.0AT$SUPLV=2S et the location’s Quality of Service (QoS). AT$GPSSAV command can be used to save GPS parameters into NVM.AT$GPSQOS=50,50,150,0Set the selected SLP address and port numberAT$LCSSLP=<slp_address_type>,<slp_address>,<port number>For example:AT$LCSSLP=1,"",7276Enable SUPL TLSAT$LCSTER=1,,,0 // non-secure modeAT$LCSTER=1,,,1 // secure modeLock <cid> for SUPL use:AT$LCSLK=1,<cid>For example:AT$LCSLK=1,1Activate the PDP contextAT#SGACT=1,1 //returns a list of IP addresses for the specified contextStart the SET Initiated Session using the MS-Based mode:AT$GPSSLSR=1,1,,,,,1OKNow poll the acquired position through AT$GPSACP command until location information is returned.AT$GPSACP$GPSACP:152324.000,4542.8396N,01344.2874E,3.00,310.0,3,000.00,0.00,0.00,200412,05OKIt must be returned within few seconds (less than ten seconds)Full test sequence non-secure Mode:Full test sequence secure Mode:4. GLOSSARY AND ACRONYMSDescription3GPP Third Generation Partnership ProjectA-GPS Assisted-Global Positioning SystemC-Plane Network Control Plane NetworkDTE Data Terminal EquipmentECEF Earth-Centered Earth-FixedGMLC Gateway Mobile Location CenterGNSS Global Navigation Satellite SystemGPS Global Positioning SystemLCS LoCation ServiceMO-LR Mobile Originated-Location RequestMS Mobile StationMT-LR Mobile Terminated-Location RequestNMEA National Marine Electronics AssociationNVM Non-Volatile MemoryOMA Open Mobile AlliancePDP Packet Data ProtocolSET SUPL Enable TerminalS-GNSS Standalone-Global Navigation Satellite System S-GPS Standalone-Global Positioning SystemSLP SUPL Location PlatformSMLC Serving Mobile Location CenterSMS Short Message ServiceSSL Secure Socket LayerSUPL Secure User Plane LocationTTFF Time to First FixUART Universal Asynchronous Receiver Transmitter URC Unsolicited Result Code5. DOCUMENT HISTORYRevision Date Changes0 2019-02-14 First issue1 2019-07-08 Updated applicability table2 2019-11-22 Added example and configuration secure mode]7 1。