瑞萨单片机M32C NC308WA有效的编程技术(培训资料)

项目二32灯电路的制作【教学目标要求】1、知识目标（1）进一步强化W A VE、PROTEUS软件的使用。

（2）掌握C语言和汇编语言的综合设计程序；熟练汇编语言的程序设计及调试、排障。

（3）掌握单片机电路的制作技能，制作32灯电路。

2、技能目标强化对W A VE、PROTEUS等软件的综合使用，加强程序的编写、调试、排障，实物电路的电子技能制作。

3、情感目标以小组协作形式开展学习，完成项目任务；养成良好的职业习惯，增强学生的分析、操作、研究创新的能力以及与小组合作、沟通能力。

4、节能、环保，健康、安全教育目标要求学生安全用电、爱护实验、实训设备，节约用电，不乱扔费弃物；培养学生良好的学习习惯。

【教学内容分析】本项目主要是单片机的综合应用实训，加强学生对软件的综合使用与提高，电路的设计、程序的编写、调试、排障等内容。

主要包括以下学习任务：任务一绘制32灯仿真电路图（2课时）任务二32灯电路制作实训1（2课时）任务三绘制32灯底板线路图（2课时）任务四32灯程序设计实训1（2课时）任务五32灯电路制作实训2（2课时）任务六32灯程序设计实训2（2课时）任务七32灯电路制作实训3（2课时）【教学重点与难点】重点：（1）电路的灵活设计与布局；（2）实训过程中的排障。

难点：（1）电路的设计；（2）汇编程序的设计与调试；（3）实物电路制作。

【教学方法和策略】布置学生5～6人为一组，分成6个学习小组。

采用实物演示、现场操作、小组合作探究、讲授等教学方法，具体教学策略是：1、书面作业先让学生自学本项目各任务的内容，收集相关资料，归纳本项目的主要知识点，初步完成书面作业。

2、展示交流各学习小组在课堂上汇报、展示前置作业成果，各小组间进行交流、质疑，小组长记录组员的表现。

教师在小组进行汇报、展示的过程中，巡视指导，并对各小组的表现进行点评并记录成绩。

3、教师评析教师根据学生掌握知识的情况，再次进行相关知识的补充、讲解。

瑞萨单片机发脉冲程序瑞萨单片机是一种常用的微控制器，广泛应用于各种电子设备中。

在很多应用中，我们需要通过单片机来发出脉冲信号，用于控制其他设备的工作。

下面，我将介绍一种简单的瑞萨单片机发脉冲程序。

首先，我们需要准备好开发环境。

瑞萨单片机的开发环境可以使用Renesas Flash Programmer (RFP)软件进行编程。

在安装好RFP软件后，我们需要连接好单片机与电脑，并确保电脑能够正确识别单片机。

接下来，我们需要编写发脉冲的程序。

在RFP软件中，我们可以使用C语言来编写单片机的程序。

下面是一个简单的发脉冲程序示例：```c#include <stdint.h>#include <iodefine.h>void delay(uint32_t count) {while(count--);}int main(void) {SYSTEM.PRCR.WORD = 0xA502;MPC.PWPR.BIT.B0WI = 0;MPC.PWPR.BIT.PFSWE = 1;PORTA.PDR.BIT.B0 = 1;MPC.PA0PFS.BIT.PSEL = 0x01;MPC.PWPR.BYTE = 0x80;SYSTEM.PRCR.WORD = 0xA500;while(1) {PORTA.PODR.BIT.B0 = 1;delay(1000000);PORTA.PODR.BIT.B0 = 0;delay(1000000);}return 0;}```在这个程序中，我们首先定义了一个延时函数delay，用于控制脉冲的频率。

然后，在main函数中，我们对单片机的端口进行了配置，将A端口的第0位设置为输出模式。

接着，我们使用一个无限循环来不断发出脉冲信号。

在循环中，我们先将A端口的第0位设置为高电平，延时一段时间后再将其设置为低电平，再延时一段时间，如此循环。

最后，我们需要将程序下载到单片机中。

瑞萨单片机发脉冲程序1. 引言本文将介绍如何使用瑞萨单片机来编写一个发脉冲的程序。

我们将首先介绍瑞萨单片机的基本知识，然后详细讲解如何编写发脉冲的程序，并提供示例代码和详细的步骤说明。

2. 瑞萨单片机简介瑞萨单片机是一种常用的嵌入式系统开发工具，它具有高性能、低功耗、易于开发和广泛的应用领域等特点。

瑞萨单片机通常使用汇编语言或C语言进行编程，并可以通过编程器将程序下载到单片机中运行。

3. 发脉冲程序设计发脉冲程序是一种常见的应用场景，它可以用于控制外部设备的工作。

在本节中，我们将介绍如何使用瑞萨单片机编写一个简单的发脉冲程序。

3.1 硬件准备在编写发脉冲程序之前，我们需要准备以下硬件设备：•瑞萨单片机开发板•发脉冲的外部设备（例如LED、继电器等）•连接线3.2 程序设计3.2.1 引入头文件首先，在程序的开头，我们需要引入瑞萨单片机的相关头文件。

这些头文件包含了一些常用的函数和宏定义，可以方便我们进行编程。

#include <reg51.h>3.2.2 定义IO口接下来，我们需要定义用于发脉冲的IO口。

在瑞萨单片机中，IO口通常用P0、P1、P2、P3等寄存器来表示。

我们可以通过设置这些寄存器的值来控制IO口的电平。

sbit pulse_pin = P1^0; // 定义发脉冲的IO口3.2.3 编写发脉冲函数现在，我们可以编写一个发脉冲的函数。

该函数将会在IO口上产生一个脉冲信号，并控制外部设备的工作。

void pulse(){pulse_pin = 1; // IO口置高，产生脉冲信号delay(1000); // 延时1秒pulse_pin = 0; // IO口置低，停止脉冲信号delay(1000); // 延时1秒}3.2.4 主函数调用最后，在主函数中调用发脉冲函数，以便在单片机上运行该程序。

void main(){while(1){pulse(); // 调用发脉冲函数}}3.3 编译和下载程序完成程序的编写后，我们需要将程序编译并下载到瑞萨单片机中运行。

瑞萨MCU在汽车仪表及R32C/100应用中的解决方案瑞萨科技致力于提供移动通信、汽车电子以及PC/AV（数码家电）领域的半导体解决方案。

在全球汽车半导体市场中，瑞萨占有7.1%的市场份额，排名第四位；在日本市场中占据第一位，市场份额为22.3%。

其汽车半导体解决方案包含了安全、信息、动力总成、底盘以及车身五个方面，其中每个方面都有多种解决方案。

汽车仪表解决方案仪表MCU的特点分以下几个方面：1.内嵌步进电机PWM控制器：可直接控制和驱动4-6个步进电机，无需外驱动器IC，因此可以节省成本和布局空间，具有优良的EMI/EMC性能；2.内嵌LCD控制器：28/32段×4公共引脚，可以直接控制LCD，同样无需外置驱动器IC，因此可以节省成本和布局空间，具有优良的EMI/EMC性能；3.高速CPU：单指令周期，20MHz的H8S最小指令执行时间为50ns，而40MHz 的H8SX最小指令执行时间是25ns；4.强大的定时器：片上16位定时器脉冲单元有三个16位定时器通道，包括输入捕捉、输出比较、PWM和相位计算。

R32C/100特殊模块的基本功能，包括三个部分：定时器脉冲单元（TPU）；步进电机PWM控制器和LCD控制器。

TPU是由3个16位定时器通道组成，包括最多8个脉冲输入/输出，可以为每个通道设置：比较匹配的波形输出；输入捕捉功能；计数器清零操作；同步运行；定时器计数器能够同时写入；可以比较匹配与输入捕捉同时清零；利用同步计数器操作实现寄存器同时输入/输出；与同步运行结合的最大7相位PWM 输出。

致芯科技最具实力的芯片解密、IC解密、单片机解密等解密服务机构，致芯科技拥有多年的解密服务经验和超高水平的解密技术，一直从客户利益出发，为每位客户提供最科学最合理最低成本的解密方案与解密服务，深受客户的信赖与喜爱。

对于LCD控制器/驱动器，其重要功能有：28/32段×4公共引脚；段输出引脚可用作11个帧频的4组端口选择；A或B波形可以用软件进行选择；内置电源分离电阻；除了待机模式和模块停止模式外，还有操作模式显示。

平凡老师的单片机教程作者：平凡第一节初学单片机几个不易掌握的概念第二节新8051教程---前言第三节单片机概述第四节单片机内、外部结构分析一第五节半导体储存器第六节单片机内、外结构分析二第七节单片机内、外结构分析三第八节单片机内、外结构分析四第九节单片机内、外结构分析五第十节寻址方式与指令系统第十一节单片机指令二数据传递类指令第十二节单片机指令三累加器A 与片外RAM 之间的数据传递类指令第十三节单片机指令四算述运算类指令第十四节单片机指令五逻辑运算类指令第十五节单片机指令六条件转移指令第十六节单片机指令七位及位操作指令第十七节计数器与定时器第十八节计时/计数器的方式控制字第十九节中断系统第二十节定时、中断练习一第二十一节定时、计时练习二第二十二节串行接口第二十三节串行接口应用编程实例第二十四节常用接口电路及基编程第二十五节动太扫描显示接口第二十六节键盘接口与编程第二十七节矩阵式键盘接口技术及编程单片机扩展一单片机扩展二单片机扩展三单片机扩展四单片机扩展五第一节初学单片机几个不易掌握的概念随着电子技术的迅速发展，计算机已深入地渗透到我们的生活中，许多电子爱好者开始学习单片机知识，但单片机的内容比较抽象，相对电子爱好者已熟悉的模拟电路、数字电路，单片机中有一些新的概念，这些概念非常基本以至于一般作者不屑去谈，教材自然也不会很深入地讲解这些概念，但这些内容又是学习中必须要理解的，下面就结合本人的学习、教学经验，对这些最基本概念作一说明，希望对自学者有所帮助。

一、总线：我们知道，一个电路总是由元器件通过电线连接而成的，在模拟电路中，连线并不成为一个问题，因为各器件间一般是串行关系，各器件之间的连线并不很多，但计算机电路却不一样，它是以微处理器为核心，各器件都要与微处理器相连，各器件之间的工作必须相互协调，所以就需要的连线就很多了，如果仍如同模拟电路一样，在各微处理器和各器件间单独连线，则线的数量将多得惊人，所以在微处理机中引入了总线的概念，各个器件共同享用连线，所有器件的8 根数据线全部接到8 根公用的线上，即相当于各个器件并联起来，但仅这样还不行，如果有两个器件同时送出数据，一个为0 ，一个为1 ，那么，接收方接收到的究竟是什么呢？这种情况是不允许的，所以要通过控制线进行控制，使器件分时工作，任何时候只能有一个器件发送数据（可以有多个器件同时接收）。

Sigmastar SSC335全功能开发板技术手册一、应用场合：1. 适用于开发以下产品：（1）200万/300万网络摄像机。

（2）300万抓拍摄像机。

（3）安防监控产品。

（4）网络音视频产品。

（5）低功耗快速启动摄像机。

（6）4G/WIFI无线传输产品。

（7）编码器。

（8）双路摄像机。

（9）运动相机。

（10）航拍摄像机。

（11）UVC相机。

2. 适用于学习linux平台、熟悉ARM开发的开发者。

3. 适用于需要熟悉sigmstar平台音视频编解码、图像处理、UVC相机、4G/WIFI无线传输的开发人员。

二、型号：CA-M3335AID-MAIN-V1三、产品特色：■主控芯片采用Sigamastar高性能多媒体处理器片上系统(SOC)，，内部集成A7、FPU、NEON，主频800MHZ。

■支持WDR、多级降噪及多种图像增强和矫正算法，为客户提供专业级的图像质量。

■采用标准的H.264/H.265 High Profile压缩算法，方便在窄带上实现高清晰的图像传输。

■最大支持300万编码.最高支持2304x1296@30帧、2048*1536@30帧、1920x1080@45帧H.264/H.265编码。

■内置1Gb DDR2。

■支持MIPI、USB Sensor输入、图像质量优异。

■支持双向语音对讲。

■支持ONVIF2.4标准协议，可对接海康、大华、雄迈等NVR。

■支持GB28181协议。

■支持手机监看。

■支持4G全网通：5模或者7模。

■支持WIFI：热点和STA模式。

■支持GPS、北斗定位。

■支持POE供电，功率13W，符合IEEE802.3af/at标准■支持二次开发。

■尺寸26*24mm，邮票孔。

方便做小型化产品。

■接口全，且与本公司其他主控、平台定义一致，适合兼容多款产品。

四、技术参数：五、产品外观及接口定义：J24：音频输入1.AIN0(左)2.音频地3.AIN1(右)J5：报警/485接口1.报警输出22.报警输出13. RS485正4. RS485负4. RS485_D+J15：SD 外接接口1. SD_DATA22. SD_DATA33. SD_CMD 4. 3.3V 5. SD_CLK J2：接POE 模块脚位接口定义主控pin脚接口类型电平功能描述说明1 SD_CDZ19 输入 3.3V SD卡插入检测低电平有效2 SD_DATA1 81 输入/输出 3.3V SD卡数据13 SD_DATA0 79 输入/输出 3.3V SD卡数据04 SD_CLK 77 输出 3.3V SD卡时钟50MHz5 GND 地数字地6 SD_CMD 78 输出 3.3V SD卡命令信号7 SD_DATA3 82 输入/输出 3.3V SD卡数据38 SD_DATA2 81 输入/输出 3.3V SD卡数据29 NC10 NC11 NC12 NC13 NC14 NC15 NC16 LINK_LAN 输入/输出 3.3V 网络连接状态指示输出高，网络连接成功连接网口RJ45绿灯17 ACT_LAN 输入/输出 3.3V 网络数据传输指示高/低切换：有数据传输，切换速度指示传输速度。

瑞萨单片机入门教程本教程以R7F0C002L单片机为例一、开发环境下载安装与工程注意：该工程目录和工程名不能含有中文1.1、 CubeSuite+环境的下载：官网下载地址将安装环境下载到本地，该文件大小532M在安装过程中有提示需要填写注册码，请输入以下注册码，如果无效请联系供应商。

查看是否已经注册：在IDE环境中选择 Help->About后有下面窗口：注册码：67DCS-V3Q7L-XMGL9-FI6L9-EE1BJ该注册码有限制台数的，一旦注册了就会把MAC绑定，重装无需注册！当有以下报错时：请查看是否已经注册。

1.2、按照一般的软件安装方法安装好IDE环境，下面介绍IDE环境的配置：1、将DIF_RFP文件夹下的Device_Custom文件夹拷贝到安装目录下的C:\Program Files\Renesas Electronics\CubeSuite+下（这里是默认的安装目录，另外注意：DIF_RFP中Readme_Device_Custom.txt说将Device_Custom文件夹拷贝到C:\Program Files\Renesas Electronics\CubeSuite+\Device下，但是实际上不可以！）。

DIF_RFP文件夹安装根目录当配置成功以后会在芯片族里面多出R7F系列的单片机，如下图示：2、将DIF_RFP文件夹下的RFP_R7F0C002L_V10000子目录下面的两个文件（Device_Custom文件夹和Custom_Productlist.xml文件）拷贝到安装目录下的C:\Program Files\Renesas Electronics\Programming Tools\Renesas Flash Programmer V2.01\Device下（这里是默认安装路径）。

1.3、开发环境新建工程：1、启动CubeSuite+环境，会弹出如下启动界面：2、创建Project工程，在上述启动界面中，点击Creat New Project栏中GO按钮，将会弹出以下对话框：选择工程路径创建输入工程名选择芯片型号选择芯片族3、点击Create创建工程，会得到如下工程界面：4、通过生成工具生成一个简单的代码：5、将芯片型号换成R7F0C002单片机，并且将选项字节配置好！详细设置请参考第三章代码生成与编码。

M16C族编程技巧(M3T-NC30WA 工具链)2005年2月M3T-NC30WA 特点•支持MCU M16C 族-M16C/60, 30, 20, 10, R8C/Tiny 系列.•性能(Performance) 可以减小ROM大小的辅助功能强大的提高代码效率的优化功能•存储器型号(Memory model) 支持每个变量的near/far限定词•扩展功能(Extended functions)支持嵌入式系统的#pragma指令　•附加工具(Attached tools)IDE -TM 和HEW, 结构汇编器(Structured assembler) 和模拟器(Simulator).M3T-NC30WA存储器分配(Memory allocation )near/far#pragma ADDRESS #pragma BITADDRESS #pragma SECTION #pragma STRUCTetc减小ROM 大小(Reducing ROM size )#pragma SBDATA #pragma SPECIAL #pragma JSRA/JSRW#pragma BIT UTLxx etc 其他#pragma INTERRUPT #pragma PARAMETER #pragma ASM/ENDASM #pragma INTCALLasm( ) etcRTOS#pragma ALMHANDLER #pragma CYCHANDLER #pragma INTHANDLER #pragma TASK提高性能!减小系统消耗(Reduce OS overhead )给不同系统分配存储器!#pragma 扩展功能(Extended Functions)NEAR 修饰符–000000H ~ 00FFFFH 区域FAR 修饰符–000000H ~0FFFFFH 区域每个变量都有Near 和far指定near/far默认ROM areaSFRRAM areanear RAM far ROMFFFF1Mbytesnear areafar areaint near i;int far j;注意: 程序已固定far 属性FFFF默认是NEAR 指针j i *i int * i ;k*k int far * k;FFFFint far * far j ;*j#pragma ADDRESS port 03ECH#pragma ADDRESS base 100H extern int base;#pragma ADDRESS base2 _base+2H extern int base2;#pragma ADDRESS base3 _base+4H extern int base4;不仅对I/O 变量，对RAM 中的变量也很方便.Same as#define base *(volatile int *)0x100#pragma 地址指定变量的绝对地址 可以被用作设定SFR 区#pragma INTERRUPT /B func()Using bank registersvoid func( void ){}R0FB R1R2A0R3A1将后寄存器切换到前寄存器R0FB R1R2A0R3A1R0FBR1R2A0R3A1SB将寄存器切换到后寄存器R0FB R1R2A0R3A1SB声明中断处理器(interrupt handler) /B 使中断处理加快#pragma INTERRUPT /E func() 允许中断(FSET I) 保存寄存器获得自动变量区 释放自动变量区 恢复寄存器 REITvoid func(void){}出口入口/E 允许多个中断支持可以通过下列方式指定中断向量表号＃pragma INTERRUPT Vector number Function_nameOr＃pragma INTERRUPT Function_name(vect= Vector number )使用编译选项–fmake_vector_table 自动生成变量中断表.#pragma INTERRUPT timerA0(vect=21)void timerA0(void){}.section __NC_rvector,ROMDATA .rvector 21,_timerA0asm function汇编语言可以被直接包含在C 程序中格式是asm(““). 例如: asm(“FSETI”); 使用“$$, $b, $@”来参考参数或自动变量.用户不需要考虑变量的存储类(storage class).asm(“mov.w R0,$@”, value );FB offsetSymbol Register-2[FB]_value R0对于变量:对于位字段:asm(“bset $b”, bit.b1 );Bit position,Symbol1,_bit可以在C 中编写长汇编源代码.int asmRoutine(int arg){return work;分配工作区供汇编代码使用.int work;将工作区的偏移(offset)设置在堆栈上asm (“在#pragma ASM 和#pragma ENDASM 之间编写长汇编源程序.#pragma ASMmov.w R0,work[FB]...#pragma ENDASM注意1 : 不要破坏asm 函数中的寄存器.int func(long arg){register int ret=0;#pragma ASMmov.l #00000000H,R2R0mov.l #_addr,A0mov.l #_addr2,A1mov.w _counter,R3rmpa.wmov.l R2R0,_result #pragma ENDASM………..return ret;}参考并修改寄存器保存寄存器恢复寄存器pushm R0,R2,R3,A0,A1popm R0,R2,R3,A0,A1注意2 : 不要写入会引起汇编源程序控制流混乱的转移(branch)指令。

单片机培训华清远见（一）引言概述：华清远见单片机培训是一门系统性的培训课程，旨在帮助学员快速入门并掌握单片机的基本原理与应用。

通过本培训，学员将学习到单片机的硬件结构、编程语言、电子系统设计以及实际应用案例等方面的知识。

本文将分五个大点详细阐述单片机培训华清远见的内容。

正文：一、单片机基础知识1. 单片机的定义和分类2. 单片机的工作原理和基本架构3. 单片机常用的编程语言和开发工具4. 单片机的输入输出方式和中断处理机制5. 单片机的时钟源和时序控制二、单片机编程技术1. 单片机常用编程语言的基本语法和数据类型2. 单片机的程序结构和调试技巧3. 单片机的位操作和存储器管理4. 单片机的中断编程和定时器计数器应用5. 单片机与外设的通信和控制技术三、单片机硬件设计1. 单片机的外部器件和电路连接2. 单片机的IO口电平转换和电源管理3. 单片机的AD/DA转换和PWM输出4. 单片机的串行通信接口和总线控制5. 单片机的外设扩展和程序存储器扩展四、单片机应用案例1. 单片机在智能家居系统中的应用2. 单片机在工业自动化控制中的应用3. 单片机在汽车电子系统中的应用4. 单片机在医疗设备中的应用5. 单片机在网络通信系统中的应用五、单片机培训总结通过华清远见单片机培训，学员将全面了解单片机的基本原理和应用技术，具备独立设计和开发单片机应用系统的能力。

无论是从理论知识，还是从实践案例，本培训都将为学员提供充分的学习资源和实践机会。

掌握单片机技术将为学员在相关行业的就业和职业发展提供有力的支持。

总结：本文针对华清远见单片机培训进行了详细的阐述。

通过系统的培训内容，学员将全面掌握单片机的基本原理、编程技术、硬件设计和应用案例等方面的知识。

这将为学员提供丰富的学习资源和实践机会，使他们具备独立设计和开发单片机应用系统的能力，为未来的职业发展打下坚实基础。

M32C/8A GroupRENESAS MCUREJ03B0213-0110Rev.1.10Jul 15, 20071.Overview1.1FeaturesThe M32C/8A Group is a single-chip control MCU, fabricated using high-performance silicon gate CMOS technology, embedding the M32C/80 Series CPU core. The M32C/8A Group is housed in 144-pin and 100-pin plastic molded LQFP packages.With a 16-Mbyte address space, this MCU combines advanced instruction manipulation capabilities to process complex instructions by less bytes and execute instructions at higher speed.The M32C/8A Group has a multiplier and DMAC adequate for office automation, communication devices and industrial equipment, and other high-speed processing applications.1.1.1ApplicationsAudio, cameras, office/communication/portable equipment, etc.1.1.2SpecificationsTables 1.11.3 to 1.4 lists the specifications of the M32C/8A Group.The M32C/8A Group is ROMless device.Use the M32C/8A Group in microprocessor mode after reset.Item Function SpecificationCPU Central processing unit M32C/80 core (multiplier: 16 bits × 16 bits → 32 bits,multiply-addition operation instructions: 16 × 16 + 48 → 48 bits)•Basic instructions: 108•Minimum instruction execution time:31.3 ns ( f(CPU) = 32 MHZ / VCC1 = 4.2 to 5.5 V)41.7 ns ( f(CPU) = 24 MHZ / VCC1 = 3.0 to 5.5 V)•Operating mode: microprocessor modeMemory ROM, RAM See Table 1.5 Product List.Power Supply Voltage Detection Vdet3 detection function, Vdet4 detection function,cold start/warm start determination functionExternal Bus Expansion Bus / memory expansionfunction•Address space: 16 Mbyte•External bus interface: 1 to 7 wait states can be inserted,4 chip select outputs, 3 V and5 V interfaces•Bus format: Switchable between separate and multiplexed busformats, switchable data bus width (8-bit or 16-bit)Clock Clock generation circuits•4 circuits:Main clock, sub clock, on-chip oscillator,PLL frequency synthesizer•Oscillation stop detection:Main clock oscillation stop detection function•Frequency divider circuit:Dividing ratio selectable among 1, 2, 3, 4, 6, 8, 10, 12, 14, 16•Low power consumption features: Wait mode, stop mode Interrupts•Interrupt vectors: 70•External interrupt inputs:NMI × 1INT × 3 (16-bit external bus width)INT × 6 (8- bit external bus width)Key input × 4•Interrupt priority levels: 7Watchdog Timer15-bit × 1 (with prescaler)DMA DMAC•4 channels, cycle steal method•Trigger sources: 31•Transfer modes: 2 (single transfer and repeat transfer) DMAC II•Can be activated by all peripheral function interrupt sources•Transfer modes: 2 (single transfer and burst transfer)•Immediate transfer, calculation transfer, and chain transferfunctionsTimer Timer A16-bit timer × 5Timer mode, event counter mode, one-shot timer mode,pulse width modulation (PWM) mode)Event counter 2-phase pulse signal processing (2-phaseencoder input) × 3Timer B16-bit timer × 6Timer mode, event counter mode, pulse period measurementmode, pulse width measurement modeTimer function for3-phase motor control 3-phase inverter control × 1 (using timer A1, timer A2, timer A4, and timer B2)On-chip dead time timerNOTES:1.IEBus is a registered trademark of NEC Electronics Corporation.2.Please contact a Renesas sales office to use the optional feature.Item FunctionSpecificationSerial InterfaceUART0 to UART4Clock synchronous / asynchronous × 5I 2C bus (optional)(2), special mode 2, GCI mode, SIM mode IEBus (optional)(1)(2)A/D Converter10-bit resolution x 18 channels, includes sample and hold functionD/A Converter8-bit resolution × 2 channelsCRC Calculation CircuitCRC-CCITT (X 16 + X 12 + X 5 + 1) compliantX/Y Converter 16 bits x 16 bits I/O Ports Programmable I/O ports •Input only: 1•CMOS I/O:81 (8-bit external bus width)73 (16-bit external bus width)with selectable pull-up resistor •N channel open drain ports: 2Operating Frequency / Supply Voltage32 MHz: VCC1 = 4.2 to 5.5 V, VCC2 = 3.0 to VCC124 MHz: VCC1 = 3.0 to 5.5 V, VCC2 = 3.0 to VCC1Current Consumption 28 mA (32 MHz / VCC1 = VCC2 = 5 V)22 mA (24 MHz / VCC1 = VCC2 = 3.3 V)45 μA (approx. 1 MHz / VCC1 = VCC2 = 3.3 V,on-chip oscillator low-power consumption mode → wait mode)0.8 μA (VCC1 = VCC2 = 3.3 V, stop mode)Operating Ambient Temperature (°C)-20 to 85°C, -40 to 85°C (optional)(2)Package144-pin LQFP (PLQP0144KA-A)Item Function SpecificationCPU Central processing unit M32C/80 core (multiplier: 16 bits × 16 bits → 32 bits,multiply-addition operation instructions: 16 × 16 + 48 → 48 bits)•Basic instructions: 108•Minimum instruction execution time:31.3 ns (f(CPU) = 32 MHZ / VCC1 = 4.2 to 5.5 V)41.7 ns (f(CPU) = 24 MHZ / VCC1 = 3.0 to 5.5 V)•Operating mode: microprocessor modeMemory ROM, RAM See Table 1.5 Product List.Power Supply Voltage Detection Vdet3 detection function, Vdet4 detection function,cold start/warm start determination functionExternal Bus Expansion Bus / memory expansionfunction•Address space: 16 Mbyte•External bus interface: 1 to 7 wait states can be inserted,4 chip select outputs, 3 V and5 V interfaces•Bus format: Switchable between separate bus and multiplexedbus formats, switchable data bus width (8-bit or 16-bit)Clock Clock generation circuits•4 circuits:Main clock, sub clock, on-chip oscillator,PLL frequency synthesizer•Oscillation stop detection:Main clock oscillation stop detection function•Frequency divider circuit:Dividing ratio selectable among 1, 2, 3, 4, 6, 8, 10, 12, 14, 16•Low power consumption features: Wait mode, stop mode Interrupts•Interrupt vectors: 70•External interrupt inputs:NMI × 1INT × 3 (16-bit external bus width)INT × 6 (8- bit external bus width)Key input × 4•Interrupt priority levels: 7Watchdog Timer15-bit × 1 (with prescaler)DMA DMAC•4 channels, cycle steal method•Trigger sources: 31•Transfer modes: 2 (single transfer and repeat transfer) DMACII•Can be activated by all peripheral function interrupt sources•Transfer modes: 2 (single transfer and burst transfer)•Immediate transfer, calculation transfer, and chain transferfunctionsTimer Timer A16-bit timer × 5Timer mode, event counter mode, one-shot timer mode,pulse width modulation (PWM) modeEvent counter 2-phase pulse signal processing (2-phaseencoder input) × 3Timer B16-bit timer × 6Timer mode, event counter mode, pulse period measurementmode, pulse width measurement modeTimer function for3-phase motor control 3-phase inverter control × 1 (using timer A1, timer A2, timer A4, and timer B2)On-chip dead time timerNOTES:1.IEBus is a registered trademark of NEC Electronics Corporation.2.Please contact a Renesas sales office for optional features.Item FunctionSpecificationSerial InterfaceUART0 to UART4Clock synchronous / asynchronous × 5I 2C bus (optional)(2), special mode 2, GCI mode, SIM mode IEBus (optional)(1)(2)A/D Converter10-bit resolution x 10 channels, includes sample and hold functionD/A Converter8-bit resolution × 2 channelsCRC Calculation CircuitCRC-CCITT (X 16 + X 12 + X 5 + 1) compliantX/Y Converter 16 bits x 16 bits I/O Ports Programmable I/O ports •Input only: 1•CMOS I/O:45 (8-bit external bus width)37 (16-bit external bus width)with selectable pull-up resistor •N channel open drain ports: 2Operating Frequency / Supply Voltage32 MHz: VCC1 = 4.2 to 5.5 V, VCC2 = 3.0 to VCC124 MHz: VCC1 = 3.0 to 5.5 V, VCC2 = 3.0 to VCC1Current Consumption 28 mA (32 MHz / VCC1 = VCC2 = 5 V)22 mA (24 MHz / VCC1 = VCC2 = 3.3 V)45 μA (approx. 1 MHz / VCC1 = VCC2 = 3.3 V,on-chip oscillator low-power consumption mode → wait mode)0.8 μA (VCC1 = VCC2 = 3.3 V, stop mode)Operating Ambient Temperature (°C)-20 to 85°C, -40 to 85°C (optional)(2)Package100-pin LQFP (PLQP0100KB-A)1.2Product ListTable 1.5 lists product information. Figure 1.1 shows product numbering system.Table 1.5Product List (M32C/8A) Current as of July. 2007(P): Under planningFigure 1.1Product Numbering SystemType No.PackageROM CapacityRAM CapacityRemarksM308A0SGP PLQP0100KB-A (100P6Q-A)−12KB ROMless M308A3SGP (P)PLQP0100KB-A (100P6Q-A)24KB ROMless M308A5SGP (P)PLQP0144KA-A (144P6Q-A)24KBROMless1.3Block DiagramFigure 1.2 shows a M32C/8A Group block diagram.1.4Pin AssignmentsFigures 1.3 and 1.4 show a pin assignment (top view).PinControl Pin Port Interrupt Pin Timer Pin UART Pin Analog Pin Bus Control Pin No.1P9_6TXD4/SDA4/SRXD4ANEX12P9_5CLK4ANEX03P9_4TB4IN CTS4/RTS4/SS4DA14P9_3TB3IN CTS3/RTS3/SS3DA05P9_2TB2IN TXD3/SDA3/SRXD36P9_1TB1IN RXD3/SCL3/STXD37P9_0TB0IN CLK38P14_69P14_510P14_411P14_312P14_213P14_114P14_015BYTE16CNVSS17XCIN P8_718XCOUT P8_619RESET20XOUT21VSS22XIN23VCC124P8_5NMI25P8_4INT226P8_3INT127P8_2INT028P8_1TA4IN/U29P8_0TA4OUT/U30P7_7TA3IN31P7_6TA3OUT32P7_5TA2IN/W33P7_4TA2OUT/W34P7_3TA1IN/V CTS2/RTS2/SS235P7_2TA1OUT/V CLK236P7_1TA0IN/TB5IN RXD2/SCL2/STXD237P7_0TA0OUT TXD2/SDA2/SRXD238P6_7TXD1/SDA1/SRXD139VCC140P6_6RXD1/SCL1/STXD141VSS42P6_5CLK143P6_4CTS1/RTS1/SS144P6_3TXD0/SDA0/SRXD045P6_2RXD0/SCL0/STXD046P6_1CLK047P6_0CTS0/RTS0/SS048P13_749P13_650P13_5PinControl Pin Port Interrupt Pin Timer Pin UART Pin Analog Pin Bus Control Pin No.51P13_452P5_7RDY53P5_6ALE54P5_5HOLD55P5_4HLDA/ALE56P13_357VSS58P13_259VCC260P13_161P13_062CLKOUT P5_3BCLK/ALE63P5_2RD64P5_1WRH/BHE65P5_0WRL/WR66P12_767P12_668P12_569P4_7CS0/A2370P4_6CS1/A2271P4_5CS2/A2172P4_4CS3/A2073P4_3A1974VCC275P4_2A1876VSS77P4_1A1778P4_0A1679P3_7A15,[A15/D15]80P3_6A14,[A14/D14]81P3_5A13,[A13/D13]82P3_4A12,[A12/D12]83P3_3A11,[A11/D11]84P3_2A10,[A10/D10]85P3_1A9,[A9/D9]86P12_487P12_388P12_289P12_190P12_091VCC292P3_0A8,[A8/D8]93VSS94P2_7A7,[A7/D7]95P2_6A6,[A6/D6]96P2_5A5,[A5/D5]97P2_4A4,[A4/D4]98P2_3A3,[A3/D3]99P2_2A2,[A2/D2]100P2_1A1,[A1/D1]Table 1.8144-Pin Version List of Pin Names (3)PinControl Pin Port Interrupt Pin Timer Pin UART Pin Analog Pin Bus Control Pin No.101P2_0A0,[A0/D0]102P1_7INT5D15103P1_6INT4D14104P1_5INT3D13105P1_4D12106P1_3D11107P1_2D10108P1_1D9109P1_0D8110P0_7D7111P0_6D6112P0_5D5113P0_4D4114P11_4115P11_3116P11_2117P11_1118P11_0119P0_3D3120P0_2D2121P0_1D1122P0_0D0123P15_7AN15_7124P15_6AN15_6125P15_5AN15_5126P15_4AN15_4127P15_3AN15_3128P15_2AN15_2129P15_1AN15_1130VSS131P15_0AN15_0132VCC1133P10_7KI3AN_7134P10_6KI2AN_6135P10_5KI1AN_5136P10_4KI0AN_4137P10_3AN_3138P10_2AN_2139P10_1AN_1140AVSS141P10_0AN_0142VREF143AVCC144P9_7RXD4/SCL4/STXD4ADTRGPinControl Pin Port Interrupt Pin Timer Pin UART Pin Analog Pin Bus Control Pin No.1P9_4TB4IN CTS4/RTS4/SS4DA12P9_3TB3IN CTS3/RTS3/SS3DA03P9_2TB2IN TXD3/SDA3/SRXD34P9_1TB1IN RXD3/SCL3/STXD35P9_0TB0IN CLK36BYTE7CNVSS8XCIN P8_79XCOUT P8_610RESET11XOUT12VSS13XIN14VCC115P8_5NMI16P8_4INT217P8_3INT118P8_2INT019P8_1TA4IN/U20P8_0TA4OUT/U21P7_7TA3IN22P7_6TA3OUT23P7_5TA2IN/W24P7_4TA2OUT/W25P7_3TA1IN/V CTS2/RTS2/SS226P7_2TA1OUT/V CLK227P7_1TA0IN/TB5IN RXD2/SCL2/STXD228P7_0TA0OUT TXD2/SDA2/SRXD229P6_7TXD1/SDA1/SRXD130P6_6RXD1/SCL1/STXD131P6_5CLK132P6_4CTS1/RTS1/SS133P6_3TXD0/SDA0/SRXD034P6_2RXD0/SCL0/STXD035P6_1CLK036P6_0CTS0/RTS0/SS037P5_7RDY38P5_6ALE39P5_5HOLD40P5_4HLDA/ALE41CLKOUT P5_3BCLK/ALE42P5_2RD43P5_1WRH/BHE44P5_0WRL/WR45P4_7CS0/A2346P4_6CS1/A2247P4_5CS2/A2148P4_4CS3/A2049P4_3A1950P4_2A18PinControl Pin Port Interrupt Pin Timer Pin UART Pin Analog Pin Bus Control Pin No.51P4_1A1752P4_0A1653P3_7A15,[A15/D15]54P3_6A14,[A14/D14]55P3_5A13,[A13/D13]56P3_4A12,[A12/D12]57P3_3A11,[A11/D11]58P3_2A10,[A10/D10]59P3_1A9,[A9/D9]60VCC261P3_0A8,[A8/D8]62VSS63P2_7A7,[A7/D7]64P2_6A6,[A6/D6]65P2_5A5,[A5/D5]66P2_4A4,[A4/D4]67P2_3A3,[A3/D3]68P2_2A2,[A2/D2]69P2_1A1,[A1/D1]70P2_0A0,[A0/D0]71P1_7INT5D1572P1_6INT4D1473P1_5INT3D1374P1_4D1275P1_3D1176P1_2D1077P1_1D978P1_0D879P0_7D780P0_6D681P0_5D582P0_4D483P0_3D384P0_2D285P0_1D186P0_0D087P10_7KI3AN_788P10_6KI2AN_689P10_5KI1AN_590P10_4KI0AN_491P10_3AN_392P10_2AN_293P10_1AN_194AVSS95P10_0AN_096VREF97AVCC98P9_7RXD4/SCL4/STXD4ADTRG99P9_6TXD4/SDA4/SRXD4ANEX1100P9_5CLK4ANEX01.5Pin FunctionsTable 1.11Pin Functions (1) (100-Pin Package and 144-Pin Package)Item Pin NameI/OTypeSupplyVoltageDescriptionPower supply VCC1,VCC2VSS −−Apply 3.0 to 5.5 V to pins VCC1 and VCC2, and 0 V to the VSS pin.The input condition of VCC1 ≥ VCC2 must be met.Analog power supply input AVCCAVSS−VCC1Power supply input pins to the A/D converter and D/A converter.Connect the AVCC pin to VCC1, and the AVSS pin to VSS.Reset input RESET I VCC1The MCU is placed in a reset state when applying an “L” signal tothe RESET pin.CNVSS CNVSS I VCC1This pin switches processor mode. Apply an “H” signal to theCNVSS pin to start up in microprocessor mode.External data bus width select input BYTE I VCC1This pin switches data bus width in external memory space 3. Adata bus is 16 bits wide when the BYTE pin is held “L” and 8 bitswide when it is held “H”.Bus control Pins D0 to D7I/O VCC2Data (D0 to D7) input/output pins while accessing an externalmemory space with separate bus.D8 to D15I/O VCC2Data (D8 to D15) inputs/output pins while accessing an externalmemory space with 16-bit separate bus.A0 to A22O VCC2Address bits (A0 to A22) output pins.A23O VCC2Inverted address bit (A23) output pin.A0/D0 toA7/D7I/O VCC2Data (D0 to D7) input/output and 8 low-order address bits (A0 toA7) output are performed by time-sharing these pins whileaccessing an external memory space with multiplexed bus.A8/D8 toA15/D15I/O VCC2Data (D8 to D15) input/output and 8 middle-order address bits (A8to A15) output are performed by time-sharing these pins whileaccessing an external memory space with 16-bit multiplexed bus. CS0 to CS3O VCC2Chip-select signal output pins used to specify external devices. WRL/WRWRH/BHERDO VCC2WRL, WRH, (WR, BHE) and RD signal output pins. WRL and WRHcan be switched with WR and BHE by program.•WRL, WRH and RD are selected:If external data bus is 16 bits wide, data is written to an evenaddress in external memory space while an “L” is output from theWRL pin. Data is written to an odd address while an “L” is outputfrom the WRH pin.Data is read while an “L” is output from the RD pin.•WR, BHE and RD are selected:Data is written while an “L” is output from the WR pin.Data is read while an “L” is output from the RD pin.Data in odd address is accessed while an “L” is output from theBHE pin. Select WR, BHE and RD when an external data bus is8 bits wide.ALE O VCC2ALE signal is used for the external devices to latch address signalswhen the multiplexed bus is selected.HOLD I VCC2The MCU is placed in a hold state while an “L” signal is applied tothe HOLD pin.HLDA O VCC2The HLDA pin outputs an “L” while the MCU is placed in a holdstateRDY I VCC2Bus is placed in a wait state while an “L” signal is applied to theRDY pin.Item Pin NameI/OTypeSupplyVoltageDescriptionMain clock input XIN I VCC1Input/output pins for the main clock oscillation circuit. Connect aceramic resonator or crystal oscillator between XIN and XOUT. Toapply an external clock, apply it to XIN and leave XOUT openMain clockoutputXOUT O VCC1Sub clock input XCIN I VCC1Input/output pins for the sub clock oscillation circuit. Connect acrystal oscillator between XCIN and XCOUT. To apply an externalclock, apply it to XCIN and leave XCOUT open.Sub clockoutputXCOUT O VCC1BCLK output BCLK O VCC2Bus clock output pinClock output CLKOUT O VCC2The CLKOUT pin outputs the clock having the same frequency asfC, f8, or f32INT interrupt input INT0 to INT2I VCC1INT interrupt input pins NT3 to INT5I VCC2NMI interrupt input NMI I VCC1NMI interrupt input pin. Connect the NMI pin to VCC1 via a resistorwhen the NMI interrupt is not used.Timer A TA0OUT toTA4OUT I/O VCC1Timer A0 to A4 input/output pins(TA0OUT is N-channel open drain output)TA0IN toTA4INI VCC1Timer A0 to A4 input pinsTimer B TB0IN toTB5INI VCC1Timer B0 to B5 input pinsThree-phase motor control timer output U, U, V, V,W, WO VCC1Three-phase motor control timer output pinsSerial interface CTS0 toCTS4I VCC1Input pins to control data transmissionRTS0 toRTS4O VCC1Output pins to control data receptionCLK0 to CLK4I/O VCC1Serial clock input/output pinsRXD0 toRXD4I VCC1Serial data input pinsTXD0 toTXD4O VCC1Serial data output pins(TXD2 is N-channel open drain output)I2C mode SDA0 toSDA4I/O VCC1Serial data input/output pins(SDA2 is N-channel open drain output)SCL0 to SCL4I/O VCC1Serial clock input/output pins(SCL2 is N-channel open drain output)Serial interface special function STXD0 toSTXD4O VCC1Serial data output pins when slave mode is selected(STXD2 is N-channel open drain output)SRXD0 toSRXD4I VCC1Serial data input pins when slave mode is selectedSS0 to SS4I VCC1Control input pins used in the serial interface special mode.NOTE:1.P0 to P5 function as bus control pins and cannot be used as I/O ports. P1_0 to P1_7 can be used as I/O portswhen using with 8-bit external bus width only.Table 1.14Pin Functions (4) (144-Pin Package Only)Item Pin Name I/O Type Supply Voltage DescriptionReference voltage input VREF I −The VREF pin supplies the reference voltage to the A/D converter and D/A converter.A/D converterAN_0 to AN_7I VCC1Analog input pins for the A/D converter.ADTRG I VCC1External trigger input pin for the A/D converter.ANEX0I/OVCC1Extended analog input pin for the A/D converter or output pin in external op-amp connection mode.ANEX1I VCC1Extended analog input pin for the A/D converter.D/A converter DA0, DA1O VCC1Output pins for the D/A converter.I/O portP0_0 to P0_7,P1_0 to P1_7,P2_0 to P2_7,P3_0 to P3_7,P4_0 to P4_7,P5_0 to P5_7I/O (1)VCC28-bit CMOS I/O ports. The Port Pi Direction Register determines if each pin is used as an input port or an output port. The Pull-up Control Register determines if the input ports, divided into groups of four, are pulled up or not.P6_0 to P6_7,P7_0 to P7_7,P9_0 to P9_7,P10_0 to P10_7I/O VCC1These 8-bit I/O ports are functionally equivalent to P0.(P7_0 and P7_1 are N-channel open drain output.)P8_0 to P8_4P8_6, P8_7These I/O ports are functionally equivalent to P0.Input port P8_5I VCC1Shares the pin with NMI. Input port to read NMI pin level.Key input interrupt inputKI0 to KI3IVCC1Key input interrupt input pinsItem Pin Name I/O Type SupplyVoltage DescriptionA/D converter AN15_0 to AN15_7I VCC1Analog input pins for the A/D converter I/O portsP11_0 to P11_4,P12_0 to P12_7,P13_0 to P13_7 I/OVCC2These I/O ports are functionally equivalent to P0.P14_0 to P14_6, P15_0 to P15_7I/O VCC12.Central Processing Unit (CPU)Figure 2.1 shows the CPU registers.The register bank is comprised of eight registers (R0, R1, R2, R3, A0, A1, SB, and FB) out of 28 CPU registers. There are two sets of register banks.Figure 2.1CPU Register2.1General Registers2.1.1Data Registers (R0, R1, R2, and R3)R0, R1, R2, and R3 are 16-bit registers for transfer, arithmetic and logic operations. R0 and R1 can be split into high-order (R0H/R1H) and low-order bits (R0L/R1L) to be used separately as 8-bit data registers.R0 can be combined with R2 and used as a 32-bit data register (R2R0). The same applies to R3R1.2.1.2Address Registers (A0 and A1)A0 and A1 are 24-bit registers used for A0-/A1-indirect addressing, A0-/A1-relative addressing, transfer, arithmetic and logic operations.2.1.3Static Base Register (SB)SB is a 24-bit register used for SB-relative addressing.2.1.4Frame Base Register (FB)FB is a 24-bit register used for FB-relative addressing.2.1.5User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)The stack pointers (SP), USP and ISP, are 24 bits wide each. The U flag is used to switch between USP and ISP.Refer to 2.1.8 Flag Register (FLG) for details on the U flag. Set USP and ISP to even addresses to execute an interrupt sequence efficiently.2.1.6Interrupt Table Register (INTB)INTB is a 24-bit register indicating the starting address of a relocatable interrupt vector table.2.1.7Program Counter (PC)PC is 24 bits wide and indicates the address of the next instruction to be executed.2.1.8Flag Register (FLG)FLG is a 16-bit register indicating the CPU state.2.1.8.1Carry Flag (C)The C flag indicates whether or not carry or borrow has been generated after executing an instruction.2.1.8.2Debug Flag (D)The D flag is for debugging only. Set it to 0.2.1.8.3Zero Flag (Z)The Z flag becomes 1 when an arithmetic operation results in 0; otherwise becomes 0.2.1.8.4Sign Flag (S)The S flag becomes 1 when an arithmetic operation results in a negative value; otherwise becomes 0.2.1.8.5Register Bank Select Flag (B)Register bank 0 is selected when the B flag is set to 0. Register bank 1 is selected when this flag is set to 1.2.1.8.6Overflow Flag (O)The O flag becomes 1 when an arithmetic operation results in an overflow; otherwise becomes 0.2.1.8.7Interrupt Enable Flag (I)The I flag enables maskable interrupts.Interrupts are disabled when the I flag is set to 0 and enabled when it is set to 1. The I flag becomes 0 when an interrupt request is acknowledged.2.1.8.8Stack Pointer Select Flag (U)ISP is selected when the U flag is set to 0. USP is selected when the U flag is set to 1.The U flag becomes 0 when a hardware interrupt request is acknowledged or the INT instruction specifying software interrupt numbers 0 to 31 is executed.2.1.8.9Processor Interrupt Priority Level (IPL)IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.If a requested interrupt has higher priority than IPL, the interrupt is enabled.2.1.8.10Reserved SpaceOnly write 0 to bits assigned to the reserved space. When read, the bits return undefined values.2.2High-Speed Interrupt RegistersRegisters associated with the high-speed interrupt are follows:•Save flag register (SVF)•Save PC register (SVP)•Vector register (VCT)2.3DMAC-Associated RegistersRegisters associated with the DMAC are as follows:•DMA mode register (DMD0, DMD1)•DMA transfer count register (DCT0, DCT1)•DMA transfer count reload register (DRC0, DRC1)•DMA memory address register (DMA0, DMA1)•DMA memory address reload register (DRA0, DRA1)•DMA SFR address register (DSA0, DSA1)3.MemoryFigure 3.1 is a memory map of the M32C/8A Group.The M32C/8A Group has 16-Mbyte address space from addresses 000000h to FFFFFFh.The fixed interrupt vectors are allocated addresses FFFFDCh to FFFFFFh. They store the starting address of each interrupt routine.The internal RAM is allocated higher addresses, beginning with address 000400h. For example, a 12-Kbyte internal RAM area is allocated addresses 000400h to 0033FFh. The internal RAM is used not only for storing data but for the stacks when subroutines are called or when interrupt requests are acknowledged.SFRs are allocated address 000000h to 0003FFh. The peripheral function control registers such as for I/O ports, A/D converters, serial interfaces, timers are allocated here. All blank spaces within SFRs are reserved and cannot be accessed by users.The special page vectors are allocated addresses FFFE00h to FFFFDBh. They are used for the JMPS instruction and JSRS instruction. Refer to the Renesas publication M32C/80 Series Software Manual for details.4.Special Function Registers (SFRs)Special Function Registers (SFRs) are the control registers of peripheral functions. Tables 4.1 to 4.11 list SFR address maps.Table 4.1SFR Address Map (1)X: UndefinedBlank spaces are all reserved. No access is allowed.NOTE:1.Bits PM01 and PM00 in the PM0 register maintain values set before reset, even after software reset or watchdog timer reset has beenperformed.Address RegisterSymbolAfter Reset0000h 0001h 0002h 0003h 0004h Processor Mode Register 0(1)PM00000 0011b(CNVSS=”H”)0005h Processor Mode Register 1PM100h 0006h System Clock Control Register 0CM00000 1000b 0007h System Clock Control Register 1CM10010 0000b0008h 0009h Address Match Interrupt Enable Register AIER 00h000Ah Protect RegisterPRCR XXXX 0000b000Bh External Data Bus Width Control Register DS XXXX 1000b(BYTE=”L”)XXXX 0000b(BYTE=”H”)000Ch Main Clock Division Register MCD XXX0 1000b 000Dh Oscillation Stop Detection Register CM200h 000Eh Watchdog Timer Start Register WDTS XXh000Fh Watchdog Timer Control RegisterWDC00XX XXXXb0010h Address Match Interrupt Register 0RMAD0000000h0011h 0012h 0013h Processor Mode Register 2PM200h0014h Address Match Interrupt Register 1RMAD1000000h0015h 0016h 0017h Voltage Detection Register 2VCR200h0018h Address Match Interrupt Register 2RMAD2000000h0019h 001Ah 001Bh Voltage Detection Register 1VCR10000 1000b001Ch Address Match Interrupt Register 3RMAD3000000h001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h PLL Control Register 0PLC00001 X010b 0027h PLL Control Register 1PLC1000X 0000b0028h Address Match Interrupt Register 4RMAD4000000h0029h 002Ah 002Bh 002Ch Address Match Interrupt Register 5RMAD5000000h002Dh 002Eh 002FhVdet4 Detection Interrupt RegisterD4INTXX00 0000bX: UndefinedBlank spaces are all reserved. No access is allowed.Address RegisterSymbolAfter Reset0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h Address Match Interrupt Register 6RMAD6000000h0039h 003Ah 003Bh 003Ch Address Match Interrupt Register 7RMAD7000000h003Dh 003Eh 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h External Space Wait Control Register 0EWCR0X0X0 0011b 0049h External Space Wait Control Register 1EWCR1X0X0 0011b 004Ah External Space Wait Control Register 2EWCR2X0X0 0011b 004Bh External Space Wait Control Register 3EWCR3X0X0 0011b 004Ch Page Mode Wait Control Register 0PWCR00001 0001b 004Dh Page Mode Wait Control Register 1PWCR10001 0001b004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh。