1.Research OverviewThe1999International Technology Roadmap for Semiconductors(ITRS99)projects at-speed testing and delayfault diagnosis as increasingly difficult problems.LBIST fault coverage requirements are projected to rise to98%in2004and99%in2005with no known solutions.Delay fault diagnosis is increasingly important,but failure analysisfor delay faults is considered a difficult challenge.In this research we propose to address these problems withresearch on delay fault modeling,fault simulation,ATPG and diagnosis,targeting full/mostly-scan logic designsimplemented in static and dynamic CMOS circuits.Previous work on delay fault testing has used abstract models such as the transition or path delay fault.Thesemodels do not completely describe real delay fault behaviors,and so result in incomplete fault coverage and poordiagnostic accuracy.They do not account for pattern-sensitive delay due to capacitive coupling or resistive bridges,nor do they take advantage of the spatially correlated nature of process parameter variation.The latter means that thepath delay fault model is very pessimistic and thus difficult to use.In this research we propose to use physically realistic yet economical fault models to improve at-speed test coverage and delay fault diagnostic accuracy.The set of faults we consider is shown in Figure1.Local delay faults are increases in logic stage delay causedby a spot defect that causes a fault such as a resistive bridge or open.Global delay faults are slow paths due toprocess parameter variation such as ILD thickness bined delay faults are caused by both of theseeffects acting together.In all three cases,capacitive crosstalk must be taken into account.We propose to developphysically realistic models for local,global,and combined delay faults and apply them in fault simulation,ATPGand diagnosis algorithms.Specifically we will consider process variation,spatial process correlation,capacitivecoupling,resistive bridges,and resistive opens.This research is novel in that no other research combines theseeffects.Our delay fault tests will also screen for some functional failures and reliability hazards.Our work onmodeling process variability is also applicable to DFM including statistical timing and signal integrity analysis.Proposed ResearchFigure1.Fault types addressed in this research.Figure2shows an example of a test generation problem for a combined delay fault.A resistive via is present onB.The capacitances shown are between neighboring lines on the specified metal layer,and vary with line width andthickness on that layer.The logic stage delays also vary with process parameters,such as polysilicon linewidth.The test generation problem is to ensure that paths A-B-C-D and A-B-C-E have delay<T max for all input transitions, process parameter values,and via resistance.Since the side inputs on the paths are stable,the paths are robustlytestable.A transition fault model would select one of A-B-C-D or A-B-C-E and propagate both rising and fallingtransitions along it.But large delay faults may escape these tests.In the transition fault model F is a Don’t Care.If itis assigned the same transition as A,then the G-B capacitance could cause G2to switch with little or no increaseddelay even for large via resistance[Moore00].This could happen even though the G-B capacitance is much smallerthan the total B capacitance if the via resistance shields most of the B capacitance from G2and the G-B capacitor.The same situation is true for the H input.Transition fault tests are not guaranteed to select the longest path,so smalldelay faults due to a moderate via resistance may also escape.The path delay fault model would avoid this problemby generating tests for both paths.However it does not consider coupling and so does not guarantee that F and H aresensitized to maximize the path delay.Even if a test generator is aware of capacitance,it still could not set F and H without additional information.Depending on the values of the G-B and G-C capacitors and the G5logic stage delay,a rising or falling transition onF may maximize the path delay.Since the G6stage delay also varies,H could be a Don’t Care or require theopposite transition of A.This parameter uncertainty means that even generating all combinations does not ensure100%delay fault coverage.The paths would be classified as possible detects.By using process sensitivity and process parameter correlation information,we can generate better tests with amore accurate coverage metric.In this example all the M4capacitors are adjacent and their values are highlycorrelated.The delays of logic stages G3and G4are highly correlated,and the parameters of gates G1,G2and G5are highly correlated.Paths A-B-C-D and A-B-C-E are structurally correlated[Luong96]in that they share the A-B-C segment.This combination of structural and spatial correlation means that if A-B-C-D is tested,then it is not necessary to test A-B-C-E.This also assumes C is an equipotential.In[Luong96]we showed that only a small amount of correlation could drastically reduce the number of paths that must be tested.The G-B and G-C capacitors track one another,so the F transition to maximize the A-B-C-D delay can be determined.We will assume it is the opposite of the A transition.Since G5and G1track one another,the G and B transitions are aligned except for the I-B crosstalk and via resistance.The via resistance can cause the B transition to come after the G transition.But due to the increasing time constant on B with increasing via resistance,the alignment window widens,and the opposing G transition is still the desired one over the entire process range.In this example the G6logic stage delay is not correlated with the other logic stages so the I transition does not track a B transition.In this example we will also assume that the latest I transition occurs well before the earliest B transition.As with F,the H transition should be the opposite of A.In summary,our more physically realistic model would test only the A-B-C-D path with patterns: (A↑,F↓,H↓)and(A↓,F↑,H↑)to ensure100%coverage of paths A-B-C-D and A-B-C-E with a resistive via at B.FD AE <Tmax?Figure2.Example of delay fault test problem.2.PI and Co-PI Previous Related WorkIn prior work we have considered local and global delay faults,but separately and incompletely.We developed a method for quickly identifying the K longest dynamically sensitizable paths under process variation,including ISCAS85circuit C6288[Bell96].In general long paths are sometimes sensitizable in that a given path is only sensitizable over a subset of the process parameters.We developed gate delay models that were a function of the seven most significant process parameters and combined these with our path search method to generate small test sets for global delay faults[Luong96].But this work did not consider interconnect variation or coupling and its nonlinear optimization algorithm was expensive.We have performed statistical timing analysis including sensitizing the worst-case path delays under coupling and process variation[Choi00].However to reduce complexity we used a simple switch factor model and did not consider process variation or mutual coupling on the side paths.Our prior work on local delay faults targeted resistive bridges that can cause local delay faults and VLV testing for them[Liao96a][Liao96b].Most of our work on resistive bridges focused on fault simulation and ATPG for functional failures[Sar-Dessai98][Sar-Dessai99][Lee00].We have recently developed new implementations that are efficient enough to apply to industrial circuits.Our prior work in performance prediction used a variety of transistors and ring oscillators.By estimating the local process gradient,we achieved80%correlation between predicted and measured FMAX values in an AMD K6 microprocessor[Lee99].This was sufficient to correctly predict the speed bin of most chips.Higher correlation could have been achieved by using ring oscillators that were more sensitive to interconnect variation.Even higher correlation can be achieved by measuring flush delays in LSSD scan chains[Huisman98].Our prior work in diagnosis focused on localization of shorts and opens[Stanojevic00].By combining stuck-at diagnosis and layout information we have produced search areas in the range of tens of square microns on industrial circuits.The FedEx fault extractor developed in this work can quickly generate realistic bridging fault lists for use in test generation as well as diagnosis.Our work in design error diagnosis and correction can also be extended to fault diagnosis[Nayak99].Our performance prediction work also provided some diagnostic results in that local delay faults were identified by significant differences between predicted and actual FMAX measurements.One fault modeling challenge is quickly and accurately estimating the sensitivity of coupling capacitances to process variation and their impact on circuit delay.We have developed a capacitance extractor that is100x faster than FastCap,and so can be used to compute process sensitivity of common interconnect configurations[Shi98]. 3.Research PlanThere are four parts to the proposed research:delay fault models,fault simulation,ATPG,and fault diagnosis, described in the following sections.We have formed two tasks to cover the research plan.Task1“Realistic Delay Fault Modeling”focuses on the work described in Section3.1.Task2“Realistic Delay Fault Simulation,Test Generation,and Diagnosis”uses the models developed in Task1in the applications described in Sections3.2-3.4.In order to create a realistic delay fault model for fault simulation and testing at both regular and VLV voltages, we must develop a simple model that captures process variation,via/contact resistance variation,coupling capacitance,and bridging resistance.The key to the simple model is a new model dimension reduction algorithm that reduces the number of variations of a given circuit,without losing any variation corners of the circuit.We will also develop algorithms and tools for delay estimation under process variation and local defects,and develop algorithms and tools for parameterized static timing analysis that quickly finds critical or near critical paths where process variation and spot defects may cause delay faults.The timing analysis does not consider path sensitization, which is left for the path generator described in Sections3.2and3.3.We will consider process variations of both interconnect(such as metal width,metal thickness,ILD thickness and via resistance)and device(such as gate length,gate oxide thickness,and doping density).We will also include coupling capacitance,bridging resistance,and spatial process parameter correlation into the model.From our experience in industry and previous research[Bell96][Luong96][Choi00],process variation can cause10% variation in signal delay.For sub-180nm technology,interconnect variation will dominate but device variation will still be important.Figure3shows the impact of process variation on parasitic capacitance in a DSM technology,for realistic ranges of process variation.Via resistance for a mature technology has a small tail,but out of every half million or million vias there could be one with large resistance.-30-20-100102030Process Variation(%)Figure3.Impact of Process Variation on Interconnect CapacitanceWe will build delay models for static and dynamic CMOS circuits as follows.We will design algorithms and tools to extract interconnect parasitic with variations.Our algorithms will be built on top of commercial layout parasitic extraction tools,with which we have extensive working experience.Model order reduction is performed on the parasitics[Liu99]and variational gate delay models are built[Cao99].These techniques permit fast delay estimation without SPICE simulation.Crosstalk,via resistance and bridging resistance can be included in a similar way.A useful tool for studying device variation is Circuit Surfer[Circuit98].Once the delay can be estimated between buffers,we want to quickly find the critical paths where delay faults may occur.This will be done by a static timing analysis tool that takes the buffer-to-buffer delay as intervals(not independent intervals,though)and performs quick screening.Now we explain the idea of model dimension reduction.Consider an RC circuit representing the parasitics of an interconnect,where the value of each resistor and capacitor may vary with the process variation and local defects. We call the number of variables the dimension of the model.In the traditional approach,the dimension equals the number of variables,which is often the sum of the number of process parameters and the number of via/contacts.As a result,fault simulation and test generation have to deal with complicated circuits and the optimization problems they must solve are very expensive.When coupling capacitance and bridging resistance are included,the model is even more complicated.We will show that it is possible to use a simple model with very few variables to capture all behavior corners of the original RC circuit.For example,it can be shown that a ladder of distributed RCs,each a variable,can be approximated by a pi model of2variable capacitors and1variable resistor,without losing any corner.We will develop algorithms to perform dimension reduction for arbitrary RC(L)circuits.The ITRS99projects increasing use of at-speed LBIST.Therefore we expect delay fault ATPG to be used as a cleanup phase.This requires delay fault simulation to drop detected faults prior to ATPG.Fault sites consist of local delay increases at gate inputs,outputs,or fan-outs,and the sensitizable paths through these points.During fault simulation,each test vector constrains the local delay and process parameter values to be in the range that they do not cause one of the sensitized paths to violate timing.A fault site can be dropped if all the untested paths in the fault site are constrained to meet their timing specification.Fault simulation proceeds by considering each fault site one at a time and applying the test vectors.The potentially sensitized paths in the fault site are identified using a min-max gate delay model,computed using the analytical timing models assuming uncorrelated best/worst process,input slope,and coupled transitions.For each path an analytical timing model is then ing timing sensitivity information and a FAN algorithm[Choi 00]we identify the side paths and their sensitizations that could generate aligned coupled transitions causing the largest delay increase on the path.The spatial process parameter correlation model and the path timing specification form constraints on path process parameters and the local delay increase.Sometimes sensitizable paths also have constraints on the range of process parameters,for which they are sensitizable,since they provide no information when they do not propagate.We remember the longest tested paths in one fault site since they are likely the longest paths in all fault sites containing them.Paths and their constraints are collected until one close to the longest structural length is sensitized,and then the longest sensitizable path under the constraints is determined using the timing models and a path generator that is a modified version of[Bell96].The generator must be modified to include existing variable assignments,the existence of a local delay fault,and the restriction that the path pass through the local delay fault.Since the timing models and constraints are linear,the analysis is very fast.If this path meets the timing specification,the fault site is dropped.Otherwise the next vector is considered.We wait until a long path is sensitized since testing short paths in the fault site is unlikely to drop the fault.For faults that are not dropped during fault simulation,the path models and constraints are retained for input to ATPG.Due to random local process variation,alignment of coupled transitions is uncertain.Fault sites that are detected for only some of the uncertainty interval are potential detects,and so are not dropped,since a test may exist that guarantees detection.Since coupled paths tend to be nearby,the random local variability and thus the number of potential detect cases should be small.In VLV testing the allowable maximum path delay during fault simulation will be relaxed since the tests will typically be applied at scan speeds.However we must still estimate which paths tested at lower speed fail to meet their normal voltage timing ing the path generator with VLV-generated constraints and normal-voltage delay models can do this.Escapes can then be targeted for at-speed test.Conversely the VLV test speed must be determined that does not cause ing VLV delay models and the path generator with normal voltage constraints can do this.3.3.Automatic Test Pattern GenerationIn ATPG we consider each fault site that was not dropped by fault simulation.We use the path generator to enumerate the K longest paths in the fault site and their necessary input assignments that could exceed their timing specification while meeting the constraints.As in fault simulation,we use timing model sensitivity information anda FAN algorithm to assign the remaining inputs so that the coupled transitions maximize the path delay.As in[Choi00],the search process must avoid local minima.In this search we do not consider input vector constraints such as a skewed load delay test.To handle the random local process variation mentioned in Section3.2,we attempt to maximize the probability of transition alignment.The tested path generates additional constraints for the remaining untested paths in the fault site.The test generation process is repeated until the fault site can be dropped.The incremental nature of the path generator reduces the cost of this iteration.By starting with the longest path first,we put the tightest constraints on later paths,permitting the fault site to be dropped earlier[Luong96].As with fault simulation,it may be beneficial to retain the constraints from one fault site when considering another nearby one,to take advantage of spatial correlation.If the local delay fault is caused by a resistive bridge,there are also constraints on the resistively coupled node. To maximize the delay on the bridged logic stage,it should transition to the opposing value prior to the on-path transition.However this assignment may preclude a coupled transition causing an even larger delay for some resistance values.To avoid this,the bridged node is first treated as a necessary assignment,and then considered a form of coupling and included in the FAN algorithm for coupled transitions.For some low-resistance bridges,the on-path value will dominate and determine the value propagated on the bridged path.Based on the results in[Luong96][Huisman98],we believe that only a small number of paths must be tested in each fault site,so the total number of paths that must be considered will be approximately linear in circuit size.Considering constraints from one fault site to the next may substantially reduce the number of tests,since the longest path in a given fault site is likely to be the longest path in all fault sites that contain it.One issue in VLV testing is that different paths may have different delay voltage sensitivities.As a result,the best vectors for VLV and normal voltage testing may be different.We will investigate whether this is a significant effect,and whether it can be readily detected during ATPG so that both vectors can be generated in those cases. 3.4.Delay Fault DiagnosisSimilar to spot defect diagnosis today,we assume that the input to the delay fault diagnosis is a set of passing and failing at-speed test vectors captured after the first failing vector.Capture of such vectors is readily automated so that a sampling scheme or dynamic tester decision can be made in order to use the diagnostic results as a form of process monitoring.For each passing and failing vector we can use the fault simulation engine to build the set of sensitizable paths and their constraints.Sensitizable paths feeding an incorrect value have the constraint that at least one of them is too slow.The combination of delay models and constraints allows us to determine the set of process parameters and local delay faults that could explain the behavior.These locations can then be examined with a SEM. Thus this is a cause-effect approach.The drawback is that when the faulty behavior is not one of the modeled behaviors,the diagnostic results are poor.An alternative is to use an effect-cause analysis similar to[Nayak99].Instead of making assumptions about process parameters,simple min-max delay models and local delay increases can be used,and their values constrained by the vector results.The level of suspicion on each fault site and paths within the site would be based on how many faulty vectors they could explain.The set of fault sites could then be reduced using our delay models.4.Relationship to Other SRC-Funded ResearchWe can take advantage of prior SRC work on delay fault modeling and transition alignment[Chen97][Chen 98][Chen99][Lee98][Liu99].[Chen99]considered delay variation due to coupling,but only at a single fault site and without process variation or correlation.We can evaluate test sets generated using surrogate approaches [Pomeranz99]to determine their realistic delay fault coverage.Previous SRC realistic delay fault diagnosis work [Sivaraman98]did not consider coupling or combined delay faults.We would investigate whether the work of [Krstic99]on power supply variation can be incorporated into our models.References[Bell96]J.Bell,“Timing Analysis of Logic-Level Digital Circuits Using Uncertainty Intervals”,M.S.Thesis,Dept.of Computer Science,Texas A&M University,1996.[Cao99]M.Cao,Y.Liu and A.Strojwas,SRC Technical Report,1999.[Chen97]W.Chen,S.Gupta and M.Breuer,“Analytic models for crosstalk delay and pulse analysis under non-ideal inputs”,ITC,1997. [Chen98]W.Chen,S.Gupta and M.Breuer,“Test Generation in VLSI Circuits for Crosstalk Noise”,ITC,1998.[Chen99]W.Chen,S.Gupta,and M.Breuer,“Test Generation for Crosstalk-Induced Delay in Integrated Circuits”,ITC99.[Choi00] B.Choi and D.Walker,“Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation”,VTS,2000.[Circuit98]Circuit Surfer User's Manual,PDF Solutions,Inc.,San Jose CA,1998.[Huisman98]L.Huisman,“Correlations Between Path Delays and the Accuracy of Performance Prediction”,ITC,1998.[Krstic99] A.Krstic,Y.Jiang,and K.Cheng,“Delay Testing Considering Power Supply Noise Effects”,ITC,1999.[Lee98]K.Lee,C.Nordquist,J.Abraham,“Automatic Test Pattern Generation for Crosstalk Glitches in Digital Circuits”,VTS,1998. [Lee99]J.Lee,D.Walker,or,Y.Peng,and G.Hill,“IC Performance Prediction for Test Cost Reduction”,ISSM99.[Lee00] C.Lee and D.Walker,“PROBE:A PPSFP Simulator for Resistive Bridging Faults”,VTS,2000.[Liao96a]Y.Liao and D.Walker,“Optimal Voltage Testing for Physically-Based Faults”,VTS,1996.[Liao96b]Y.Liao and D.Walker,“Fault Coverage Analysis of Physically-Based Bridging Faults at Different Power Supply Voltages”, ITC,1996.[Liu99]Y.Liu,L.Pileggi and A.Strojwas,“Model Order-Reduction of RCL Interconnect Including Variational Analysis”,DAC,1999. [Luong96]G.Luong,and D.Walker,“Test Generation for Global Delay Faults”,ITC,1996,pp.433-442.[Moore00]W.Moore,G.Gronthoud,K.Baker and M.Lousberg,“Delay-Fault Testing and Defects in Sub-Micron ICs–Does Critical Resistance Really Mean Anything?”,ITC,2000.[Nayak99] D.Nayak and D.Walker,“Simulation-Based Design Error Diagnosis and Correction in Combinational Circuits”,VTS,1999. [Pomeranz99]I.Pomeranz and S.Reddy,“On Achieving Complete Coverage of Delay Faults in Full Scan Circuits using Locally Available Lines”,ITC,1999.[Sar-Dessai98]V.Sar-Dessai and D.Walker,“Accurate Fault Modeling and Fault Simulation of Resistive Bridges”,DFTS,1998.[Sar-Dessai99]V.Sar-Dessai,and D.Walker,“Resistive Bridge Fault Modeling,Simulation,and Test Generation”,ITC,1999. [Sivaraman98]M.Sivaraman and A.Strojwas,A Unified Approach for Timing Verification and Delay Fault Testing,Kluwer,1998.[Shi98]W.Shi,J.Liu,N.Kakani and T.Yu,“A Fast Hierarchical Algorithm for3-D Capacitance Extraction”,DAC,1998. [Stanojevic00]Z.Stanojevic,H.Balachandran,D.Walker,khani,S.Jandhyala,J.Saxena and K.Butler,“Computer-Aided Fault to Defect Mapping(CAFDM)for Defect Diagnosis”,ITC,2000.Faculty Web Site and Papers:/faculty/walker/cadt00_06_22.html。
