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Stratix II GX Device Handbook, Volume 1Modes of Operation

The adder, subtractor, and accumulate functions of a DSP block have four modes of operation:

■Simple multiplier

■Multiply-accumulator

■Two-multipliers adder

■Four-multipliers adder

Table2–22 shows the different number of multipliers possible in each DSP block mode according to size. These modes allow the DSP blocks to implement numerous applications for DSP including FFTs, complex FIR, FIR, 2D FIR filters, equalizers, IIR, correlators, matrix multiplication, and many other functions. The DSP blocks also support mixed modes and mixed multiplier sizes in the same block. For example, half of one DSP block can implement one 18 × 18-bit multiplier in multiply-accumulator mode, while the other half of the DSP block implements four 9 × 9-bit multipliers in simple multiplier mode.

Chapter 1:Overview for the Arria II Device FamilyArria II Device Architecture

Arria II Device Handbook Volume 1: Device Interfaces and Integration■Remote System Upgrade■Allows error-free deployment of system upgrades from a remote locationsecurely and reliably without an external controller■Soft logic (either the Nios II embedded processor or user logic) implementationin the device helps download a new configuration image from a remotelocation, store it in configuration memory, and direct the dedicated remotesystem upgrade circuitry to start a reconfiguration cycle■Dedicated circuitry in the remote system upgrade helps to avoid system downtime by performing error detection during and after the configuration process,recover from an error condition by reverting back to a safe configurationimage, and provides error status informationSEU Mitigation■Offers built-in error detection circuitry to detect data corruption due to soft errorsin the configuration random access memory (CRAM) cells■Allows all CRAM contents to be read and verified to match aconfiguration-computed cyclic redundancy check (CRC) value■You can identify and read out the bit location and the type of soft error through theJTAG or the core interfaceJTAG Boundary Scan Testing ■Supports JTAG IEEE Std. 1149.1 and IEEE Std. 1149.6 specifications■IEEE Std. 1149.6 supports high-speed serial interface (HSSI) transceivers andperforms boundary scan on alternating current (AC)-coupled transceiver channels■Boundary-scan test (BST) architecture offers the capability to test pin connectionswithout using physical test probes and capture functional data while a device isoperating normallyChapter 3:Memory Blocks in Arria II DevicesMemory Modes

1.Intel® Agilex™ General-Purpose I/O and LVDS SERDESOverviewThe Intel® Agilex™ I/O system includes a general-purpose I/O (GPIO) interface, aSecure Device Manager (SDM) I/O interface, and a Hard Processor System (HPS) I/Ointerface. Each I/O interface is designed to meet different interfacing requirements.The general-purpose I/O interface system support:•1.2 V single-ended non-voltage referenced Joint Electron Device EngineeringCouncil (JEDEC) compliant I/O standards.•1.2 V single-ended and differential voltage referenced JEDEC compliant I/Ostandards.•True differential I/O compatible with LVDS and able to interface with LVDS subsetssuch as RSDS, Mini-LVDS, Sub-LVDS, and any I/O standards that use equivalentelectrical specification.•DDR4 memory interface up to 1600 MHz with a Hard Memory Controller (HMC).•LVDS serializer/deserializer (SERDES) interface up to 1.6 Gbps.The SDM and HPS I/O interfaces can support 1.8 V single-ended non-voltagereferenced I/O standard for SDM and HPS interfacing.Related InformationIntel Agilex Device Data Sheet1.1. Intel Agilex I/O and Differential I/O BuffersThe I/O bank within the GPIO interface supports differential and single-ended I/Ostandards. The GPIO bank has true differential I/O buffer pairs using the TrueDifferential Signaling I/O standard, which is compatible with the LVDS, RSDS, Mini-LVDS, and LVPECL I/O standards. One true differential buffer pair forms a truedifferential channel. When using SERDES, half of the true differential buffers supportdedicated transmitter channels and the other half support dedicated true receiverchannels. When SERDES is not used, you can configure any of the true differentialbuffers to transmitter or receiver channels. Refer to the device pin-out files forlocations of the dedicated receiver and transmitter channels.Differential voltage referenced output pins are not true differential output pins. Thedifferential voltage referenced I/O standards use two single-ended output pins whereone of the output pins is inverted.The I/O bank within the HPS and SDM interfaces supports single-ended IO standards.Intel Agilex devices use different power supplies to power I/O buffers for differentinterfaces:UG-20214 | 2021.04.05Send Feedback

GW1N系列FPGA产品

数据手册

DS100-1.6, 2019-02-14

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版本信息

日期 版本 说明

2016/03/31 1.05 初始版本。

2016/04/14 1.06 修正PLL示意图，统一S-SRAM、B-SRAM术语

2016/04/18 1.07  更新GW1N-1 MG160和PG204封装的最大用户IO数

P4；

 增加JTAG和SSPI管脚不支持IO Logic。

2016/07/11 1.08  更新器件封装标识；

 更新JTAG和SSPI编程的时序图和时序参数定义；

 更新B-SRAM操作模式和时钟模式的结构框图；

 更新PLL结构框图、RESET_P描述；

 增加GW1N-2/4 QN32封装信息。

2016/09/23 1.09  更新产品信息列表及封装信息列表；

 更新用户闪存时钟频率；

 更新DUALBOOT的描述：当内置Flash为空时，器件

不进行配置操作；

 内部OSC默认频率更新为2.1MHz；

 添加QN88的ESD性能参数，所有封装的ESD性能参