stm32f103中文资料

stm32f103芯片STM32F103是STMicroelectronics（ST半导体）推出的一款高性能、低功耗的32位ARM Cortex-M3单片机系列芯片。

它是STMicroelectronics公司在2007年推出的STM32系列产品之一，也是最早得到广泛使用的一款产品，至今仍有很高的市场份额。

STM32F103芯片采用ARM Cortex-M3内核，运行频率高达72MHz，具有较强的计算能力。

该系列芯片采用了先进的32位RISC架构，支持高达7个程序可见的寄存器组，以及高达20个通用寄存器。

它具有高性能、高效能的特点，能够满足各类应用的需求。

STM32F103芯片拥有丰富的外设资源，包括多个通用定时器、高速串口、I2C总线、SPI总线、CAN总线等，并且具有多个GPIO引脚可供用户使用。

这些外设资源的丰富性可满足各类应用的需求，同时也能够减少外部芯片的使用，提高整个系统的集成度。

STM32F103芯片还具有良好的低功耗特性。

它采用了先进的功耗管理机制，并且支持多种低功耗模式，例如低功耗待机模式、低功耗休眠模式等。

这些低功耗模式可以有效降低系统的功耗，延长系统的电池寿命，适用于对功耗要求较高的应用场景，如便携设备、无线传感器网络等。

STM32F103芯片还支持多种通信协议，包括SPI、I2C、CAN等常用通信协议，使得它能够与其他设备进行高效可靠的通信。

同时，该芯片还支持USB OTG（On-The-Go）功能，允许设备在主机模式和设备模式之间切换，具有较好的灵活性和扩展性。

总的来说，STM32F103芯片是一款功能丰富、性能卓越的32位ARM Cortex-M3单片机系列芯片。

它具有高性能、低功耗、丰富的外设资源和通信能力等特点，适用于各种应用场景，如工业控制、智能家居、医疗设备、电力电子等。

由于其优秀的性能和可靠性，STMicroelectronics的STM32F103芯片在市场上得到了广泛的推广和应用。

stm32f103中文手册一、概述高性能的ARM 32位Cortex-M3CPU，主频可达72MHz，具有单周期乘法和硬件除法指令，支持嵌套向量中断控制器（NVIC）和嵌入式跟踪宏单元（ETM）。

高密度的存储器资源，包括64KB至512KB的闪存，20KB至64KB的SR AM，以及可选的2KB的备份SRAM。

丰富的外设资源，包括12个通用定时器，2个高级定时器，3个同步串行接口（SPI），2个I2C接口，5个USART接口，1个USB全速设备接口，1个CAN接口，2个DAC转换器，2个12位ADC转换器，以及多达80个G PIO引脚。

灵活的时钟控制系统，支持4种内部时钟源和4种外部时钟源，以及多种预分频器和倍频器。

低功耗模式，包括睡眠模式、停止模式和待机模式，以及电压监测和温度传感器功能。

先进的调试和编程功能，支持JTAG和SWD接口，以及串行线调试（SWV）和串行线跟踪（SWO）功能。

二、引脚定义stm32f103的引脚定义如下图所示：其中：VDDA和VSSA分别为模拟电源正负极。

VDD和VSS分别为数字电源正负极。

NRST为复位引脚。

BOOT0和BOOT1为启动模式选择引脚。

PA0至PA15为端口A的16个GPIO引脚。

PB0至PB15为端口B的16个GPIO引脚。

PC0至PC15为端口C的16个GPIO引脚。

PD0至PD15为端口D的16个GPIO引脚（仅144引脚封装有）。

PE0至PE15为端口E的16个GPIO引脚（仅144引脚封装有）。

OSC_IN和OSC_OUT为外部晶振输入输出引脚。

JTMS/SWDIO、JTCK/SWCLK、JTDI、JTDO/TRACESWO、JNTRST分别为JTAG/SWD接口的5个信号线。

PB6/PB7/PB8/PB9/PB10/PB11分别可作为I2C1/I2C2接口的SCL/SDA 信号线。

PA4/PA5/PA6/PA7/PB12/PB13/PB14/PB15分别可作为SPI1/SPI2接口的NSS/SCK/MISO/MOSI信号线。

stm32f103中文手册概述72 MHz的最大主频，1.25 DMIPS/MHz的性能64 KB到512 KB的闪存，20 KB到64 KB的SRAM7个通道的DMA控制器2个12位模数转换器（ADC），每一个ADC最多16个通道2个数字摹拟转换器（DAC）3个高级控制定时器，4个通用定时器，2个基本定时器，1个系统定时器1个USB全速设备接口2个CAN总线接口3个I2C总线接口5个USART接口，其中3个支持同步通信2个SPI总线接口1个SDIO接口51到112个GPIO引脚，支持中断和唤醒功能7到12位的LCD驱动器（仅STM32F103x8和STM32F103xB）多种低功耗模式，包括停机、待机、睡眠和住手模式多种时钟源和时钟安全系统多种复位源和复位管理系统多种保护机制，包括闪存写保护、调试访问保护、电源电压检测等引脚分配stm32f103有多种封装形式，包括LQFP64、LQFP100、LQFP144、BG A100、BGA144等。

不同封装形式的引脚分配如下图所示：![引脚分配图]存储器映射stm32f103的存储器空间为4GB，分为两部份：代码区和系统区。

代码区占用前2GB，用于存放程序代码和数据。

系统区占用后2GB，用于存放外设寄存器和系统服务。

存储器映射如下表所示：---地址范围 ---描述 ---------------0x0000 0000 0x1FFF FFFF ---代码区 -------0x2000 0000 0x2000 FFFF ---SRAM -------0x4000 0000 0x4002 3FFF ---外设寄存器 -------0x4200 0000 0x43FF FFFF ---外设位带区 -------0xE000 0000 0xE00F FFFF ---Cortex-M3系统服务 ----外设介绍ADCstm32f103有两个12位ADC，每一个ADC最多可以配置16个输入通道。

stm32f103芯片手册STM32F103是一款Cortex-M3内核的32位MCU芯片，由意法半导体（STMicroelectronics）公司生产。

该芯片具有低功耗、高计算性能和丰富的外设接口的特点，被广泛应用于各种应用领域。

下面是对STM32F103芯片手册的1000字简要介绍。

首先，STM32F103芯片具有强大的计算能力和丰富的存储器资源。

它采用了ARM Cortex-M3内核，主频可高达72MHz，同时支持单周期乘法和硬件除法指令，可快速执行复杂的算法。

此外，芯片内置了128KB或256KB的闪存和20KB的静态RAM，可以存储大量的程序代码和数据。

其次，STM32F103芯片提供了丰富的外设接口，能够满足各种应用需求。

它包括多个通用输入/输出（GPIO）引脚，可用于连接外部设备和传感器。

同时，芯片还提供了多个串行通信接口，如USART、SPI和I2C，可以与其他设备进行高速数据传输。

此外，芯片还支持多个定时器/计数器，用于实现精确的计时和定时功能。

第三，STM32F103芯片具有低功耗特性和丰富的电源管理功能。

它采用了多种节能技术，如待机模式、休眠模式和停机模式，可以最大限度地降低功耗。

同时，芯片还内置了多个电源管理模块，例如低功耗时钟、电压调整器和电池备份电源，以提供稳定可靠的电源供应。

最后，STM32F103芯片还提供了完善的开发工具和支持资源。

意法半导体提供了一整套的软件开发工具，包括Keil MDK和IAR Embedded Workbench等，可简化开发流程。

此外，芯片手册还详细介绍了芯片的引脚定义、寄存器配置、时钟设置、中断管理、外设控制等内容，为开发者提供了全面的技术支持。

综上所述，STM32F103芯片手册详细介绍了该芯片的技术规格、外设接口、低功耗特性和开发支持资源。

它具有强大的计算能力、丰富的存储资源和多样化的外设功能，适用于各种应用领域，如工业控制、智能家居、医疗设备等。

Features•ARM® 32-bit Cortex®-M3 CPU Core –72 MHz maximum frequency,1.25 DMIPS/MHz (Dhrystone2.1)performance at 0 wait state memoryaccess–Single-cycle multiplication and hardware division•Memories–64 or 128 Kbytes of Flash memory–20 Kbytes of SRAM•Clock, reset and supply management – 2.0 to 3.6 V application supply and I/Os–POR, PDR, and programmable voltage detector (PVD)–4-to-16 MHz crystal oscillator–Internal 8 MHz factory-trimmed RC–Internal 40 kHz RC–PLL for CPU clock–32 kHz oscillator for RTC with calibration •Low-power–Sleep, Stop and Standby modes–V BAT supply for RTC and backup registers • 2 x 12-bit, 1 µs A/D converters (up to 16channels)–Conversion range: 0 to 3.6 V–Dual-sample and hold capability–Temperature sensor•DMA–7-channel DMA controller–Peripherals supported: timers, ADC, SPIs, I2Cs and USARTs•Up to 80 fast I/O ports–26/37/51/80 I/Os, all mappable on 16 external interrupt vectors and almost all5 V-tolerant •Debug mode–Serial wire debug (SWD) & JTAGinterfaces•7 timers–Three 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter andquadrature (incremental) encoder input –16-bit, motor control PWM timer with dead-time generation and emergency stop – 2 watchdog timers (Independent andWindow)–SysTick timer 24-bit downcounter•Up to 9 communication interfaces–Up to 2 x I2C interfaces (SMBus/PMBus)–Up to 3 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control)–Up to 2 SPIs (18 Mbit/s)–CAN interface (2.0B Active)–USB 2.0 full-speed interface•CRC calculation unit, 96-bit unique ID •Packages are ECOPACK®Table 1. Device summaryReference Part numberSTM32F103x8STM32F103C8, STM32F103R8STM32F103V8, STM32F103T8STM32F103xBSTM32F103RB STM32F103VB,STM32F103CB, STM32F103TB找Memory、FPGA、二三极管、连接器、模块、光耦、电容电阻、单片机、处理器、晶振、传感器、滤波器，上深圳市美光存储技术有限公司August 20152.2 Full compatibility throughout the familyThe STM32F103xx is a complete family whose members are fully pin-to-pin, software andfeature compatible. In the reference manual, the STM32F103x4 and STM32F103x6 areidentified as low-density devices, the STM32F103x8 and STM32F103xB are referred to asmedium-density devices, and the STM32F103xC, STM32F103xD and STM32F103xE arereferred to as high-density devices.Low- and high-density devices are an extension of the STM32F103x8/B devices, they arespecified in the STM32F103x4/6 and STM32F103xC/D/E datasheets, respectively. Low-density devices feature lower Flash memory and RAM capacities, less timers andperipherals. High-density devices have higher Flash memory and RAM capacities, andadditional peripherals like SDIO, FSMC, I2S and DAC, while remaining fully compatible withthe other members of the STM32F103xx family.The STM32F103x4, STM32F103x6, STM32F103xC, STM32F103xD and STM32F103xEare a drop-in replacement for STM32F103x8/B medium-density devices, allowing the userto try different memory densities and providing a greater degree of freedom during thedevelopment cycle.Moreover, the STM32F103xx performance line family is fully compatible with all existingSTM32F101xx access line and STM32F102xx USB access line devices.2.3.13 DMAThe flexible 7-channel general-purpose DMA is able to manage memory-to-memory,peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supportscircular buffer management avoiding the generation of interrupts when the controllerreaches the end of the buffer.Each channel is connected to dedicated hardware DMA requests, with support for softwaretrigger on each channel. Configuration is made by software and transfer sizes betweensource and destination are independent.The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose andadvanced-control timers TIMx and ADC.Description STM32F103x8, STM32F103xBAdvanced-control timer (TIM1)The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6channels. It has complementary PWM outputs with programmable inserted dead-times. Itcan also be seen as a complete general-purpose timer. The 4 independent channels can beused for•Input capture•Output compare•PWM generation (edge- or center-aligned modes)•One-pulse mode outputIf configured as a general-purpose 16-bit timer, it has the same features as the TIMx timer. Ifconfigured as the 16-bit PWM generator, it has full modulation capability (0-100%).In debug mode, the advanced-control timer counter can be frozen and the PWM outputsdisabled to turn off any power switch driven by these outputs.Many features are shared with those of the general-purpose TIM timers which have thesame architecture. The advanced-control timer can therefore work together with the TIMtimers via the Timer Link feature for synchronization or event chaining.General-purpose timers (TIMx)There are up to three synchronizable general-purpose timers embedded in theSTM32F103xx performance line devices. These timers are based on a 16-bit auto-reloadup/down counter, a 16-bit prescaler and feature 4 independent channels each for inputcapture/output compare, PWM or one-pulse mode output. This gives up to 12 inputcaptures/output compares/PWMs on the largest packages.The general-purpose timers can work together with the advanced-control timer via the TimerLink feature for synchronization or event chaining. Their counter can be frozen in debugmode. Any of the general-purpose timers can be used to generate PWM outputs. They allhave independent DMA request generation.These timers are capable of handling quadrature (incremental) encoder signals and thedigital outputs from 1 to 3 hall-effect sensors.Independent watchdogThe independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It isclocked from an independent 40 kHz internal RC and as it operates independently of themain clock, it can operate in Stop and Standby modes. It can be used either as a watchdogto reset the device when a problem occurs, or as a free-running timer for application timeoutmanagement. It is hardware- or software-configurable through the option bytes. The countercan be frozen in debug mode.Window watchdogThe window watchdog is based on a 7-bit downcounter that can be set as free-running. Itcan be used as a watchdog to reset the device when a problem occurs. It is clocked fromthe main clock. It has an early warning interrupt capability and the counter can be frozen indebug mode.。

mpu6050中文数据手册STM32F103CDE_DS_中文数据手册_V5导读：就爱阅读网友为您分享以下“STM32F103CDE_DS_中文数据手册_V5”的资讯，希望对您有所帮助，感谢您对92to 的支持!STM32F103xC, STM32F103xD, STM32F103xE数据手册55.1电气特性测试条件除非特别说明，所有电压的都以VSS为基准。

5.1.1 最小和最大数值除非特别说明，在生产线上通过对100%的产品在环境温度TA=25°C和TA=TAmax下执行的测试(TAmax与选定的温度范围匹配)，所有最小和最大值将在最坏的环境温度、供电电压和时钟频率条件下得到保证。

在每个表格下方的注解中说明为通过综合评估、设计模拟和/或工艺特性得到的数据，不会在生产线上进行测试；在综合评估的基础上，最小和最大数值是通过样本测试后，取其平均值再加减三倍的标准分布(平均±3∑)得到。

5.1.2 典型数值除非特别说明，典型数据是基于TA=25°C和VDD=3.3V(2V ≤ VDD ≤ 3.3V电压范围)。

这些数据仅用于设计指导而未经测试。

典型的ADC精度数值是通过对一个标准的批次采样，在所有温度范围下测试得到，95%产品的误差小于等于给出的数值(平均±2∑)。

5.1.3 典型曲线除非特别说明，典型曲线仅用于设计指导而未经测试。

5.1.4 负载电容测量引脚参数时的负载条件示于图10中。

图10引脚的负载条件5.1.5 引脚输入电压引脚上输入电压的测量方式示于图11中。

图11引脚输入电压参照2009年3月STM32F103xCDE数据手册英文第5版（本译文仅供参考，如有翻译错误，请以英文原稿为准）29/87STM32F103xC, STM32F103xD, STM32F103xE数据手册5.1.6 供电方案图12供电方案注：上图中的4.7μF电容必须连接到VDD3。

STM32F103系列微处理器，STM微电子设备**STM32F103**Cortex-M3内核，CPU速度为72MHz，最大闪存为1MB。

包括电机控制外设和USB全速接口。

STM32系列arm型Cortex-M3 32位闪存微控制器具有功耗低、电压低、性能优良、实时性好等特点。

这一系列的包类型可以在您的嵌入式应用程序中使用。

MCU架构具有易于使用的STM32平台，适用于电机驱动、PC和游戏、HVAC和工业应用等应用。

32位RISC针对针软件兼容SRAM高达96 KB闪存高达1MB电源：2 V至3.6 V温度范围：-40至+85°C或-40至+105°C stm32f1系列32位arm？皮质？-m3微控制器，STMicroelectronics（STMicroelectronics）基于arm cortex的32位闪存微控制器STM32系列™M3核心突破了嵌入式应用的特殊开发核心。

STM32系列得益于Cortex-M3体系结构的增强，包括Thumb-2指令集，它可以传递更高的性能、更好的编码密度、更快的中断响应以及所有领先的工业功耗。

卓越的实时性能、卓越的效率和全新的外围设备可以最大限度地实现系列管脚之间的集成、外围设备和软件的兼容性Stm32f103c8t6是一款中密度性能线，配备Arm Cortex-M3 32位微控制器，48路LQFP 封装。

它结合了一个高性能的RISC核心，72MHz工作频率，高速嵌入式存储器，增强的I/O范围和外部连接两个APB总线。

Stm32f103c8t6具有12位模数转换器、定时器、PWM定时器、标准和高级通信接口。

综合省电模式允许设计师设计低功耗应用. 工作电压范围：2V到3.6v。

64k字节的闪存。

20K字节SRAM.CRC计算单元，96位唯一ID。

两个12位1μs ADC（最多10个通道）。

7通道DMA控制器，3个通用定时器和1个高级控制定时器。

Contents STM32F103x8,STM32F103xB Contents1Introduction (9)2Description (9)2.1Device overview (10)2.2Full compatibility throughout the family (13)2.3Overview (14)2.3.1ARM®Cortex™-M3core with embedded Flash and SRAM (14)2.3.2Embedded Flash memory (14)2.3.3CRC(cyclic redundancy check)calculation unit (14)2.3.4Embedded SRAM (14)2.3.5Nested vectored interrupt controller(NVIC) (14)2.3.6External interrupt/event controller(EXTI) (15)2.3.7Clocks and startup (15)2.3.8Boot modes (15)2.3.9Power supply schemes (15)2.3.10Power supply supervisor (15)2.3.11Voltage regulator (16)2.3.12Low-power modes (16)2.3.13DMA (17)2.3.14RTC(real-time clock)and backup registers (17)2.3.15Timers and watchdogs (17)2.3.16I²C bus (19)2.3.17Universal synchronous/asynchronous receiver transmitter(USART)..192.3.18Serial peripheral interface(SPI) (19)2.3.19Controller area network(CAN) (19)2.3.20Universal serial bus(USB) (19)2.3.21GPIOs(general-purpose inputs/outputs) (20)2.3.22ADC(analog-to-digital converter) (20)2.3.23T emperature sensor (20)2.3.24Serial wire JTAG debug port(SWJ-DP) (20)3Pinouts and pin description (21)4Memory mapping (34)2/105DocID13587Rev16STM32F103x8,STM32F103xB Contents5Electrical characteristics (35)5.1Parameter conditions (35)5.1.1Minimum and maximum values (35)5.1.2Typical values (35)5.1.3Typical curves (35)5.1.4Loading capacitor (35)5.1.5Pin input voltage (35)5.1.6Power supply scheme (36)5.1.7Current consumption measurement (37)5.2Absolute maximum ratings (37)5.3Operating conditions (38)5.3.1General operating conditions (38)5.3.2Operating conditions at power-up/power-down (39)5.3.3Embedded reset and power control block characteristics (40)5.3.4Embedded reference voltage (41)5.3.5Supply current characteristics (41)5.3.6External clock source characteristics (51)5.3.7Internal clock source characteristics (55)5.3.8PLL characteristics (57)5.3.9Memory characteristics (57)5.3.10EMC characteristics (58)5.3.11Absolute maximum ratings(electrical sensitivity) (60)5.3.12I/O current injection characteristics (61)5.3.13I/O port characteristics (62)5.3.14NRST pin characteristics (68)5.3.15TIM timer characteristics (69)5.3.16Communications interfaces (70)5.3.17CAN(controller area network)interface (75)5.3.1812-bit ADC characteristics (76)5.3.19T emperature sensor characteristics (80)6Package characteristics (81)6.1Package mechanical data (81)6.2Thermal characteristics (93)6.2.1Reference document (93)6.2.2Selecting the product temperature range (94)DocID13587Rev163/105Contents STM32F103x8,STM32F103xB7Ordering information scheme (96)8Revision history (97)4/105DocID13587Rev16STM32F103x8,STM32F103xB List of tables List of tablesT able1.Device summary (1)T able2.STM32F103xx medium-density device features and peripheral counts (10)T able3.STM32F103xx family (13)T able4.Timer feature comparison (17)T able5.Medium-density STM32F103xx pin definitions (28)T able6.Voltage characteristics (37)T able7.Current characteristics (38)T able8.Thermal characteristics (38)T able9.General operating conditions (38)T able10.Operating conditions at power-up/power-down (39)T able11.Embedded reset and power control block characteristics (40)T able12.Embedded internal reference voltage (41)T able13.Maximum current consumption in Run mode,code with data processingrunning from Flash (42)T able14.Maximum current consumption in Run mode,code with data processingrunning from RAM (42)T able15.Maximum current consumption in Sleep mode,code running from Flash or RAM (44)T able16.Typical and maximum current consumptions in Stop and Standby modes (45)T able17.Typical current consumption in Run mode,code with data processingrunning from Flash (48)T able18.Typical current consumption in Sleep mode,code running from Flash orRAM (49)T able19.Peripheral current consumption (50)T able20.High-speed external user clock characteristics (51)T able21.Low-speed external user clock characteristics (51)T able22.HSE4-16MHz oscillator characteristics (53)T able23.LSE oscillator characteristics(f LSE=32.768kHz) (54)T able24.HSI oscillator characteristics (55)T able25.LSI oscillator characteristics (56)T able26.Low-power mode wakeup timings (57)T able27.PLL characteristics (57)T able28.Flash memory characteristics (57)T able29.Flash memory endurance and data retention (58)T able30.EMS characteristics (59)T able31.EMI characteristics (59)T able32.ESD absolute maximum ratings (60)T able33.Electrical sensitivities (60)T able34.I/O current injection susceptibility (61)T able35.I/O static characteristics (62)T able36.Output voltage characteristics (66)T able37.I/O AC characteristics (67)T able38.NRST pin characteristics (68)T able39.TIMx characteristics (69)T able40.I2C characteristics (70)T able41.SCL frequency(f PCLK1=36MHz.,V DD_I2C=3.3V) (71)T able42.SPI characteristics (72)T B startup time (74)T B DC electrical characteristics (75)DocID13587Rev165/105List of tables STM32F103x8,STM32F103xBT B:Full-speed electrical characteristics (75)T able46.ADC characteristics (76)T able47.R AIN max for f ADC=14MHz (77)T able48.ADC accuracy-limited test conditions (77)T able49.ADC accuracy (78)T able50.TS characteristics (80)T able51.VFQFPN366x6mm,0.5mm pitch,package mechanical data (82)T able52.UFQFPN487x7mm,0.5mm pitch,package mechanical data (83)T able53.LFBGA100-10x10mm low profile fine pitch ball grid array packagemechanical data (85)T able54.LQPF100,14x14mm100-pin low-profile quad flat package mechanical data (87)T able55.UFBGA100-ultra fine pitch ball grid array,7x7mm,0.50mm pitch,packagemechanical data (88)T able56.LQFP64,10x10mm,64-pin low-profile quad flat package mechanical data (89)T able57.TFBGA64-8x8active ball array,5x5mm,0.5mm pitch,package mechanical data (90)T able58.LQFP48,7x7mm,48-pin low-profile quad flat package mechanical data (92)T able59.Package thermal characteristics (93)T able60.Ordering information scheme (96)T able61.Document revision history (97)6/105DocID13587Rev16STM32F103x8,STM32F103xB List of figures List of figuresFigure1.STM32F103xx performance line block diagram (11)Figure2.Clock tree (12)Figure3.STM32F103xx performance line LFBGA100ballout (21)Figure4.STM32F103xx performance line LQFP100pinout (22)Figure5.STM32F103xx performance line UFBGA100pinout (23)Figure6.STM32F103xx performance line LQFP64pinout (24)Figure7.STM32F103xx performance line TFBGA64ballout (25)Figure8.STM32F103xx performance line LQFP48pinout (26)Figure9.STM32F103xx performance line UFQFPN48pinout (26)Figure10.STM32F103xx performance line VFQFPN36pinout (27)Figure11.Memory map (34)Figure12.Pin loading conditions (36)Figure13.Pin input voltage (36)Figure14.Power supply scheme (36)Figure15.Current consumption measurement scheme (37)Figure16.Typical current consumption in Run mode versus frequency(at3.6V)-code with data processing running from RAM,peripherals enabled (43)Figure17.Typical current consumption in Run mode versus frequency(at3.6V)-code with data processing running from RAM,peripherals disabled (43)Figure18.Typical current consumption on V BAT with RTC on versus temperature at differentV BAT values (45)Figure19.Typical current consumption in Stop mode with regulator in Run mode versustemperature at V DD=3.3V and3.6V (46)Figure20.Typical current consumption in Stop mode with regulator in Low-power mode versustemperature at V DD=3.3V and3.6V (46)Figure21.Typical current consumption in Standby mode versus temperature atV DD=3.3V and3.6V (47)Figure22.High-speed external clock source AC timing diagram (52)Figure23.Low-speed external clock source AC timing diagram (52)Figure24.Typical application with an8MHz crystal (53)Figure25.Typical application with a32.768kHz crystal (55)Figure26.Standard I/O input characteristics-CMOS port (64)Figure27.Standard I/O input characteristics-TTL port (64)Figure28.5V tolerant I/O input characteristics-CMOS port (65)Figure29.5V tolerant I/O input characteristics-TTL port (65)Figure30.I/O AC characteristics definition (68)Figure31.Recommended NRST pin protection (69)Figure32.I2C bus AC waveforms and measurement circuit (71)Figure33.SPI timing diagram-slave mode and CPHA=0 (73)Figure34.SPI timing diagram-slave mode and CPHA=1(1) (73)Figure35.SPI timing diagram-master mode(1) (74)B timings:definition of data signal rise and fall time (75)Figure37.ADC accuracy characteristics (78)Figure38.Typical connection diagram using the ADC (79)Figure39.Power supply and reference decoupling(V REF+not connected to V DDA) (79)Figure40.Power supply and reference decoupling(V REF+connected to V DDA) (80)Figure41.VFQFPN366x6mm,0.5mm pitch,package outline(1) (82)Figure42.VFQFPN36recommended footprint(dimensions in mm)(1)(2) (82)DocID13587Rev167/105List of figures STM32F103x8,STM32F103xBFigure43.UFQFPN487x7mm,0.5mm pitch,package outline (83)Figure44.UFQFPN48recommended footprint (84)Figure45.LFBGA100-10x10mm low profile fine pitch ball grid array packageoutline (85)Figure46.Recommended PCB design rules(0.80/0.75mm pitch BGA) (86)Figure47.LQFP100,14x14mm100-pin low-profile quad flat package outline (87)Figure48.LQFP100recommended footprint(1) (87)Figure49.UFBGA100-ultra fine pitch ball grid array,7x7mm,0.50mm pitch,package outline (88)Figure50.LQFP64,10x10mm,64-pin low-profile quad flat package outline (89)Figure51.LQFP64recommended footprint(1) (89)Figure52.TFBGA64-8x8active ball array,5x5mm,0.5mm pitch,package outline (90)Figure53.Recommended PCB design rules for pads(0.5mm pitch BGA) (91)Figure54.LQFP48,7x7mm,48-pin low-profile quad flat package outline (92)Figure55.LQFP48recommended footprint(1) (92)Figure56.LQFP100P D max vs.T A (95)8/105DocID13587Rev16STM32F103x8,STM32F103xB Introduction 1IntroductionThis datasheet provides the ordering information and mechanical device characteristics ofthe STM32F103x8and STM32F103xB medium-density performance line microcontrollers.For more details on the whole STMicroelectronics STM32F103xx family,please refer toSection2.2:Full compatibility throughout the family.The medium-density STM32F103xx datasheet should be read in conjunction with the low-,medium-and high-density STM32F10xxx reference manual.The reference and Flash programming manuals are both available from theSTMicroelectronics website .For information on the Cortex™-M3core please refer to the Cortex™-M3T echnicalReference Manual,available from the website at the following address:/help/index.jsp?topic=/com.arm.doc.ddi0337e/2DescriptionThe STM32F103xx medium-density performance line family incorporates the high-performance ARM Cortex™-M332-bit RISC core operating at a72MHz frequency,high-speed embedded memories(Flash memory up to128Kbytes and SRAM up to20Kbytes),and an extensive range of enhanced I/Os and peripherals connected to two APB buses.Alldevices offer two12-bit ADCs,three general purpose16-bit timers plus one PWM timer,aswell as standard and advanced communication interfaces:up to two I2Cs and SPIs,threeUSART s,an USB and a CAN.The devices operate from a2.0to3.6V power supply.They are available in both the–40to+85°C temperature range and the–40to+105°C extended temperature range.Acomprehensive set of power-saving mode allows the design of low-power applications.The STM32F103xx medium-density performance line family includes devices in six differentpackage types:from36pins to100pins.Depending on the device chosen,different sets ofperipherals are included,the description below gives an overview of the complete range ofperipherals proposed in this family.These features make the STM32F103xx medium-density performance line microcontrollerfamily suitable for a wide range of applications such as motor drives,application control,medical and handheld equipment,PC and gaming peripherals,GPS platforms,industrialapplications,PLCs,inverters,printers,scanners,alarm systems,video intercoms,andHVACs.DocID13587Rev169/105TimersCommunicationDescription STM32F103x8,STM32F103xB 2.1Device overviewTable2.STM32F103xx medium-density device features and peripheral1.On the TFBGA64package only15channels are available(one analog input pin has been replaced by‘Vref+’).10/105DocID13587Rev16Peripheral STM32F103Tx STM32F103Cx STM32F103Rx STM32F103Vx Flash-Kbytes64128641286412864128SRAM-Kbytes20202020 General-purpose3333Advanced-control1111SPI12222I C1222USART2333USB1111CAN1111 GPIOs2637518012-bit synchronized ADCNumber of channels210channels210channels2(1)16channels216channels CPU frequency72MHzOperating voltage 2.0to3.6VOperating temperaturesAmbient temperatures:-40to+85°C/-40to+105°C(see Table9)Junction temperature:-40to+125°C(see Table9)Packages VFQFPN36LQFP48,UFQFPN48LQFP64,TFBGA64LQFP100,LFBGA100,UFBGA100f l a s ho b lI n t e r f a c eB u s M a t r i xA HB :F m a x =48/72M H zA PB 2:F m a x =48/72M H zA PB 1:F m a x =24/36M H zpbusPCLK2 HCLK CLOCK RTC AWUTAMPER -RTCSTM32F103x8, STM32F103xBDescriptionFigure 1. STM32F103xx performance line block diagramTRACECLKTRACED[0:3] as ASNJTRSTTRSTJTDIJTCK/SWCLK JTMS/SWDIOJTDO as AFTPIUTrace/trigSW/JTAGCortex -M3 CPUIbusF max : 7 2M Hz DbusTraceControlle rFlash 128 KB64 bitPOWERVOLT. REG. 3.3V TO 1.8V@VDDV DD = 2 to 3.6VV SSNVICSystemSRAM20 KB@VDDGP DMA7 channelsPCLK1 FCLKPLL &MANAGTXTAL OSC4-16 MHzOSC_INOSC_OUTRC 8 MHzNRST @VDDASUPPLYSUPERVISIONRC 40 kHz @VDDA@VBATIWDG Standby interfaceV BATVDDA VSSA 80AF PA[15:0] PB[15:0]POR / PDRPVDEXTIWAKEUPGPIOAGPIOBRstIntAHB2 AHB2APB2 APB1XTAL 32 kHzBackup reg Backu p i nterf ace TIM2 TIM3OSC32_IN OSC32_OUT4 Channels 4 ChannelsPC[15:0]GPIOCTIM 44 ChannelsPD[15:0]GPIOD PE[15:0] GPIOEUSART2USART3RX,TX, CTS, RTS,CK, SmartCard as AFRX,TX, CTS, RTS, CK, SmartCard as AF4 Channels3 compl. ChannelsETR and BKINMOSI,MISO, SCK,NSS as AFRX,TX, CTS, RTS,TIM1SPI12x(8x16bit)SPI2I2C1 I2C2MOSI,MISO,SCK,NSS as AFSCL,SDA,SMBA as AFSCL,SDA as AFSmartCard as AFUSART1@VDDAbxCANUSBDP/CAN_TXUSB 2.0 FSUSBDM/CAN_RX16AF V REF+ V REF -12bit ADC1 IF12bit ADC2 IFSRAM 512BWWDGTemp sensorai14390d1. T A = –40 °C to +105 °C (junction temperature up to 125 °C).2. AF = alternate function on I/O port pin.DocID13587 Rev 1611/105peripheralsIf (APB2 prescaler =1) x1 ADC /2, 4, 6, 8 ADCCLKDescriptionSTM32F103x8, STM32F103xBFigure 2. Clock treeFLITFCLKto Flash programming interface8 MHz HSI RCHSIUSBPrescaler 48 MHzUSBCLKto USB interface/2/1, 1.572 MHz maxClockHCLKto AHB bus, core, memory and DMA PLLSRCSWPLLMUL/8Enable (3 bits)to Cortex System timerFCLK Cortex..., x16 x2, x3, x4 PLLHSIPLLCLK HSESYSCLK72 MHz max AHB Prescaler /1, 2..512 APB1Prescaler/1, 2, 4, 8, 16free running clock36 MHz max PCLK1to APB1Peripheral Clock Enable (13 bits)TIM2,3, 4to TIM2, 3and 4CSSIf (APB1 prescaler =1) x1 TIMXCLKelse x2 Peripheral ClockEnable (3 bits)OSC_OUTOSC_IN4-16 MHzHSE OSCPLLXTPRE/2APB2Prescaler/1, 2, 4, 8, 16TIM1 timer 72 MHz maxPeripheral ClockEnable (11 bits) PCLK2peripherals to APB2to TIM1 TIM1CLK else x2 Peripheral ClockOSC32_INOSC32_OUTLSE OSC32.768 kHz/128LSERTCCLKto RTCPrescaler Enable (1 bit) to ADCRTCSEL[1:0]LSI RCLSIto Independent Watchdog (IWDG)40 kHzIWDGCLKLegend:HSE = high -speed external clock signalHSI = high -speed internal clock signalMCOMainClock Output/2PLLCLKHSI LSI = low -speed internal clock signal LSE = low -speed external clock signalHSESYSCLKMCOai149031. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 64 MHz.2. For the USB function to be available, both HSE and PLL must be enabled, with USBCLK running at 48 MHz.3. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz, 28 MHz or 56 MHz.12/105DocID13587 Rev 16STM32F103x8, STM32F103xBDescription2.2 Full compatibility throughout the familyThe STM32F103xx is a complete family whose members are fully pin -to -pin, software and feature compatible. In the reference manual, the STM32F103x4 and STM32F103x6 are identified as low -density devices, the STM32F103x8 and STM32F103xB are referred to as medium -density devices, and the STM32F103xC, STM32F103xD and STM32F103xE are referred to as high -density devices.Low - and high -density devices are an extension of the STM32F103x8/B devices, they are specified in the STM32F103x4/6 and STM32F103xC/D/E datasheets, respectively. Low - density devices feature lower Flash memory and RAM capacities, less timers and peripherals. High -density devices have higher Flash memory and RAM capacities, and additional peripherals like SDIO, FSMC, I 2S and DAC, while remaining fully compatible with the other members of the STM32F103xx family .The STM32F103x4, STM32F103x6, STM32F103xC, STM32F103xD and STM32F103xE are a drop -in replacement for STM32F103x8/B medium -density devices, allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle.Moreover, the STM32F103xx performance line family is fully compatible with all existing STM32F101xx access line and STM32F102xx USB access line devices.1.For orderable part numbers that do not show the A internal code after the temperature range code (6 or 7),the reference datasheet for electrical characteristics is that of the STM32F103x8/B medium -density devices.DocID13587 Rev 16 13/105PinoutLow -density devicesMedium -density devices High -density devices 16 KB Flash 32 KB Flash (1) 64 KB Flash 128 KB Flash 256 KB Flash 384 KB Flash 512 KB Flash6 KB RAM 10 KB RAM 20 KB RAM 20 KB RAM 48 KB RAM 64 KB RAM 64 KB RAM144 5 × USART s 4 × 16-bit timers, 2 × basic timers2 3 × SPIs, 2 × I Ss, 2 × I2Cs USB, CAN, 2 × PWM timers 3 × ADCs, 2 × DACs, 1 × SDIOFSMC (100 and 144 pins) 100 3 × USART s 3 × 16-bit timers 2 2 × SPIs, 2 × I Cs, USB, CAN, 1 × PWM timer2 × ADCs 64 2 × USART s 2 × 16-bit timers 2 1 × SPI, 1 × I C, USB, CAN, 1 × PWM timer 2 × ADCs 48 36Description STM32F103x8,STM32F103xB 2.3Overview2.3.1ARM®Cortex™-M3core with embedded Flash and SRAMThe ARM Cortex™-M3processor is the latest generation of ARM processors for embeddedsystems.It has been developed to provide a low-cost platform that meets the needs of MCUimplementation,with a reduced pin count and low-power consumption,while deliveringoutstanding computational performance and an advanced system response to interrupts.The ARM Cortex™-M332-bit RISC processor features exceptional code-efficiency,delivering the high-performance expected from an ARM core in the memory size usuallyassociated with8-and16-bit devices.The STM32F103xx performance line family having an embedded ARM core,is thereforecompatible with all ARM tools and software.Figure1shows the general block diagram of the device family.2.3.2Embedded Flash memory64or128Kbytes of embedded Flash is available for storing programs and data.2.3.3CRC(cyclic redundancy check)calculation unitThe CRC(cyclic redundancy check)calculation unit is used to get a CRC code from a32-bitdata word and a fixed generator polynomial.Among other applications,CRC-based techniques are used to verify data transmission orstorage integrity.In the scope of the EN/IEC60335-1standard,they offer a means ofverifying the Flash memory integrity.The CRC calculation unit helps compute a signature ofthe software during runtime,to be compared with a reference signature generated at link-time and stored at a given memory location.2.3.4Embedded SRAMTwenty Kbytes of embedded SRAM accessed(read/write)at CPU clock speed with0waitstates.2.3.5Nested vectored interrupt controller(NVIC)The STM32F103xx performance line embeds a nested vectored interrupt controller able tohandle up to43maskable interrupt channels(not including the16interrupt lines ofCortex™-M3)and16priority levels.•Closely coupled NVIC gives low-latency interrupt processing•Interrupt entry vector table address passed directly to the core•Closely coupled NVIC core interface•Allows early processing of interrupts•Processing of late arriving higher priority interrupts•Support for tail-chaining•Processor state automatically saved•Interrupt entry restored on interrupt exit with no instruction overhead14/105DocID13587Rev16万联芯城专注电子元器件配单服务，只售原装现货库存，万联芯城电子元器件全国供应，专为终端生产，研发企业提供现货物料，价格优势明显，BOM配单采购可节省逐个搜索购买环节，只需提交BOM物料清单，商城即可为您报价，解决客户采购烦恼，为客户节省采购成本，点击进入万联芯城。