BTA208M-800C中文资料

TL C 5171NSC800 High-Performance Low-Power CMOS MicroprocessorJune1992 NSC800TM High-PerformanceLow-Power CMOS MicroprocessorGeneral DescriptionThe NSC800is an8-bit CMOS microprocessor that func-tions as the central processing unit(CPU)in National Semi-conductor’s NSC800microcomputer family National’smicroCMOS technology used to fabricate this device pro-vides system designers with performance equivalent tocomparable NMOS products but with the low power advan-tage of CMOS Some of the many system functions incorpo-rated on the device are vectored priority interrupts refreshcontrol power-save feature and interrupt acknowledge TheNSC800is available in dual-in-line and surface mountedchip carrier packagesThe system designer can choose not only from the dedicat-ed CMOS peripherals that allow direct interfacing to theNSC800but from the full line of National’s CMOS productsto allow a low-power system solution The dedicated periph-erals include NSC810A RAM I O Timer NSC858UARTand NSC831I OAll devices are available in commercial industrial and mili-tary temperature ranges along with two added reliabilityflows The first is an extended burn in test and the second isthe military class C screening in accordance with Method5004of MIL-STD-883FeaturesY Fully compatible with Z80 instruction setPowerful set of158instructions10addressing modes22internal registersY Low power 50mW at5V V CCY Unique power-save featureY Multiplexed bus structureY Schmitt trigger input on resetY On-chip bus controller and clock generatorY Variable power supply2 4V b6 0VY On-chip8-bit dynamic RAM refresh circuitryY Speed 1 0m s instruction cycle at4 0MHzNSC800-44 0MHzNSC800-353 5MHzNSC800-32 5MHzNSC800-11 0MHzY Capable of addressing64k bytes of memory and256I O devicesY Five interrupt request lines on-chipBlock DiagramTL C 5171–73NSC800TM is a trademark of National Semiconductor CorpTRI-STATE is a registered trademark of National Semiconductor CorpZ80 is a registered trademark of Zilog CorpC1995National Semiconductor Corporation RRD-B30M105 Printed in U S ATable of Contents1 0ABSOLUTE MAXIMUM RATINGS2 0OPERATING CONDITIONS3 0DC ELECTRICAL CHARACTERISTICS4 0AC ELECTRICAL CHARACTERISTICS5 0TIMING WAVEFORMSNSC800HARDWARE6 0PIN DESCRIPTIONS6 1Input Signals6 2Output Signals6 3Input Output Signals7 0CONNECTION DIAGRAMS8 0FUNCTIONAL DESCRIPTION8 1Register Array8 2Dedicated Registers8 2 1Program Counter8 2 2Stack Pointer8 2 3Index Register8 2 4Interrupt Register8 2 5Refresh Register8 3CPU Working and Alternate Register Sets8 3 1CPU Working Registers8 3 2Alternate Registers8 4Register Functions8 4 1Accumulator8 4 2F Register Flags8 4 3Carry(C)8 4 4Adds Subtract(N)8 4 5Parity Overflow(P V)8 4 6Half Carry(H)8 4 7Zero Flag(Z)8 4 8Sign Flag(S)8 4 9Additional General Purpose Registers8 4 10Alternate Configurations8 5Arithmetic Logic Unit(ALU)8 6Instruction Register and Decoder9 0TIMING AND CONTROL9 1Internal Clock Generator9 2CPU Timing9 3Initialization9 4Power Save Feature9 0TIMING AND CONTROL9 5Bus Access Control9 6Interrupt ControlNSC800SOFTWARE10 0INTRODUCTION11 0ADDRESSING MODES11 1Register11 2Implied11 3Immediate11 4Immediate Extended11 5Direct Addressing11 6Register Indirect11 7Indexed11 8Relative11 9Modified Page Zero11 10Bit12 0INSTRUCTION SET12 1Instruction Set Index Alphabetical12 2Instruction Set Mnemonic Notation12 3Assembled Object Code Notation12 48-Bit Loads12 516-Bit Loads12 68-Bit Arithmetic12 716-Bit Arithmetic12 8Bit Set Reset and Test12 9Rotate and Shift12 10Exchanges12 11Memory Block Moves and Searches12 12Input Output12 13CPU Control12 14Program Control12 15Instruction Set Alphabetical Order12 16Instruction Set Numerical Order13 0DATA ACQUISITION SYSTEM14 0NSC800M 883B MIL STD883 CLASS CSCREENING15 0BURN-IN CIRCUITS16 0ORDERING INFORMATION17 0RELIABILITY INFORMATION21 0Absolute Maximum Ratings(Note1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Storage Temperature b65 C to a150 C Voltage on Any Pinwith Respect to Ground b0 3V to V CC a0 3V Maximum V CC7V Power Dissipation1W Lead Temp (Soldering 10seconds)300 C 2 0Operating Conditions NSC800-1x T A e0 C to a70 CT A e b40 C to a85 C NSC800-3x T A e0 C to a70 CT A e b40 C to a85 CT A e b55 C to a125 C NSC800-35 883C x T A e b55 C to a125 C NSC800-4x T A e0 C to a70 CT A e b40 C to a85 C NSC800-4MIL x T A e b55 C to a90 C3 0DC Electrical Characteristics V CC e5V g10% GND e0V unless otherwise specifiedSymbol Parameter Conditions Min Typ Max Units V IH Logical1Input Voltage0 8V CC V CC V V IL Logical0Input Voltage00 2V CC V V HY Hysteresis at RESET IN input V CC e5V0 250 5V V OH1Logical1Output Voltage I OUT e b1 0mA2 4V V OH2Logical1Output Voltage I OUT e b10m A V CC b0 5V V OL1Logical0Output Voltage I OUT e2mA00 4V V OL2Logical0Output Voltage I OUT e10m A00 1V I IL Input Leakage Current0s V IN s V CC b10 010 0m A I OL Output Leakage Current0s V IN s V CC b10 010 0m A I CC Active Supply Current I OUT e0 f(XIN)e2MHz T A e25 C811mAI CC Active Supply Current I OUT e0 f(XIN)e5MHz T A e25 C1015mA I CC Active Supply Current I OUT e0 f(XIN)e7MHz1521mAT A e25 CI CC Active Supply Current I OUT e0 f(XIN)e8MHz T A e25 C1521mAI Q Quiescent Current I OUT e0 PS e0 V IN e0or V IN e V CC25mAf(XIN)e0MHz T A e25 C X IN e0 CLK e1I PS Power-Save Current I OUT e0 PS e0 V IN e0or V IN e V CC57mAf(XIN)e5 0MHz T A e25C IN Input Capacitance610pF C OUT Output Capacitance812pF V CC Power Supply Voltage(Note2)2 456V Note1 Absolute Maximum Ratings indicate limits beyond which permanent damage may occur Continuous operation at these limits is not intended and should be limited to those conditions specified under DC Electrical CharacteristicsNote2 CPU operation at lower voltages will reduce the maximum operating speed Operation at voltages other than5V g10%is guaranteed by design not tested34 0AC Electrical Characteristics V CC e5V g10% GND e0V unless otherwise specifiedSymbol Parameter NSC800-1NSC800-3NSC800-35NSC800-4Units Notes Min Max Min Max Min Max Min Maxt X Period at XIN and XOUT5003333200333314233331253333nsPinsT Period at Clock Output10006667400666728466672506667ns(e2t X)t R Clock Rise Time1101109080ns Measured from10%–90%of signalt F Clock Fall Time70605550ns Measured from10%–90%of signalt L Clock Low Time4351509080ns50%duty cycle squarewave input on XINt H Clock High Time4501458575ns50%duty cycle squarewave input on XINt ACC(OP)ALE to Valid Data1340490340300ns Add t for each WAIT STATE t ACC(MR)ALE to Valid Data1875620405360ns Add t for each WAIT STATE t AFR AD(0–7)Float after0000nsRD Fallingt BABE BACK Rising to Bus1000400300250nsEnablet BABF BACK Falling to50505050nsBus Floatt BACL BACK Fall to CLK4251256055nsFallingt BRH BREQ Hold Time0000nst BRS BREQ Set-Up Time100505045nst CAF Clock Falling ALE070065060055nsFallingt CAR Clock Rising to ALE01000100090080nsRisingt CRD Clock Rising to100909080nsRead Risingt CRF Clock Rising to80707065nsRefresh Fallingt DAI ALE Falling to INTA4451609585nsFallingt DAR ALE Falling to40057516025010018090160nsRD Fallingt DAW ALE Falling to9001010350420225300200265nsWR Fallingt D(BACK)1ALE Falling to BACK2460975635560ns Add t for each WAIT state Falling Add t for opcode fetch cycles t D(BACK)2BREQ Rising to BACK5001610200700140540125475nsRisingt D(I)ALE Falling to INTR 1360475284250ns Add t for each WAIT state NMI RSTA-C PS Add t for opcode fetch cycles BREQ Inputs Validt DPA Rising PS to5001685200760140580125510ns See Figure14also Falling ALEt D(WAIT)ALE Falling to550250170125nsWAIT Input ValidOP Opcode FetchMR Memory Read44 0AC Electrical Characteristics V CC e5V g10% GND e0V unless otherwise specified(Continued)Symbol Parameter NSC800-1NSC800-3NSC800-35NSC800-4Units Notes Min Max Min Max Min Max Min MaxT H(ADH)1A(8–15)Hold Time During0000nsOpcode FetchT H(ADH)2A(8–15)Hold Time During4001008560nsMemory or IO RD and WRT H(ADL)AD(0–7)Hold Time100603530nsT H(WD)Write Data Hold Time4001008575nst INH Interrupt Hold Time0000nst INS Interrupt Set-Up Time100505045nst NMI Width of NMI Input50302520nst RDH Data Hold after Read0000nst RFLF RFSH Rising to ALE60504540nsFallingt RL(MR)RD Rising to ALE Rising3901005045ns(Memory Read)t S(AD)AD(0–7)Set-Up Time300454540nst S(ALE)A(8–15) SO SI IO M350705550nsSet-Up Timet S(WD)Write Data Set-Up Time385753530nst W(ALE)ALE Width430130115100nst WH WAIT Hold Time0000nst W(I)Width of INTR RSTA-C 500200140125nsPS BREQt W(INTA)INTA Strobe Width1000400225200ns Add two t states for firstINTA of each interruptresponse string Add t foreach WAIT statet WL WR Rising to ALE Rising4501307070nst W(RD)Read Strobe Width During960360210185ns Add t for each WAITState Add t 2for Memory Opcode FetchRead Cyclest W(RFSH)Refresh Strobe Width1925725450395nst WS WAIT Set-Up Time100706055nst W(WAIT)WAIT Input Width550250195175nst W(WR)Write Strobe Width985370250220ns Add t for each WAIT state t XCF XIN to Clock Falling251001595590580nst XCR XIN to Clock Rising25851585590580ns Note1 Test conditions t e1000ns for NSC800-1 400ns for NSC800 285ns for NSC800-35 250ns for NSC800-4Note2 Output timings are measured with a purely capacitive load of100pF55 0Timing WaveformsOpcode Fetch CycleTL C 5171–3Memory Read and Write CycleTL C 5171–465 0Timing Waveforms (Continued)Interrupt Power-Save CycleTL C 5171–5Note 1 This t state is the last t state of the last M cycle of any instruction Note 2 Response to INTR input Note 3 Response to PS inputBus Acknowledge CycleTL C 5171–6Waveform not drawn to proportion Use only for specifying test pointsAC Testing Input Output Waveform TL C 5171–7AC Testing Load CircuitTL C 5171–87NSC800HARDWARE6 0Pin Descriptions6 1INPUT SIGNALSReset Input(RESET IN) Active low Sets A(8–15)and AD (0–7)to TRI-STATE (high impedance) Clears the con-tents of PC I and R registers disables interrupts and acti-vates reset outBus Request(BREQ) Active low Used when another de-vice requests the system bus The NSC800recognizes BREQ at the end of the current machine cycle and sets A(8–15) AD(0–7) IO M RD and WR to the high imped-ance state RFSH is high during a bus request cycle The CPU acknowledges the bus request via the BACK output signalNon-Maskable Interrupt(NMI) Active low The non-mask-able interrupt generated by the peripheral device(s) is the highest priority interrupt The edge sensitive interrupt re-quires only a pulse to set an internal flip-flop which gener-ates the internal interrupt request The NMI flip-flop is moni-tored on the same clock edge as the other interrupts It must also meet the minimum set-up time spec for the inter-rupt to be accepted in the current machine instruction When the processor accepts the interrupt the flip-flop resets automatically Interrupt execution is independent of the in-terrupt enable flip-flop NMI execution results in saving the PC on the stack and automatic branching to restart address X’0066in memoryRestart Interrupts A B C(RSTA RSTB RSTC) Active low level sensitive The CPU recognizes restarts generated by the peripherals at the end of the current instruction if their respective interrupt enable and master enable bits are set Execution is identical to NMI except the interrupts vec-tor to the following restart addressesNameRestart Address(X’)NMI0066RSTA003CRSTB0034RSTC002CINTR(Mode1)0038The order of priority is fixed The list above starts with the highest priorityInterrupt Request(INTR) Active low level sensitive The CPU recognizes an interrupt request at the end of the cur-rent instruction provided that the interrupt enable and mas-ter interrupt enable bits are set INTR is the lowest priority interrupt Program control selects one of three response modes which determines the method of servicing INTR in conjunction with INTA See Interrupt ControlWait(WAIT) Active low When set low during RD WR or INTA machine cycles(during the WR machine cycle wait must be valid prior to write going active)the CPU extends its machine cycle in increments of t(wait)states The wait ma-chine cycle continues until the WAIT input returns high The wait strobe input will be accepted only during machine cycles that have RD WR or INTA strobes and during the machine cycle immediately after an interrupt has been ac-cepted by the CPU The later cycle has its RD strobe sup-pressed but it will still accept the waitPower-Save(PS) Active low PS is sampled during the last t state of the current instruction cycle When PS is low theCPU stops executing at the end of current instruction and keeps itself in the low-power mode Normal operation re-sumes when PS returns high(see Power Save Feature de-scription)CRYSTAL(X IN X OUT) X IN can be used as an external clock input A crystal can be connected across X IN and X OUT to provide a source for the system clock6 2OUTPUT SIGNALSBus Acknowledge(BACK) Active low BACK indicates to the bus requesting device that the CPU bus and its control signals are in the TRI-STATE mode The requesting device then commands the bus and its control signalsAddress Bits8–15 A(8–15) Active high These are the most significant8bits of the memory address during a memory instruction During an I O instruction the port ad-dress on the lower8address bits gets duplicated onto A(8–15) During a BREQ BACK cycle the A(8–15)bus is in theTRI-STATE modeReset Out(RESET OUT) Active high When RESET OUT is high it indicates the CPU is being reset This signal is normally used to reset the peripheral devicesInput Output Memory(IO M) An active high on the IO M output signifies that the current machine cycle is an input output cycle An active low on the IO M output signifies that the current machine cycle is a memory cycle It is TRI-STATE during BREQ BACK cyclesRefresh(RFSH) Active low The refresh output indicates that the dynamic RAM refresh cycle is in progress RFSH goes low during T3and T4states of all M1cycles During the refresh cycle AD(0–7)has the refresh address and A(8–15)indicates the interrupt vector register data RFSH is high during BREQ BACK cyclesAddress Latch Enable(ALE) Active high ALE is active only during the T1state of any M cycle and also T3state of the M1cycle The high to low transition of ALE indicates that a valid memory I O or refresh address is available on the AD(0–7)linesRead Strobe(RD) Active low The CPU receives data via the AD(0–7)lines on the trailing edge of the RD strobe The RD line is in the TRI-STATE mode during BREQ BACK cy-clesWrite Strobe(WR) Active low The CPU sends data via the AD(0–7)lines while the WR strobe is low The WR line is in the TRI-STATE mode during BREQ BACK cyclesClock(CLK) CLK is the output provided for use as a sys-tem clock The CLK output is a square wave at one half the input frequencyInterrupt Acknowledge(INTA) Active low This signal strobes the interrupt response vector from the interrupting peripheral devices onto the AD(0–7)lines INTA is active during the M1cycle immediately following the t state where the CPU recognized the INTR interrupt requestTwo of the three interrupt request modes use INTA In mode0one to four INTA signals strobe a one to four byte instruction onto the AD(0–7)lines In mode2one INTA sig-nal strobes the lower byte of an interrupt response vector onto the bus In mode1 INTA is inactive and the CPU re-sponse to INTR is the same as for an NMI or restart inter-rupt86 0Pin Descriptions(Continued)Status(SO S1) Bus status outputs provide encoded infor-mation regarding the current M cycle as followsMachine CycleStatus ControlS0S1IO M RD WR Opcode Fetch11001 Memory Read01001 Memory Write10010I O Read01101I O Write10110 Halt 00001 Internal Operation 01011 Acknowledge of Int 11011ALE is not suppressed in this cycleThis is the cycle that occurs immediately after the CPU accepts an inter-rupt(RSTA RSTB RSTC INTR NMI)Note1 During halt CPU continues to do dummy opcode fetch from location following the halt instruction with a halt status This is so CPU can continue to do its dynamic RAM refreshNote2 No early status is provided for interrupt or hardware restarts 6 3INPUT OUTPUT SIGNALSMultiplexed Address Data AD(0–7) Active high At RD Time Input data to CPUAt WR Time Output data from CPUAt Falling Edge Least significant byte of addressof ALE Time during memory reference cycle 8-bitport address during I O referencecycleDuring BREQ High impedanceBACK Cycle7 0Connection DiagramsDual-In-Line PackageTop ViewTL C 5171–10 Order Number NSC800D or N See NS Package D40C or N40AChip Carrier PackageTop ViewTL C 5171–11Order Number NSC800E or VSee NS Package E44B or V44A98 0Functional DescriptionThis section reviews the CPU architecture shown below fo-cusing on the functional aspects from a hardware perspec-tive including timing details As illustrated in Figure1 the NSC800is an8-bit parallel device The major functional blocks are the ALU register array interrupt control timing and control logic These areas are connected via the8-bit internal data bus Detailed de-scriptions of these blocks ae provided in the following sec-tionsTL C 5171–9 Note Applicable pinout for40-pindual-in-line package within parenthesesFIGURE1 NSC800CPU Functional Block Diagram108 0Functional Description(Continued)8 1REGISTER ARRAYThe NSC800register array is divided into two parts the dedicated registers and the working registers as shown in Figure2Main Reg Set Alternate Reg SetV W V W Accumulator Flags Accumulator FlagsA F A FB C B C WorkingD E D E Registers H L H L *Interrupt MemoryVector I Refresh RIndex Register IX DedicatedIndex Register IY RegistersStack Pointer SPProgram Counter PC–FIGURE2 NSC800Register Array8 2DEDICATED REGISTERSThere are6dedicated registers in the NSC800 two8-bit and four16-bit registers(see Figure3)Although their contents are under program control the pro-gram has no control over their operational functions unlike the CPU working registers The function of each dedicated register is described as followsCPU Dedicated RegistersProgram Counter PC(16)Stack Pointer SP(16)Index Register IX(16)Index Register IY(16)Interrupt Vector Register I(8)Memory Refresh Register R(8)FIGURE3 Dedicated Registers8 2 1Program Counter(PC)The program counter contains the16-bit address of the cur-rent instruction being fetched from memory The PC incre-ments after its contents have been transferred to the ad-dress lines When a program jump occurs the PC receives the new address which overrides the incrementerThere are many conditional and unconditional jumps calls and return instructions in the NSC800’s instruction reper-toire that allow easy manipulation of this register in control-ling the program execution(i e JP NZ nn JR Zd2 CALL NC nn)8 2 2Stack Pointer(SP)The16-bit stack pointer contains the address of the current top of stack that is located in external system RAM The stack is organized in a last-in first-out(LIFO)structure The pointer decrements before data is pushed onto the stack and increments after data is popped from the stackVarious operations store or retrieve data on the stack This along with the usage of subroutine calls and interrupts al-lows simple implementation of subroutine and interrupt nesting as well as alleviating many problems of data manip-ulation8 2 3Index Register(IX and IY)The NSC800contains two index registers to hold indepen-dent 16-bit base addresses used in the indexed addressing mode In this mode an index register either IX or IY con-tains a base address of an area in memory making it a point-er for data tablesIn all instructions employing indexed modes of operation another byte acts as a signed two’s complement displace-ment This addressing mode enables easy data table ma-nipulations8 2 4Interrupt Register(I)When the NSC800provides a Mode2response to INTR the action taken is an indirect call to the memory location containing the service routine address The pointer to the address of the service routine is formed by two bytes the high-byte is from the I Register and the low-byte is from the interrupting peripheral The peripheral always provides an even address for the lower byte(LSB e0) When the proc-essor receives the lower byte from the peripheral it concate-nates it in the following mannerI Register External byte8bits0uThe LSB of the external byte must be zeroFIGURE4a Interrupt RegisterThe even memory location contains the low-order byte the next consecutive location contains the high-order byte of the pointer to the beginning address of the interrupt service routine8 2 5Refresh Register(R)For systems that use dynamic memories rather than static RAM’s the NSC800provides an integral8-bit memory re-fresh counter The contents of the register are incremented after each opcode fetch and are sent out on the lower por-tion of the address bus along with a refresh control signal This provides a totally transparent refresh cycle and does not slow down CPU operationThe program can read and write to the R register although this is usually done only for test purposes118 0Functional Description(Continued)8 3CPU WORKING AND ALTERNATE REGISTER SETS 8 3 1CPU Working RegistersThe portion of the register array shown in Figure4b repre-sents the CPU working registers These sixteen8-bit regis-ters are general-purpose registers because they perform a multitude of functions depending on the instruction being executed They are grouped together also due to the types of instructions that use them particularly alternate set oper-ationsThe F(flag)register is a special-purpose register because its contents are more a result of machine status rather than program data The F register is included because of its inter-action with the A register and its manipulations in the alter-nate register set operations8 3 2Alternate RegistersThe NSC800registers designated as CPU working registers have one common feature the existence of a duplicate reg-ister in an alternate register set This architectural concept simplifies programming during operations such as interrupt response when the machine status represented by the con-tents of the registers must be savedThe alternate register concept makes one set of registers available to the programmer at any given time Two instruc-tions(EX AF A‘F’and EXX) exchange the current working set of registers with their alternate set One exchange be-tween the A and F registers and their respective duplicates (A’and F’)saves the primary status information contained in the accumulator and the flag register The second exchange instruction performs the exchange between the remaining registers B C D E H and L and their respective alter-nates B’ C’ D’ E’ H’ and L’ This essentially saves the contents of the original complement of registers while pro-viding the programmer with a usable alternate setCPU Main Working Register SetAccumulator A(8)Flags F(8)Register B(8)Register C(8)Register D(8)Register E(8)Register H(8)Register L(8)CPU Alternate Working Register SetAccumulator A’(8)Flags F’(8)Register B’(8)Register C’(8)Register D’(8)Register E’(8)Register H’(8)Register L’(8)FIGURE4b CPU Working and Alternate Registers8 4REGISTER FUNCTIONS8 4 1Accumulator(A Register)The A register serves as a source or destination register for data manipulation instructions In addition it serves as the accumulator for the results of8-bit arithmetic and logic op-erationsThe A register also has a special status in some types of operations that is certain addressing modes are reserved for the A register only although the function is available for all the other registers For example any register can be loaded by immediate register indirect or indexed address-ing modes The A register however can also be loaded via an additional register indirect addressingAnother special feature of the A register is that it produces more efficient memory coding than equivalent instruction functions directed to other registers Any register can be rotated however while it requires a two-byte instruction to normally rotate any register a single-byte instruction is available for rotating the contents of the accumulator(A reg-ister)8 4 2F Register-FlagsThe NSC800flag register consists of six status bits that contain information regarding the results of previous CPU operations The register can be read by pushing the con-tents onto the stack and then reading it however it cannot be written to It is classified as a register because of its affiliation with the accumulator and the existence of a dupli-cate register for use in exchange instructions with the accu-mulatorOf the six flags shown in Figure5 only four can be directly tested by the programmer via conditional jump call and return instructions They are the Sign(S) Zero(Z) Parity Overflow(P V) and Carry(C)flags The Half Carry(H)and Add Subtract(N)flags are used for internal operations re-lated to BCD arithmeticTL C 5171–23FIGURE5 Flag Register128 0Functional Description(Continued)8 4 3Carry(C)A carry from the highest order bit of the accumulator during an add instruction or a borrow generated during a subtrac-tion instruction sets the carry flag Specific shift and rotate instructions also affect this bitTwo specific instructions in the NSC800instruction reper-toire set(SCF)or complement(CCF)the carry flagOther operations that affect the C flag are as followsAddsSubtractsLogic Operations(always resets C flag)Rotate AccumulatorRotate and ShiftsDecimal AdjustNegation of AccumulatorOther operations do not affect the C flag8 4 4Adds Subtract(N)This flag is used in conjunction with the H flag to ensure that the proper BCD correction algorithm is used during the deci-mal adjust instruction(DAA) The correction algorithm de-pends on whether an add or subtract was previously done with BCD operandsThe operations that set the N flag areSubtractionsDecrements(8-bit)Complementing of the AccumulatorBlock I OBlock SearchesNegation of the AccumulatorThe operations that reset the N flag areAddsIncrementsLogic OperationsRotatesSet and Complement CarryInput Register IndirectBlock TransfersLoad of the I or R RegistersBit TestsOther operations do not affect the N flag8 4 5Parity Overflow(P V)The Parity Overflow flag is a dual-purpose flag that indi-cates results of logic and arithmetic operations In logic op-erations the P V flag indicates the parity of the result the flag is set(high)if the result is even reset(low)if the result is odd In arithmetic operations it represents an overflow condition when the result interpreted as signed two’s com-plement arithmetic is out of range for the eight-bit accumu-lator(i e b128to a127)The following operations affect the P V flag according to the parity of the result of the operationLogic OperationsRotate and ShiftRotate DigitsDecimal AdjustInput Register IndirectThe following operations affect the P V flag according to the overflow result of the operationAdds(16bit with carry 8-bit with without carry)Subtracts(16bit with carry 8-bit with without carry)Increments and DecrementsNegation of AccumulatorThe P V flag has no significance immediately after the fol-lowing operationsBlock I OBit TestsIn block transfers and compares the P V flag indicates the status of the BC register always ending in the reset state after an auto repeat of a block move Other operations do not affect the P V flag8 4 6Half Carry(H)This flag indicates a BCD carry or borrow result from the low-order four bits of operation It can be used to correct the results of a previously packed decimal add or subtract op-eration by use of the Decimal Adjust Instruction(DAA)The following operations affect the H flagAdds(8-bit)Subtracts(8-bit)Increments and DecrementsDecimal AdjustNegation of AccumulatorAlways Set by Logic ANDComplement AccumulatorBit TestingAlways Reset By Logic OR’s and XOR’sRotates and ShiftsSet CarryInput Register IndirectBlock TransfersLoads of I and R Registers The H flag has no significance immediately after the follow-ing operations16-bit Adds with without carry16-Bit Subtracts with carryComplement of the carryBlock I OBlock SearchesOther operations do not affect the H flag13。

General DescriptionThe MAX200–MAX211/MAX213 transceivers are designed for RS-232 and V.28 communication inter-faces where ±12V supplies are not available. On-board charge pumps convert the +5V input to the ±10V need-ed for RS-232 output levels. The MAX201 and MAX209operate from +5V and +12V, and contain a +12V to -12V charge-pump voltage converter.The MAX200–MAX211/MAX213 drivers and receivers meet all EIA/TIA-232E and CCITT V.28 specifications at a data rate of 20kbps. The drivers maintain the ±5V EIA/TIA-232E output signal levels at data rates in excess of 120kbps when loaded in accordance with the EIA/TIA-232E specification.The 5µW shutdown mode of the MAX200, MAX205,MAX206, and MAX211 conserves energy in battery-powered systems. The MAX213 has an active-low shut-down and an active-high receiver enable control. Two receivers of the MAX213 are active, allowing ring indica-tor (RI) to be monitored easily using only 75µW power.The MAX211 and MAX213 are available in a 28-pin wide small-outline (SO) package and a 28-pin shrink small-outline (SSOP) package, which occupies only 40% of the area of the SO. The MAX207 is now avail-able in a 24-pin SO package and a 24-pin SSOP. The MAX203 and MAX205 use no external components,and are recommended for applications with limited circuit board space.ApplicationsComputersLaptops, Palmtops, Notebooks Battery-Powered Equipment Hand-Held Equipment Next-Generation Device Features ♦For Low-Cost Applications:MAX221E: ±15kV ESD-Protected, +5V, 1µA, Single RS-232 Transceiver with AutoShutdown™♦For Low-Voltage and Space-Constrained Applications:MAX3222E/MAX3232E/MAX3237E/MAX3241E/MAX3246E: ±15kV ESD-Protected, Down to 10nA,+3.0V to +5.5V, Up to 1Mbps, True RS-232Transceivers (MAX3246E Available in UCSP™Package)♦For Space-Constrained Applications:MAX3228E/MAX3229E: ±15kV ESD-Protected,+2.5V to +5.5V, RS-232 Transceivers in UCSP ♦For Low-Voltage or Data Cable Applications:MAX3380E/MAX3381E: +2.35V TO +5.5V, 1µA,2Tx/2Rx RS-232 Transceivers with ±15kV ESD-Protected I/O and Logic Pins ♦For Low-Power Applications:MAX3224E–MAX3227E/MAX3244E/MAX3245E:±15kV ESD-Protected, 1µA, 1Mbps, +3.0V to+5.5V, RS-232 Transceivers with AutoShutdown Plus™MAX200–MAX211/MAX213+5V , RS-232 Transceivers with 0.1µF External Capacitors ________________________________________________________________Maxim Integrated Products 119-0065; Rev 6; 10/03For pricing, delivery, and ordering information,please contact Maxim/Dallas Direct!at 1-888-629-4642, or visit Maxim’s website at .Ordering Information appears at end of data sheetAutoShutdown, AutoShutdown Plus, and UCSP are trademarks of Maxim Integrated Products, Inc.MAX200–MAX211/MAX213+5V , RS-232 Transceiverswith 0.1µF External Capacitors______________________________________________________________________________________19Ordering Information*Contact factory for dice specifications.M A X 200–M A X 211/M A X 213+5V , RS-232 Transceiverswith 0.1µF External Capacitors Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.20____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600©2003 Maxim Integrated ProductsPrinted USAis a registered trademark of Maxim Integrated Products.Package Information(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,go to /packages .)。

BU208ABU508A/BU508AFIHIGH VOLTAGE FAST-SWITCHINGNPN POWER TRANSISTORSsSTMicroelectronics PREFERRED SALESTYPESs HIGH VOLTAGE CAPABILITY (> 1500 V) sFULLY INSULATED PACKAGE (PLIANT) FOR EASY MOUNTINGAPPLICATIONS:s HORIZONTAL DEFLECTION FOR COLOUR TVDESCRIPTION The BU208A, BU508A and BU508AFI are manufactured using Multiepitaxial Mesa technology for cost-effective high performance and use a Hollow Emitter structure to enhance switching speeds.April 2002 ABSOLUTE MAXIMUM RATINGS®1/8r o d u c t (s ) - s o l e t e P r o d u c t (s ) -r o d u c t (s ) - O b s o THERMAL DATAELECTRICAL CHARACTERISTICS (T case = 25 o C unless otherwise specified)Safe Operating Area (TO-3)Safe Operating Areas (TO-218/ISOWATT218)BU208A / BU508A / BU508AFIs o l e t e P r o d u c t (sOb s o l e t e P - O b s o l e t e P r o d uc t(s )Derating Curves (TO-3)DC Current GainBase Emitter Saturation VoltageDerating Curves (TO-218/ISOWATT218)Collector Emitter Saturation VoltageSwitching Time Inductive LoadBU208A / BU508A / BU508AFIO b s - O b s o l e t e P r o d u c t (s )Ob s o l e t e Pt (s ) Figure 1:Inductive Load Switching Test Circuit.Switching Time Inductive LoadBU208A / BU508A / BU508AFIO b s P r o d u c t (s )BU208A / BU508A / BU508AFIBU208A / BU508A / BU508AFIBU208A / BU508A / BU508AFIOb s o l e t e P r o d uc t (s ) - O b s o l e t e P r od u c t (s ) Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.The ST logo is a trademark of STMicroelectronics© 2002 STMicroelectronics – Printed in Italy – All Rights ReservedSTMicroelectronics GROUP OF COMPANIESAustralia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.BU208A / BU508A / BU508AFIO b s o l e t e P r o d u c t (s ) - O b s o l e t e P r o d u c t (s )分销商库存信息:STMBU208A BU508A BU508AFI。

一 设备树结构说明二 设备树目录对应的菜单项及工具栏2.1 根目录及一级子目录（AMP ‐204C 子目录）2.1.1 对应菜单1、Initial Options 菜单项2、About 菜单项该菜单项用于获取MCPRO2版本信息、数据库版本信息及MCPRO2所支持的产品信息等等。

3、根目录右键菜单当选择ADLINK 根目录，右键点击，弹出保存/载入所有参数菜单，如下所示2.2 二级子目录（Card No 0子目录）2.2.1对应菜单及工具栏当选中相应的卡ID 目录（例如Card No 0），会弹出如下DIO 和DSP 操作菜单及工具栏2.2.2 右键菜单当选中相应的卡ID2.3 三级子目录（Motion 子目录）2.3.1对应工具栏2.3.2对应菜单栏2.3.3 右键菜单当选中相应卡ID 目录（例如Card No 0）下的Motion ，右击 会弹出如下右键菜单ServoOn 该卡下面的所有轴ServoOff 该卡下面的所有轴2.4 末级子目录（单轴操作子目录）2.4.1对应工具栏当选中相应的轴号时，会弹出如下工具栏2.4.2对应菜单栏2.4.3 右键菜单三 MCPRO2操作3.1 设置向导（SetupWizard ）选择要操作的轴，在工具栏点击SetupWizard 按钮，弹出SetupWizard 对话框。

如下图示。

Step 1：Control Mode （控制模式）该步骤用于设置板卡控制模式及伺服更新率。

但是为防止客户误操作，控制模式设置和伺服更新率设置被移出该步骤。

如果要设置，请参考下面的设置。

1、选择要操作的轴2、点击SetupWizard按钮3、弹出SetupWizard对话框1、更改控制模式：注意：请根据每个轴使用的电机类型来设置每个轴的控制模式，控制模式一旦设定，请勿随意变更。

1、先选择Motion 子目录点击此按钮保存设置2、设置伺服更新率：以下两种方式都可以设置伺服更新率： 方式1：方式2：注意：如非必要，请勿随意更改伺服更新率。