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ispXPGA FamilyMarch 2003Preliminary Data SheetTM© 2003 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at /legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The speci fications and information herein are subject to change without notice.■Non-volatile, In finitely Recon figurable•Instant-on - Powers up in microseconds via on-chip E 2CMOS ® based memory •No external con figuration memory•Excellent design security , no bit stream to intercept •Recon figure SRAM based logic in milliseconds■High Logic Density for System-levelIntegration•139K to 1.25M system gates •160 to 496 I/O•1.8V , 2.5V , and 3.3V V CC operation•Up to 414Kb sysMEM™ embedded memory■High Performance Programmable FunctionUnit (PFU)•Four LUT -4 per PFU supports wide and narrow functions•Dual flip-flops per LUT -4 for extensive pipelining •Dedicated logic for adders, multipliers, multiplex-ers, and counters■Variable-Length Interconnect RoutingTechnology•Optimum speed, power, and flexibility for logic interconnections■ Flexible Memory Resources•Multiple sysMEM Embedded RAM Blocks–Single port, Dual port, and FIFO operation •64-bit distributed memory in each PFU–Single port, Double port, FIFO, and Shift Register operation■ Eight sysCLOCK™ Phase Locked Loops(PLLs) for Clock Management•T rue PLL technology•10MHz to 320MHz operation •Clock multiplication and division •Phase adjustment•Shift clocks in 250ps steps■ sysIO™ for High System Performance•High speed memory support through SSTL and HSTL•Advanced buses supported through PCI, GTL+, LVDS, BLVDS, and LVPECL•Standard logic supported through LVTTL, LVCMOS 3.3, 2.5, and 1.8•Programmable drive strength for series termination •Programmable bus maintenance■ sysHSI™ Capability for Ultra Fast SerialCommunications•Up to 850Mbps performance •Up to 20 channels per device•Built in Clock Data Recovery (CDR) and Serialization and De-serialization (SERDES)■ Flexible Programming, Recon figuration,and Testing•IEEE 1532 and 1149.1 compliant•Microprocessor con figuration interface•Program E 2 CMOS while operating from SRAMTable 1. ispXPGA Family Selection GuideispXPGA 125ispXPGA 200ispXPGA 500ispXPGA 1200System Gates 139K 210K 476K 1.25M PFUs 48467617643844LUT -4s 19362704705615376Logic FFs 3.8K 5.4K 14.1K 30.7K sysMEM Memory 92K 111K 184K 414K Distributed Memory 30K 43K 112K 246K EBR20244090sysHSI Channels 481220User I/O 160/176160/208336496Packaging256 fpBGA 516 fpBGA 1256 fpBGA 516 fpBGA 1516 fpBGA 1 900 fpBGA680 fpSBGA 1 900 fpBGA1.Thermally enhanced package.Note: LFX1200B/C is preliminary, LFX125/200/500B/C information is advanced.Lattice Semiconductor ispXPGA Family Data SheetispXPGA Family OverviewThe ispXPGA family of devices allows the creation of high-performance logic designs that are both non-volatile andinfinitely re-programmable. Other FPGA solutions force a compromise being either re-programmable or non-vola-tile. This family couples this capability with a mainstream architecture containing the features required for today’ssystem-level design.Electrically Erasable CMOS (E2CMOS) memory cells provide the ispXPGA family with non-volatile capability.These allow logic to be functional microseconds after power is applied, allowing easy interfacing in many applica-tions. This capability also means that expensive external configuration memories are not required and that designs can be secured from unauthorized read back. Internal SRAM cells allow the device to be infinitely reconfigured if desired. Both the SRAM and E2CMOS cells can be programmed and verified through the IEEE 1532 industry stan-dard. Additionally, the SRAM cells can be configured and read-back through the sysCONFIG™ peripheral port.The family spans the density and I/O range required for the majority of today’s logic designs, 139K to 1.25M systemgates and 160 to 496 I/O. The devices are available for operation from 1.8V, 2.5V, and 3.3V power supplies, provid-ing easy integration into the overall system.The system-level needs of designers are met through the incorporation of sysMEM dual-port memory blocks,sysIO advanced I/O support, and sysCLOCK Phase Locked Loops (PLLs). High-speed serial communications aresupported through multiple sysHSI blocks, which provide clock data recovery (CDR) and serialization/de-serializa-tion (SERDES).The ispLEVER™ design tool from Lattice allows designers easy implementation of designs using the ispXPGAproduct. Synthesis library support is available for the major logic synthesis tools. The ispLEVER tool takes the out-put from these common synthesis packages and place and routes the design in the ispXPGA product. The toolallows floor planning and the management of other constraints within the device. The tool also provides outputs tocommon timing analysis tools for timing analysis.T o increase designer productivity, Lattice provides a variety of pre-designed modules referred to as IP cores for theispXPGA product. These IP cores allow designers to concentrate on the unique portions of their design while usingpre-designed block to implement standard functions such as bus-interfaces, standard communication-interfaces,and memory-controllers.Through the use of advanced technology and innovative architecture the ispXPGA FPGA devices provide design-ers with excellent speed performance. Although design dependent, many typical designs can run at over 150MHz.Certain designs can run at over 300MHz. T able 2 details the performance of several building blocks commonlyused by logic designers.Table 2. ispXPGA Speed Performance for Typical Building BlocksFunction Performance8:1 Asynch MUX150 MHz1:32 Asynch Demultiplexer125 MHz8 x 8 2-LL Piped Multiplier225 MHz32-bit Up/Down Counter290 MHz32-bit Shift Register360 MHzLattice Semiconductor ispXPGA Family Data SheetArchitecture OverviewThe ispXPGA architecture is a symmetrical architecture consisting of an array of Programmable Function Units(PFUs) enclosed by Input Output Groups (PICs) with columns of sysMEM Embedded Block RAMs (EBRs) distrib-uted throughout the array. Figure 1 illustrates the ispXPGA architecture. Each PIC has two corresponding sysIOblocks, each of which includes one input and output buffer. On two sides of the device, between the PICs and thesysIO blocks, there are sysHSI High-Speed Interface blocks. The symmetrical architecture allows designers to eas-ily implement their designs, since any logic function can be placed in any section of the device.The PFUs contain the basic building blocks to create logic, memory, arithmetic, and register functions. They areoptimized for speed and flexibility allowing complex designs to be implemented quickly and efficiently.The PICs interface the PFUs and EBRs to the external pins of the device. They allow the signals to be registeredquickly to minimize setup times for high-speed designs. They also allow connections directly to the different logicelements for fast access to combinatorial functions.The sysMEM EBRs are large, fast memory elements that can be configured as RAM, ROM, FIFO, and other stor-age types. They are designed to facilitate both single and dual-port memory for high-speed applications.These three components of the architecture are interconnected via a high-speed, flexible routing array. The routing array consists of Variable Length Interconnect (VLI) lines between the PICs, PFUs, and EBRs. There is additionalrouting available to the PFU for feedback and direct routing of signals to adjacent PFUs or PICs.The sysIO blocks consist of configurable input and output buffers connected directly to the PICs. These buffers canbe configured to interface with 16 different I/O standards. This allows ispXPGA to interface with other devices with-out the need for external transceivers.The sysHSI blocks provide the necessary components to allow the ispXPGA device to transfer data at up to850Mbps using the LVDS standard. These components include serializing, de-serializing, and clock data recovery(CDR) logic.The sysCLOCK blocks provide clock multiplication/division, clock distribution, delay compensation, and increasedperformance through the use of PLL circuitry that manipulates the global clocks. There is one sysCLOCK block foreach global clock tree in the device.Lattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice SemiconductorispXPGA Family Data SheetTable 5. ispXPGA Supported I/O StandardsTable 6. Differential Interface Standard Support 1sysIO StandardV CCO V REF V TT LVTTL 3.3V N/A N/A LVCMOS-3.3 3.3V N/A N/A LVCMOS-2.5 2.5V N/A N/A LVCMOS-1.8 1.8V N/A N/A PCI 3.3V N/A N/A AGP-1X3.3V N/A N/A SSTL3, Class I, II 3.3V 1.5V 1.5V SSTL2, Class I, II 2.5V 1.25V 1.25V HSTL, Class I 1.5V 0.75V 0.75V HSTL, Class III 1.5V 0.9V 1.5V GTL+N/A 1.0V 1.5V LVPECL 3.3V N/A N/A LVDS 1 2.5V N/A N/A BLVDS2.5VN/AN/A1.V CCO must be2.5V for high speed serial operations (sysHSI block).sysIO Buffer Not Using sysHSI BlocksysIO Buffer Using sysHSI Block LVDS Driver Supported with external resistor network SupportedReceiver Supported with standard termination Supported with standard termination BLVDS Driver Supported with external resistor network Not supportedReceiver Supported (may need termination)Supported (may need termination)LVPECLDriver Supported with external resistor network Not supportedReceiverSupported with terminationSupported with termination1.For more information, refer to Lattice technical note TN1000, sysIO Usage Guidelines,available at .Lattice Semiconductor ispXPGA Family Data SheetTable 7. sysHSI Block REFCLK Selections1sysHSI Block Available Global Clock Nets0CLK0, CLK1, CLK2, CLK31CLK0, CLK1, CLK2, CLK42CLK0, CLK1, CLK2, CLK53CLK0, CLK1, CLK3, CLK64CLK0, CLK1, CLK3, CLK75CLK0, CLK3, CLK5, CLK76CLK0, CLK2, CLK5, CLK77CLK0, CLK1, CLK5, CLK68CLK0, CLK5, CLK69CLK0, CLK5, CLK6, CLK71.T able 6 applies to all devices. Ignore sysHSI blocks not availablein a specific device.Configuration and ProgrammingThe ispXPGA family of devices takes a unique approach to FPGA configuration memory. It contains two types of memory, Static RAM and non-volatile E2CMOS cells. The static RAM is used to control the functionality of the device during normal operation and the E2CMOS memory cells are used to load the SRAM. The E2CMOS memory module can be thought of as the hard drive for the ispXPGA configuration and the SRAM as the working configura-tion memory. There is a one-to-one relationship between SRAM memory and the E2CMOS cells. The SRAM can be configured either from the E2CMOS memory or from an external source, as shown in Figure 21.Figure 21 shows the different ports and modes that are used in the configuration and programming of the ispXPGA devices. There are two possible ports that can be used for configuration of the SRAM memory: the ISP port which is compliant to the IEEE 1149.1 T est Access Port (T AP) Std. and the ISP port which accommodates bit-wide config-uration. The sysCONFIG port allows byte-wide configuration of the SRAM configuration memory. When program-ming the E2CMOS memory, only the 1149.1 T AP can be used.Configuration and programming done through the 1149.1 T est Access Port (T AP) are fully compliant to both the IEEE Std. 1149.1 Boundary Scan T AP specification and the IEEE Std. 1532 In-System Configuration specification. T o configure or program the device using the 1149.1 T AP the device must be in the ISP mode. T o configure the SRAM memory using the sysCONFIG Port, the device must be in the sysCONFIG mode. Upon power-up, the device’s SRAM memory can be configured either from the E2CMOS memory or from an external source through the sysCONFIG mode. Additionally, the SRAM can be re-configured from the E2CMOS memory by executing a “REFRESH.” See Lattice technical note number TN1026, is pXP Configuration Us age Guide, for more in depth information on the different programming modes, timing and wake-up, available at .Absolute Maximum Ratings 1, 2, 31.8V2.5V/3.3VSupply Voltage (V CC ). . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.5V . . . . . . . . . .-0.5 to 5.5V PLL Supply Voltage (V CCP ) . . . . . . . . . . . . . . . . . -0.5 to 2.5V . . . . . . . . . .-0.5 to 5.5V Output Supply Voltage (V CCO ). . . . . . . . . . . . . . . -0.5 to 4.5V . . . . . . . . . .-0.5 to 4.5V IEEE 1149.1 T AP Supply Voltage (V CCJ ). . . . . . . -0.5 to 4.5V . . . . . . . . . .-0.5 to 4.5V Input Voltage Applied 4 . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V . . . . . . . . . .-0.5 to 4.5V Storage T emperature . . . . . . . . . . . . . . . . . . . . . .-65 to 150°C. . . . . . . . . -65 to 150°C Junction T emperature (T J ) with Power Applied . .-55 to 150°C. . . . . . . . . -55 to 150°C1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci fication is not implied (while programming, following the programming speci fications).2. Compliance with the Lattice Thermal Management technical note is required.3. All voltages referenced to GND.4. Overshoot and undershoot of -2V to (V IH (MAX) + 2) volts is permitted for a duration of <20nsRecommended Operating ConditionsE 2CMOS Erase Reprogram Speci ficationsHot Socketing Characteristics 1, 2, 3, 4SymbolParameterMin Max Units V CCSupply Voltage for 1.8V device1.65 1.95V Supply Voltage for2.5V device 2.3 2.7V Supply Voltage for3.3V device3.0 3.6V V CCPSupply Voltage for PLL block for 1.8V device1.65 1.95V Supply Voltage for PLL block for2.5V device 2.3 2.7V Supply Voltage for PLL block for3.3V device3.0 3.6V V CCJ Supply Voltage for IEEE 1149.1 T est Access Port for LVCMOS 1.8V1.65 1.95V Supply Voltage for IEEE 1149.1 T est Access Port for LVCMOS2.5V 2.3 2.7V Supply Voltage for IEEE 1149.1 T est Access Port for LVCMOS3.3V 3.0 3.6V T J (COM)Junction T emperature Commercial Operation 085C T J (IND)Junction T emperature Industrial Operation-40105CParameterMin Max Units Erase/Reprogram Cycle 11,000—Cycles1.Valid over commercial temperature range.Symbol ParameterConditionMin Typ Max Units I DKInput or I/O Leakage Current0 ≤ V IN ≤ 3.0V—+/-50+/-800µA1. Insensitive to sequence of V CC and V CCO . However, assumes monotonic rise / fall rates for V CC and V CCO .2. LVTTL, LVCMOS only3. 0 < V CC ≤ V CC (MAX), 0 < V CCO ≤ V CCO (MAX)4.I DK is additive to I PU , I PD or I BH . Device defaults to pull-up until fuse circuitry is active.DC Electrical CharacteristicsOver Recommended Operating ConditionsSupply CurrentOver Recommended Operating ConditionsSymbol ParameterConditionMin Typ Max Units I IL , I IH 1Input or I/O Low Leakage 0 ≤ V IN < (V CCO - 0.2V)——10µA (V CCO - 0.2V) ≤ V IN ≤ 3.6V ——40µA I PU I/O Active Pull-up Current 0 ≤ V IN ≤ 0.7 V CCO30—150µA I PD I/O Active Pull-down CurrentV IL (MAX) ≤ V IN ≤ V IH (MAX)30—150µA I BHLS Bus Hold Low Sustaining Current V IN = V IL (MAX)30——µA I BHHS Bus Hold High Sustaining Current V IN = 0.7 V CCO 30——µA I BHLO Bus Hold Low Overdrive Current 0 ≤ V IN ≤ V IH (MAX)——150µA I BHHO Bus Hold High Overdrive Current 0 ≤ V IN ≤ V IH (MAX)——150µA V BHT Bus Hold T rip Points V CCO * 0.35—V CCO * 0.65V C 1I/O Capacitance 2V CCO = 3.3V , 2.5V , 1.8V—8—pf V CC = 1.8V , V IO = 0 to V IH (MAX) ——C 2Clock Capacitance 2V CCO = 3.3V , 2.5V , 1.8V—6—pf V CC = 1.8V , V IO = 0 to V IH (MAX) ——C 3Global Input Capacitance 2V CCO = 3.3V , 2.5V , 1.8V—6—pfV CC = 1.8V , V IO = 0 to V IH (MAX)——1.Input or I/O leakage current is measured with the pin con figured as an input or as an I/O with the output driver tri-stated. It is not measured with the output driver active. Bus maintenance circuits are disabled.2.T A = 25°C, f = 1.0MHz.Symbol ParameterCondition Min Typ Max Units I CC 1, 2Standby Core Operating Power Supply CurrentV CC = 3.3V —220—mA V CC = 2.5V —220—mA V CC = 1.8V —200—mA I CCO 3Standby Output Power Supply CurrentV CCO = 3.3V— 2.0—mA V CCO = 2.5V — 2.0—mA V CCO = 1.8V — 2.0—mA V CCO = 1.5V — 2.0—mA I CCP 4Standby PLL Operating Supply CurrentV CCP = 3.3V—17.0—mA V CCP = 2.5V —17.0—mA V CCP = 1.8V —15.0—mA I CCJ 5Standby IEEE 1149.1 T AP Power Supply CurrentV CCJ = 3.3V— 2.0—mA V CCJ = 2.5V — 1.5—mA V CCJ = 1.8V—1.0—mA1.T A = 25˚C, frequency = 1.0 MHz, device con figured with 16-bit counters.2.I CC varies with speci fic device con figuration and operating frequency. For more accurate power calculation use the ispXPGA Power Estimator.3.T A = 25˚C, per bank, no DC load, frequency = 0 MHz.4.T A = 25˚C, per PLL, frequency = 10 MHz.5.T A = 25˚CsysIO Differential Standards DC Electrical CharacteristicsParameter Description Test Conditions Min.Typ.Max. LVDS1V INP, V INM Input voltage 0V— 2.4V V THD Differential input threshold+/-100mV——V CM Input Common Mode voltage Half the sum of the two inputs 0.05V— 2.35V I IN Input current Power on or Power off ——+/-10uA V OH Output High Voltage for V OP or V OM RT = 100 Ohm— 1.38V 1.60V V OL Output Low Voltage for V OP or V OM RT = 100 Ohm0.9V 1.03V—V OD Output Voltage Differential|V OP - V OM|, R T = 100 ohm250mV350mV450mV ∆V OD Change in V OD between high and low——50mVV OS Output Voltage Offset|V OP + V OM|/2, R T = 100 ohm 1.125V 1.25V 1.375V ∆V OS Change in V OS between H and L——50mV——24mA I OSD Output short circuit current V OD = 0V Driver outputsshortedBLVDS1V INP, V INM Input voltage 0V— 2.4V V THD Differential input threshold+/-100mV——V CM Input Common Mode voltage Half the sum of the two inputs 0.05V— 2.35V I IN Input current Power on or Power off ——+/-10uA V OH Output High Voltage for V OP or V OM R T = 27Ω— 1.4V 1.80V V OL Output Low Voltage for V OP or V OM R T = 27Ω0.95V 1.1V—V OD Output Voltage Differential|V OP - V OM|, RT = 27Ω240mV300mV460mV ∆V OD Change in V OD Between H and L27mV V OS Output Voltage Offset|V OP + V OM| /2, RT = 27Ω 1.1V 1.3V 1.5V ∆V OS Change in V OS Between H and L27mVI OSD Output Short Circuit Current V OD = 0. Driver Outputs36mA65mAShorted.1.V OP and V OM are the two outputs of the LVDS/BLVDS output buffer.LVPECL1DCParameter Parameter Description Min.Max.Min.Max.Min.Max.Units V CCO 3.0 3.3 3.6V V IH Input Voltage High 1.49 2.72 1.49 2.72 1.49 2.72V V IL Input Voltage Low0.86 2.1250.86 2.1250.86 2.125V V OH Output Voltage High 1.8 2.11 1.92 2.28 2.13 2.41V V OL Output Voltage Low0.96 1.27 1.06 1.43 1.3 1.57V V DIFF Differential Input voltage0.3—0.3—0.3—V 1.These values are valid at the output of the source termination pack as shown above with 100-ohm differential load only (see Figure 22). The V OH levels are 200mV below the standard LVPECL levels and are compatible with devices tolerant of the lower common mode ranges.ispXPGA PFU Timing ParametersOver Recommended Operating ConditionsParameter Description-4-3Units Min.Max.Min.Max.Functional DelaysLUTst LUT44-Input LUT Delay—0.44—0.51ns t LUT55-Input LUT Delay—0.79—0.91ns t LUT66-Input LUT Delay—0.93— 1.07ns Shift Register (LUT)t LSR_S Shift Register Setup Time-0.62—-0.53—ns t LSR_H Shift Register Hold Time0.63—0.72—ns t LSR_CO Shift Register Clock to Output Delay—0.75—0.86ns Arithmetic Functionst LCTHRUR MC (Macro Cell) Carry In to MC Carry Out Delay (Rip-ple)—0.09—0.10ns t LCTHRUL1MC Carry In to MC Carry Out Delay (Look Ahead)—0.05—0.06ns t LSTHRU MC Sum In to MC Sum Out Delay—0.45—0.52ns t LSINCOUT MC Sum In to MC Carry Out Delay—0.31—0.36ns t LCINSOUTR MC Carry In to MC Sum Out Delay (Ripple)—0.39—0.45ns t LCINSOUTL MC Carry In to MC Sum Out Delay (Look Ahead)—0.28—0.32ns Feed-thrut LFT PFU Feed-Thru Delay—0.16—0.18ns Distributed RAMt LRAM_CO Clock to RAM Output— 1.33— 1.53ns t LRAMAD_S Address Setup Time-0.40—-0.34—ns t LRAMD_S Data Setup Time0.22—0.25—ns t LRAMWE_S Write Enable Setup Time0.46—0.53—ns t LRAMAD_H Address Hold Time0.60—0.69—ns t LRAMD_H Data Hold Time0.11—0.13—ns t LRAMWE_H Write Enable Hold Time0.12—0.14—ns t LRAMCPW Clock Pulse Width (High or Low) 3.00— 3.45—ns t LRAMADO Address to Output Delay—0.93— 1.07ns Register/Latch DelaysRegisterst L_CO Register Clock to Output Delay—0.62—0.71ns t L_S Register Setup Time (Data before Clock)0.14—0.16—ns t L_H Register Hold Time (Data after Clock)-0.12—-0.10—ns t LCE_S Register Clock Enable Setup Time-0.11—-0.09—ns t LCE_H Register Clock Enable Hold Time0.11—0.13—ns Latchest L_GO Latch Gate to Output Delay—0.10—0.12ns t LL_S Latch Setup Time0.14—0.16—ns t LL_H Latch Hold Time-0.12—-0.10—ns t LLPD Latch Propagation Delay (T ransparent Mode)—0.10—0.12nsispXPGA PIC Timing ParametersReset/Sett LASSRO Asynchronous Set/Reset to Output — 1.17— 1.35ns t LASSRPW Asynchronous Set/Reset Pulse Width — 4.50— 5.18ns t LASSRR Asynchronous Set/Reset Recovery —0.55—0.63ns t LSSR_S Synchronous Set/Reset Setup Time -0.03—-0.03—ns t LSSR_HSynchronous Set/Reset Hold Time0.03—0.03—ns1.t LCTHRUL quoted bit by bit.Timing v.2.0Parameter Description -4-3UnitsMin.Max.Min.Max.Register/Latch Delays t IO_CO Register Clock to Output Delay— 1.09— 1.25ns t IO_S Register Setup Time (Data before Clock)0.05—0.06—ns t IO_H Register Hold Time (Data after Clock)0.06—0.07—ns t IOCE_S Register Clock Enable Setup Time -0.03—-0.03—ns t IOCE_H Register Clock Enable Hold Time 0.13—0.15—ns t IO_GO Latch Gate to Output Delay —0.91— 1.05ns t IOL_S Latch Setup Time 0.05—0.06—ns t IOL_H Latch Hold Time0.06—0.07—ns t IOLPD Latch Propagation Delay (T ransparent Mode)—0.10—0.12ns t IOASRO Asynchronous Set/Reset to Output — 1.26— 1.45ns t IOASRPW Asynchronous Set/Reset Pulse Width — 4.50— 5.18ns t IOASRR Asynchronous Set/Reset Recovery Time —0.25—0.29ns Input/Output Delayst IOBUF Output Buffer Delay — 1.06— 1.22ns t IOIN Input Buffer Delay —0.76—0.87ns t IOEN Output Enable Delay —0.56—0.64ns t IODIS Output Disable Delay —-0.10—-0.09ns t IOFTFeed-thru Delay—0.20—0.23nsTiming v.2.0ispXPGA PFU Timing Parameters (Continued)Over Recommended Operating ConditionsParameterDescription-4-3Units Min.Max.Min.Max.ispXPGA EBR Timing ParametersParameter Description-4-3Units Min.Max.Min.Max.Synchronous Writet EBSWAD_S Address Setup Delay0.61—0.70—nst EBSWAD_H Address Hold Delay-0.39—-0.33—nst EBSWCPW Clock Pulse Width— 3.40— 3.91nst EBSWWE_S Write Enable Setup Time-0.12—-0.10—nst EBSWWE_H Write Enable Hold Time0.16—0.18—nst EBSWD_S Data Setup Time0.28—0.32—nst EBSWD_H Data Hold Time-0.26—-0.22—ns Synchronous Readt EBSR_CO Clock to Data Delay— 2.19— 2.52nst EBSRAD_S Address Setup Delay0.10—0.12—nst EBSRAD_H Address Hold Delay-0.07—-0.06—nst EBSRCPW Clock Pulse Width— 3.40— 3.91nst EBSRCE_S Clock Enable Setup Time-1.71—-1.45—nst EBSRCE_H Clock Enable Hold Time 1.69— 1.94—nst EBSRWE_S Write Enable Setup Time-0.17—-0.14—nst EBSRWE_H Write Enable Hold Time0.12—0.14—nst EBSRWEEN Write Enable to Data Enable Time— 1.05— 1.21nst EBSRWEDIS Write Enable to Data Disable Time— 1.02— 1.17nst EBSREN Output Enable to Data Enable Time— 1.05— 1.21nst EBSRDIS Output Enable to Data Disable Time—0.86—0.99ns Asynchronous Readt EBARADO Address to New Valid Data Delay— 2.46— 2.83nst EBARAD_H Address to Previous Valid Data Delay— 2.17— 2.50nst EBARWEEN Write Enable to Data Enable Time— 1.04— 1.20nst EBARWEDIS Write Enable to Data Disable Time— 1.01— 1.16nst EBAREN Output Enable to Data Enable Time— 1.05— 1.21nst EBARDIS Output Enable to Data Disable Time—0.86—0.99nsTiming v.2.0ispXPGA Family Timing AddersParameter DescriptionBaseParameter-4-3Units Min.Max.Min.Max.Optional Adderst INDIO Input Delay—— 6.0— 6.9ns t IOI Input AdjustersLVTTL_in Using 3.3V TTL t IOIN— 0.5—0.5ns LVCMOS_18_in Using 1.8V CMOS t IOIN— 0.0—0.0ns LVCMOS_25_in Using 2.5V CMOS t IOIN— 0.3—0.3ns LVCMOS_33_in Using 3.3V CMOS t IOIN— 0.5—0.5ns AGP_1X_in Using AGP 1x t IOIN— 1.0— 1.0ns CTT25_in Using CTT 2.5V t IOIN— 1.0— 1.0ns CTT33_in Using CTT 3.3V t IOIN— 1.0— 1.0ns GTL+_in Using GTL+t IOIN— 0.5—0.5ns HSTL_I_in Using HSTL 2.5V, Class I t IOIN—0.5—0.5ns HSTL_III_in Using HSTL 2.5V, Class III t IOIN—0.5—0.5ns LVDS_in Using Low VoltageDifferential Signaling (LVDS)t IOIN— 0.8—0.8nsBLVDS_in Using Bus Low VoltageDifferential Signaling (BLVDS)t IOIN—0.8—0.8ns LVPECL_in Using Low Voltage PECL t IOIN— 0.8—0.8ns PCI_in Using PCI t IOIN— 1.0— 1.0ns SSTL2_I_in Using SSTL 2.5V, Class I t IOIN— 0.8—0.8ns SSTL2_II_in Using SSTL 2.5V, Class II t IOIN— 0.5—0.5ns SSTL3_I_in Using SSTL 3.3V, Class I t IOIN— 0.8—0.8ns SSTL3_II_in Using SSTL 3.3V, Class II t IOIN— 0.8—0.8ns t IOO Output AdjustersSlow Slew Using Slow Slew (LVTTL andLVCMOS Outputs only)t IOBUF, t IOEN—0.7—0.7nsLVTTL_out Using 3.3V TTL Drive t IOBUF, t IOEN,t IODIS— 1.0 — 1.0 nsLVCMOS_18_4mA_out Using 1.8V CMOS Standard,4mA Drive t IOBUF, t IOEN,t IODIS—0.8—0.8nsLVCMOS_18_5.33mA_out Using 1.8V CMOS Standard,5.33mA Drive t IOBUF, t IOEN,t IODIS—0.6—0.6nsLVCMOS_18_8mA_out Using 1.8V CMOS Standard,8mA Drive t IOBUF, t IOEN,t IODIS—0.0—0.0nsLVCMOS_18_12mA_out Using 1.8V CMOS Standard,12mA Drive t IOBUF, t IOEN,t IODIS—0.2—0.2nsLVCMOS_25_4mA_out Using 2.5V CMOS Standard,4mA Drive t IOBUF, t IOEN,t IODIS—0.7—0.7nsLVCMOS_25_5.33mA_out Using 2.5V CMOS Standard,5.33 mA Drive t IOBUF, t IOEN,t IODIS—0.5—0.5nsLVCMOS_25_8mA_out Using 2.5V CMOS Standard,8mA Drive t IOBUF, t IOEN,t IODIS—0.5—0.5nsLVCMOS_25_12mA_out Using 2.5V CMOS Standard,12mA Drive t IOBUF, t IOEN,t IODIS—0.5—0.5nsLVCMOS_25_16mA_out Using 2.5V CMOS Standard,16mA Drive t IOBUF, t IOEN,t IODIS—0.5—0.5nsLVCMOS_33_4mA_outUsing 3.3V CMOS Standard, 4mA Drive t IOBUF , t IOEN, t IODIS— 1.0— 1.0ns LVCMOS_33_5.33mA_out Using 3.3V CMOS Standard, 5.33mA Drive t IOBUF , t IOEN,t IODIS — 1.0— 1.0ns LVCMOS_33_8mA_out Using 3.3V CMOS Standard, 8mA Drivet IOBUF , t IOEN, t IODIS —0.7—0.7ns LVCMOS_33_12mA_out Using 3.3V CMOS Standard, 12mA Drivet IOBUF , t IOEN, t IODIS —0.5—0.5ns LVCMOS_33_16mA_out Using 3.3V CMOS Standard, 16mA Drivet IOBUF , t IOEN, t IODIS —0.5—0.5ns LVCMOS_33_24mA_out Using 3.3V CMOS Standard, 24mA Drivet IOBUF , t IOEN, t IODIS —0.5—0.5ns AGP_1X_out Using AGP 1x Standard t IOBUF , t IOEN, t IODIS—0.5—0.5ns CTT25_out Using CTT 2.5V t IOBUF , t IOEN, t IODIS—0.5—0.5ns CTT33_out Using CTT 3.3V t IOBUF , t IOEN, t IODIS—0.5—0.5ns GTL+_out Using GTL+t IOBUF , t IOEN, t IODIS—0.5—0.5ns HSTL_I_out Using HSTL 2.5V , Class I t IOBUF , t IOEN, t IODIS—0.5—0.5ns HSTL_III_out Using HSTL 2.5V , Class III t IOBUF , t IOEN, t IODIS—0.5—0.5ns LVDS_out Using Low Voltage Differen-tial Signaling (LVDS)t IOBUF , t IOEN, t IODIS— 1.0— 1.0ns BLVDS_out Using Bus Low Voltage Differ-ential Signaling (BLVDS)t IOBUF , t IOEN,t IODIS — 1.0— 1.0ns LVPECL_out Using Low Voltage PECL t IOBUF , t IOEN, t IODIS— 1.0— 1.0ns PCI_out Using PCI Standard t IOBUF , t IOEN, t IODIS—0.5—0.5ns SSTL2_I_out Using SSTL 2.5V , Class I t IOBUF , t IOEN, t IODIS—0.5—0.5ns SSTL2_II_out Using SSTL 2.5V , Class II t IOBUF , t IOEN, t IODIS—0.5—0.5ns SSTL3_I_out Using SSTL 3.3V , Class I t IOBUF , t IOEN, t IODIS—0.5—0.5ns SSTL3_II_outUsing SSTL 3.3V , Class IIt IOBUF , t IOEN, t IODIS—0.5—0.5nsTiming v.2.0ispXPGA Family Timing Adders (Continued)ParameterDescriptionBase Parameter-4-3Units Min.Max.Min.Max.。

Extract from the onlinecatalogFKICS 2,5/11-ST-5,08Order No.: 1981830The figure shows a 10-position version of the producthttp://eshop.phoenixcontact.de/phoenix/treeViewClick.do?UID=1981830Plug, inverted, number of positions: 11, pitch: 5.08 mm, U = 320 V, I = 12 A, nominal cross section = 2.5 mm²http://Please note that the data givenhere has been taken from theonline catalog. For comprehensiveinformation and data, please referto the user documentation. TheGeneral Terms and Conditions ofUse apply to Internet downloads. Technical dataDimensions / positionsPitch 5.08 mmDimension a50.8 mmNumber of positions11Technical dataInsulating material group IRated surge voltage (III/3) 4 kV Rated surge voltage (III/2) 4 kV Rated surge voltage (II/2) 4 kV Rated voltage (III/2)320 V Rated voltage (II/2)630 V Connection in acc. with standard EN-VDE Nominal current I N12 A Nominal voltage U N320 V Nominal cross section 2.5 mm2 Maximum load current12 A Insulating material PA Inflammability class acc. to UL 94V0 Internal cylindrical gage A2 Stripping length10 mmConnection dataConductor cross section solid min.0.2 mm2 Conductor cross section solid max. 2.5 mm2 Conductor cross section stranded min.0.2 mm2 Conductor cross section stranded max. 2.5 mm2 Conductor cross section stranded, with ferrule0.25 mm2 with plastic sleeve min.Conductor cross section stranded, with ferrule1.5 mm2 with plastic sleeve max.Conductor cross section AWG/kcmil min.24 Conductor cross section AWG/kcmil max162 conductors with same cross section, stranded,0.5 mm2 TWIN ferrules with plastic sleeve, min.2 conductors with same cross section, stranded,1 mm2 TWIN ferrules with plastic sleeve, max.Certificates / ApprovalsApproval logoCULNominal voltage U N300 VNominal current I N10 AAWG/kcmil26-12ULNominal voltage U N300 VNominal current I N10 AAWG/kcmil26-12Certification CB, CUL, UL, VDE-PZIAccessoriesItem Designation DescriptionAssembly1876880STZ 8-FKC-5,08Strain relief for snapping into the latching chambers of the plugcomponents, 8-pos.1876877STZ 4-FKC-5,08Strain relief for snapping into the latching chambers of the plugs,4-pos.Marking0804293SK 5,08/3,8:FORTL.ZAHLEN Marker card, printed horizontally, self-adhesive, 12 identicaldecades marked 1-10, 11-20 etc. up to 91-(99)100, sufficient for120 terminal blocksPlug/Adapter1734401CR-MSTB Coding section, inserted into the recess in the header or theinverted plug, red insulating material0201744MPS-MT Test plug, consisting of: Metal part for 2.3 mm diameter sockethole0201647RPS Reducing plug, for transition from 4 mm diameter test plug socket,insulation: grayTools1205053SZS 0,6X3,5Screwdriver, bladed, matches all screw terminal blocks up to 4.0mm² connection cross section, blade: 0.6 x 3.5 mm, without VDEapprovalAdditional productsItem Designation DescriptionGeneral1872693A-ICV 2,5/ 2-G-5,08Header, nominal current: 12 A, rated voltage: 250 V, pitch: 5.08mm, no. of positions: 2, mounting: Mounting rail1873058FKC 2,5/ 2-ST-5,08Plug component, nominal current: 12 A, rated voltage: 250 V,pitch: 5.08 mm, no. of positions: 2, type of connection: Spring-cage connection1902110FKCT 2,5/ 2-ST-5,08Plug component, nominal current: 12 A, rated voltage: 250 V,pitch: 5.08 mm, no. of positions: 2, type of connection: Spring-cage connection1873951FKCVR 2,5/ 2-ST-5,08Plug component, nominal current: 12 A, rated voltage: 250 V,pitch: 5.08 mm, no. of positions: 2, type of connection: Spring-cage connection1873650FKCVW 2,5/ 2-ST-5,08Plug component, nominal current: 12 A, rated voltage: 250 V,pitch: 5.08 mm, no. of positions: 2, type of connection: Spring-cage connection1777280FRONT-MSTB 2,5/ 2-ST-5,08Plug component, nominal current: 12 A, rated voltage: 250 V,pitch: 5.08 mm, no. of positions: 2, type of connection: Screwconnection1786404IC 2,5/ 2-G-5,08Header, nominal current: 12 A, rated voltage: 320 V, pitch: 5.08mm, number of positions: 2, mounting type: Soldering 1785942ICV 2,5/ 2-G-5,08Header, nominal current: 12 A, rated voltage: 320 V, pitch: 5.08mm, number of positions: 2, mounting type: Soldering 1757019MSTB 2,5/ 2-ST-5,08Plug component, nominal current: 12 A, rated voltage: 250 V,pitch: 5.08 mm, no. of positions: 2, type of connection: Screwconnection1808816MSTBC 2,5/ 2-ST-5,08Plug component, nominal current: 12 A, rated voltage: 320 V,pitch: 5.08 mm, no. of positions: 2, type of connection: Crimpconnection1809501MSTBC 2,5/ 2-STZ-5,08Plug component, nominal current: 12 A, rated voltage: 320 V,pitch: 5.08 mm, no. of positions: 2, type of connection: Crimpconnection1769010MSTBP 2,5/ 2-ST-5,08Plug component, nominal current: 12 A, rated voltage: 250 V,pitch: 5.08 mm, no. of positions: 2, type of connection: Screwconnection1779987MSTBT 2,5/ 2-ST-5,08Plug component, nominal current: 12 A, rated voltage: 250 V,pitch: 5.08 mm, no. of positions: 2, type of connection: Screwconnection1824120MSTBU 2,5/ 2-STD-5,08Plug component, nominal current: 12 A, rated voltage: 320 V,pitch: 5.08 mm, no. of positions: 2, type of connection: Screwconnection1792249MVSTBR 2,5/ 2-ST-5,08Plug component, nominal current: 12 A, rated voltage: 250 V,pitch: 5.08 mm, no. of positions: 2, type of connection: Screwconnection1792757MVSTBW 2,5/ 2-ST-5,08Plug component, nominal current: 12 A, rated voltage: 250 V,pitch: 5.08 mm, no. of positions: 2, type of connection: Screwconnection1917901QC 0,75/ 2-ST-5,08Plug components, 5.08 mm pitch, color: green, no. of positions 2,dimension a 5.08 mm1883255QC 1/ 2-ST-5,08Plug, nominal current: 10 A, rated voltage: 500 V, pitch: 5.08mm, number of positions: 2, connection method: Insulationdisplacement connection QUICKON1826283SMSTB 2,5/ 2-ST-5,08Plug component, nominal current: 12 A, rated voltage: 250 V,pitch: 5.08 mm, no. of positions: 2, type of connection: Screwconnection1853010TMSTBP 2,5/ 2-ST-5,08Plug component, nominal current: 12 A, rated voltage: 250 V,pitch: 5.08 mm, no. of positions: 2, type of connection: Screwconnection1873029ZFKK 1,5-ICV-5,08Modular terminal blocks with plug entry, cross section: 0.2 - 1.5mm², width: 5.1 mm, color: grayDrawingsDimensioned drawingAddressPHOENIX CONTACT GmbH & Co. KGFlachsmarktstr. 832825 Blomberg,GermanyPhone +49 5235 3 00Fax +49 5235 3 41200http://www.phoenixcontact.de© 2008 Phoenix ContactTechnical modifications reserved;。

IrCCInfrared Communications ControllerFEATURES• Multi-Protocol Serial Communications Controller• Full IrDA v1.1 Implementation: 2.4Kbps, 115.2Kbps, .576Mbps, 1.152Mbps and4Mbps• Consumer Infrared (TV Remote Control) Interface• SHARP Amplitude Shift Keyed Infrared (ASK IR) Interface• Direct Rx/Tx Infrared Diode Control (Raw) and General Purpose Data Pins • Programmable High-Speed Synchronous Communications Engine (SCE) with a 128-Byte FIFO and Programmable Threshold • High-Speed NS16C550A-Compatible Universal Asynchronous Receiver/Transmitter Interface (ACE UART2) with 16-Byte Send and Receive FIFOs• ISA Single-Byte and Burst-Mode DMA and Interrupt-Driven Programmed I/O with ZeroWait State and String Move Timing• 16-bit CRC-CCITT and 32-bit IEEE 802 CRC32 Hardware CRC GeneratorsGENERAL DESCRIPTIONThis document describes the Infrared Communications Controller (IrCC) function whichis common to a number of SMSC products including the FDC37C669FR, FDC37C93xFR, and FDC37C957FR devices. The IrCC consistsof two main architectural blocks: the ACE 16550A UART and a Synchronous Communications Engine (SCE) (Figure 2). Each block is supported by its own unique register set.The IrCC UART-driven IrDA SIR and SHARP ASK modes are backward-compatible with early SMSC Super I/O and Ultra I/O infrared implementations. The IrCC SCE supports IrDA v1.1 .576Mbps, 1.152Mbps, 4Mbps, and Consumer IR modes. All of the SCE modes use DMA. The IrCC offers flexible signal routing and programmable output control through the Raw mode interface, General Purpose Data pins and Output Multiplexer. Chip-level address decodingis required to access the IrCC register sets.TABLE OF CONTENTS FEATURES (1)GENERAL DESCRIPTION (1)INTERFACE DESCRIPTION (4)PORTS (4)CONFIGURATION CONTROLS (6)CHIP-LEVELRAW IR (8)CONSUMER IR (TV REMOTE) (9)INTRODUCTION (9)DESCRIPTION (10)IrDA SIR AND SHARP ASK IR INTERFACE (14)DATA ASSOCIATION (19)INFRARED REGISTERS (24)ACECONTROLS (24)UARTCONTROLS (25)SCEMASTER BLOCK CONTROL REGISTER (26)BLOCK ZERO (27)REGISTERBLOCK ONE (32)REGISTERBLOCK TWO (36)REGISTERREGISTERBLOCK THREE (37)BLOCK FOUR (38)REGISTERACE UART (40)DESCRIPTION (40)REGISTER SCE (55)DESCRIPTION (55)FRAMING (55)INDICATOR (55)ACTIVEFRAMEENCODER (56)IrDAIR ENCODER (61)CONSUMERLOOPBACK MODE (63)BUS INTERFACE I/O (65)MULTIPLEXER (65)FIFOSCE FIFO (65)128-BYTEDMA (67)PROGRAMMED I/O (71)IOCHRDYTIME-OUT (73)ZERO WAIT STATE SUPPORT (75)OUTPUT MULTIPLEXER (76)CHIP-LEVEL IrCC ADDRESSING SUPPORT (77)AC TIMING (78)23INTERFACE DESCRIPTIONThe Interface Description lists the signals that are required to place the IrCC in a larger chip-level context.There are four groups of signals in this section: PORT signals, HOST BUS controls, SYSTEM controls, and CHIP-LEVEL CONFIGURATION controls. PORTSThe four Ports (IR, COM, AUX, and General Purpose) provide external access for serial data and controls. The active IrCC encoder is routed through the Output Multiplexer to either the IR, COM, or AUX port. The General Purpose port provides external access for controls that are independent of the IrCC Block Control bits or the Output Multiplexer.Table 1 - IR Port SignalsNAME SIZE(BITS) TYPE DESCRIPTIONIRRx 1 Input Infrared Receive DataIRTx 1 Output Infrared Transmit DataTable 2 - COM Port SignalsNAME SIZE(BITS) TYPE DESCRIPTIONCRx 1 Input COM Receive DataCTx 1 Output COM Transmit DatanRTS 1 Output Request to SendnDTR 1 Output Data Terminal Ready nCTS 1 Input Clear To SendnDSR 1 Input Data Set ReadynDCD 1 Input Data Carrier DetectnRI 1 Input RingIndicatorTable 3 - AUX Port Signals(e.g., can be used for high-current drivers for Consumer IR) NAME SIZE(BITS) TYPE DESCRIPTIONARx 1 Input Aux. Receive DataATx 1 Output Aux. Transmit Data4NAME SIZE(BITS) TYPE DESCRIPTION Fast 1 Output General Purpose Data GP Data 1 Output General Purpose DataFastThe Fast pin always reflects the state of Fast, bit 6 of SCE Line Control Register A. The state of Fast is independent of the IrCC Block Controls or the Output Multiplexer. The Fast pin can be used at the chip level for IR Transceiver configuration. GP DataThe G.P. Data pin always reflects the state of General Purpose Data, bit 5 of SCE Line Control Register A. The state of G.P. Data is independent of the IrCC Block Controls or the Output Multiplexer.Table 5 - HOST SignalsNAME SIZE(BITS) TYPE DESCRIPTIOND0-D7 8 Bidirectional Host Data BusA0-A2 3 Input IrCC Register Address BusnIOR 1 Input ISA I/O ReadnIOW 1 Input ISA I/O WriteAEN 1 Input ISA Address EnableDRQ 1 Output DMARequest nDACK 1 Input ISA DMA AcknowledgeTC 1 Input ISA DMA Terminal CountIRQ 1 Output InterruptRequest IOCHRDY 1 Output ISA I/O Channel ReadynSRDY 1 OutputISASynchronous Ready (Zero Wait State)5NAME SIZE(BITS) TYPE DESCRIPTION CLK 1 Input SystemClock RESET 1 Input IrCC System ResetPower Down 1 Input Low Power ControlDMAEN 1 Output DRQ Tristate ControlIRQEN 1 Output IRQ Tristate ControlnACE 1 Input ACE 550 Register Bank SelectnSCE 1 Input SCE Register Bank SelectVCC Power SystemSupply GND Power SystemGroundDMAENDMAEN is used by the chip-level interface to tristate the IrCC DRQ output when the DMA Enable bit is inactive. The DMA Enable bit is located in SCE Configuration Register B, bit 0.IRQENIRQEN is used by the chip-level interface to tristate the IrCC IRQ output when the OUT2 bit is inactive. The OUT2 bit is located in 16550A MODEM Control Register.Power DownThe Power Down pin is used by the chip-level interface to put the SCE into low power mode. NOTE: Power Down does not force the ACE550 into low power mode.CHIP-LEVEL CONFIGURATION CONTROLSThe following signals come from chip-level configuration registers. There are two types of Chip-Level Configuration Controls: IrCC-Specific controls, and Legacy Controls. Both types have equivalent controls in either the IrCC ACE or SCE Registers.The IrCC-Specific controls have been newly added primarily to support the IrCC block.Provisions have been made in new chip-level configuraton contexts to accommodate these signals.The Legacy controls already exist in other contexts. Provisions have been made in legacy devices to accommodate these controls from either the Chip-Level Configuration Registers or the IrCC Registers; i.e., the last updated value from either source determines the current control state and is visible in both registers.6Table 7 - IRCC-Specific Chip-Level ControlsNAME SIZE(BITS) TYPE DESCRIPTION DMA Channel 4 Input ISA DMA Channel Number IRQ Level 4 Input ISA Interrupt LevelDMA Channel4-bit bus from a chip-level configuration register, used to identify the current IrCC DMA channel number. The value appears in the upper nibble of IrCC Register Block Three, Address Four. IRQ Level4-bit bus from a chip-level configuration register, used to identify the current IrCC IRQ level. The value appears in the lower nibble of IrCC Register Block Three, Address Four.Table 8 - Legacy Chip-Level ControlsNAME SIZE(BITS)TYPE DESCRIPTION Tx Polarity 1 Input Output Mux. Transmit Polarity Rx Polarity 1 Input Output Mux. Receive Polarity Half Duplex 1 Input 16550A UART Half Duplex Control IR Mode 3 Input IR Mode Register BitsIR Location 2 Input IR Option Register Location BitsTx PolarityTypically part of a 16550A Serial Port Option Register. The value also appears in IrCC Register Block One, Address Zero.Rx PolarityTypically part of a 16550A Serial Port Option Register. The value also appears in IrCC Register Block One, Address Zero.Half DuplexTypically part of a 16550A Serial Port Option Register. The value also appears in IrCC Register Block One, Address Zero.IR ModeTypically part of a 16550A Serial Port Option Register. These values are also part of the IrCC Block Control bits 3-5, Register Block One, Address Zero.IR LocationTypically part of a 16550A Serial Port IR Option Register. These values are the IrCC Output Mux bits, Register Block One, Address One.NOTE: These legacy controls are uniformly updated in the IrCC and the Top-level Device Configuration Registers only when either set of registers are explicitly written using IOW or following a device-level POR. IrCC software resets will not affect the legacy bits.7OPERATION MODESRAW IRIn Raw mode the state of the IR emitter and detector can be directly accessed through the host interface (Figure 3).The IR emitter tracks the Raw Tx Control bit. For example, depending on the state of the Tx Polarity control a logic '1' may turn the LED on and a logic '0' may turn the LED off. Care must be taken in software to ensure that the LED is not on continuously. The Raw Rx Control bit represents the state of the PIN diode. For example, depending on the state of the Rx Polarity control a logic '1' may mean no IR is detected, a logic '0' may mean IR is being detected. If an IR carrier is being received, the Raw Rx Control bit will oscillate at the carrier frequency.If enabled, a Raw Mode Interrupt will be generated when the Raw Rx Control bit transitions to the active state, depending on the state of the Rx Polarity control.8CONSUMER IR (TV REMOTE)INTRODUCTIONThe IrCC Consumer IR (TV Remote) block is a general-purpose programmable Amplitude Shift Keyed serial communications interface that includes a Carrier Frequency Divider, a Programmable Receive Carrier Range Sensitivity Register, and Receive and Transmit Modulators (Figure 4).The Consumer IR block transfers data between the SCE and Output Multiplexer without framing as a fixed bit-cell serial NRZ data stream. The components of this block can also modulate and demodulate serial data at programmable bit rates and carrier frequencies.Variable length encoding and all packet framing is handled by system software. Consequently, many encoding methods, modulation frequencies and bit rates can be supported, including 38KHz PPM, PWM and RC-5 TV Remote formats. Register controls for this block can be found in Register Block Two. They are the Consumer IR Control Register, the Consumer IR Carrier Rate Register, and the Consumer IR Bit Rate Register.9DESCRIPTIONCarrier Frequency DividerThe Carrier Frequency Divider register is used to program the ASK carrier frequency for the transmit modulator and receive detector (Figure 5). The divider is eight bits wide.The input clock to the Carrier Frequency Divider is 1.6MHz (48MHz ÷ 30). The relationship between the divider value (CFD) and the carrier frequency (Fc) is as follows:CFD = (1.6MHz/Fc) - 1 For example, program the Carrier Frequency Divider register with 41 ('29'Hex) for a 38KHz TV Remote: Fc = 38.095KHz. This is ~.25% accuracy. Table 9 contains representative CFD vs. Carrier Frequency relationships.The Carrier Frequency range is 1.6MHz to 6.25KHz.The carrier frequency encoder/decoder can be defeated using the Carrier Off bit. When Carrier Off is one, the transmitter outputs a non-modulated SCE serial NRZ data stream at the programmed bit rate; the receiver does not attempt to demodulate a carrier from the incoming serial data stream.Table 9 - Representative Carrier Frequencies10Bit Rate DividerThe Transmit and Receive Bit Rate Divider register is used to extract a serial NRZ data stream for the IrCC SCE. The divider is eight bits wide.The input clock to the Bit Rate Divider is 100KHz (Carrier Frequency Divider input clock ÷ 16). The relationship between the Bit Rate Divider (BRD) and the Bit Rate (Fb) is as follows:BRD = (.1MHz/Fb) - 1For example, program the Bit Rate Divider with 55 ('37'Hex) for a .562ms TV Remote bit cell: Fb = 1.786KHz. This is ~.5% accuracy. Table 10 contains representative BRD vs. Bit Rate relationships. The Bit Rate range is 100KHz to 390.625Hz.Table 10 - Representative Bit Rates11Receive Carrier SenseThe Programmable Receive Carrier Sense register is used to program the Consumer IR decoder to detect the presence of IR energy in a wide-to-narrow range of carrier frequencies. The register is two bits wide. The range values are shown in Table 11. Carriers that fall outside of the Receive Carrier range sensitivity “abort” the message; i.e., the Abort bit is set, an EOM Interrupt is generated, and the receiver is disabled. If the “Carrier Off” bit is active, the Receive Carrier range sensitivity is disabled.Table 11 - Receive Carrier Sense Range D1 D0 RANGE0 0 ±10%0 1 ±20%1 0 ±40%1 1 reserved12Receiver Bit Cell SynchronizationThe Consumer IR Receiver demodulates incoming ASK waveforms into NRZ data for the SCE. The IrCC uses the edges of the demodulated incoming infrared data to indicate changes in bit state.For continuous periods of high or low data without transitions, the IrCC samples the signal level in the center of each incoming bit period. Using the Receiver Bit Cell Synchronization mechanism, any transition resets the timer that is used in the sampling process to eliminate errors due to timing differences between the receive decoder and the incoming bit period (Figure 6). Receiver synchronization can be disabled to allow direct sampling of the demodulated incoming infrared data stream at some preset receive bit rate. This is useful in situations where the speed of the receive data is not strictly known. In such cases, the receive bit rate is set as high as possible, the Receiver Bit Cell Synchronization is disabled, and the system software is used to measure the bit-cell period from the oversampled data. The learned parameters can then be used to switch to the synchronized, fixed bit-cell mode to reduce processing overhead in the host CPU for all future transactions.13IrDA SIR AND SHARP ASK IR INTERFACEThis infrared interface provides a two-way wireless communications port using infrared as a transmission medium. Two infrared implementations have been provided in this blockof the IrCC, IrDA SIR and Sharp ASK IR.IrDA SIR allows serial communication at baud rates up to 115K Baud. Each word is sent serially beginning with a zero value start bit. A zero is signaled by sending a single infrared pulse at the beginning of the serial bit time. A one is signaled by sending no infrared pulse during the bit time. Please refer to Figure 7-Figure 10 for the parameters of these pulses and the IrDA waveform.The ASK infrared allows serial communication at baud rates up to 19.2K Baud. Each word is sent serially beginning with a zero value start bit. A zero is signaled by sending a 500KHz waveform for the duration of the serial bit time. A one is signaled by sending no transmission during the bit time. Please refer to the AC timing for the parameters of the ASKIR waveform.If the Half Duplex option is chosen, there is a time-out when the direction of the transmission is changed. This time-out starts at the last bit transferred during a transmission and blocks the receiver input until the time-out expires. If the transmit buffer is loaded with more data before the time-out expires, the timer is restarted after the new byte is transmitted. If data is loaded into the transmit buffer while a character is being received, the transmission will not start until the time-out expires after the last receive bit has been received. If the start bit of another character is received during this time-out, the timer is restarted after the new character is received. The time-out is programmable up to a maximum of 10ms through the IR Half-Duplex Time-Out Configuration Register.1415PARAMETER MIN TYP MAX UNITSt1 Pulse Width at 115kbaud1.41.62.71µst1 Pulse Width at 57.6kbaud 1.4 3.22 3.69 µs t1 Pulse Width at 38.4kbaud 1.4 4.8 5.53 µs t1 Pulse Width at 19.2kbaud 1.4 9.7 11.07 µs t1 Pulse Width at 9.6kbaud 1.4 19.5 22.13 µs t1 Pulse Width at 4.8kbaud 1.4 39 44.27 µs t1 Pulse Width at 2.4kbaud 1.4 78 88.5 µs t2 Bit Time at 115kbaud 8.68 µs t2 Bit Time at 57.6kbaud 17.4 µs t2 Bit Time at 38.4kbaud 26 µs t2 Bit Time at 19.2kbaud 52 µs t2 Bit Time at 9.6kbaud 104 µs t2 Bit Time at 4.8kbaud 208 µs t2Bit Time at 2.4kbaud416µsNOTES:1. IrDA @ 115k is HPSIR compatible. IrDA @ 2400 will allow compatibility with HP95LX and 48SX.2. IRRX: CRC Bit 1: 1 = XMIT active lownIRRX: CRC Bit 1: 0 = XMIT active high (default)UNITSMAXTYPPARAMETER MINt1 Pulse Width at 115kbaud 1.41 1.6 2.71 µst1 Pulse Width at 57.6kbaud 1.41 3.22 3.69 µs5.53t1 Pulse Width at 38.4kbaud 1.414.8µs11.079.7t1 Pulse Width at 19.2kbaud 1.41µs22.1319.5t1 Pulse Width at 9.6kbaud 1.41µst1 Pulse Width at 4.8kbaud 1.41 39 44.27 µst1 Pulse Width at 2.4kbaud 1.41 78 88.55 µst2 Bit Time at 115kbaud 8.68 µst2 Bit Time at 57.6kbaud 17.4 µst2 Bit Time at 38.4kbaud 26 µst2 Bit Time at 19.2kbaud 52 µst2 Bit Time at 9.6kbaud 104 µst2 Bit Time at 4.8kbaud 208 µst2 Bit Time at 2.4kbaud 416 µsNOTES:1. Receive Pulse Detection Criteria: A received pulse is conidered detected if the received pulse is aminimum of 1.41 µs2. IRTX: CRC Bit 0: 1 = RCV active lownIRTX: CRC Bit 0: 0 = RCV active high (default)16UNITSMAXTYPPARAMETER MINt1 Modulated Output Bit Time µst2 Off Bit Time µsOutput “On” 0.8 1 1.2 µst3 Modulatedt4 Modulated Output “Off” 0.8 1 1.2 µsOutput “On” 0.8 1 1.2 µst5 Modulatedt6 Modulated Output “Off” 0.8 1 1.2 µsNOTES:1. IRTX: CRC Bit 1: 1 = XMIT active lownIRTX: CRC Bit 1: 0 = XMIT active high (default)MIRTX, nMIRTX are the modulated outputs.17UNITSMAXTYPPARAMETER MINt1 Modulated Output Bit Time µst2 Off Bit Time µsOutput “On” 0.8 1 1.2 µst3 Modulatedt4 Modulated Output “Off” 0.8 1 1.2 µsOutput “On” 0.8 1 1.2 µst5 Modulatedt6 Modulated Output “Off” 0.8 1 1.2 µsNOTES:1. IRRX: CRC Bit 1: 1 = RCV active lownIRRX: CRC Bit 1: 0 = RCV active high (default)MIRRX, nMIRRX are the modulated outputs.18INFRARED DATA ASSOCIATIONDescriptionThe Infrared Data Association (IrDA) was created to develop an interoperable, low-cost, low-power, half-duplex serial data interconnection standard that supports a walk-up, point-to-point user model that is adaptable to a wide range of appliances and devices.The IrDA Serial Infrared Data Link Standard, Version 1.1 is the standard to which the SMSC IrCC conforms. Relevant IrDA documents in this specification include the SIR-Physical Layer Specification, Version 1.1, October 17, 1995, the SIR-Link Access Protocol (IrLAP), Version 1.0, June 23, 1994, and the Link Management Protocol (IrLMP), Version 1.1, January 23, 1996.The high-speed extensions (FIR) to the IrDA physical layer as described in the SIR-Physical Layer Specification appear as alternate modulation and demodulation paths for data from IrLAP bound for the IR medium and are transparent to IrLAP as it is defined for SIR.IR hardware and software must comply as a system with the entire family of IrDA specifications, including the SIR/FIR-Physical Layer Specifications, IrLAP, and IrLMP.A block diagram of one end of an IrDA link that includes the SIR and FIR physical implementations is shown in Figure 11.SIR Interaction PulseThe SIR Interaction Pulse (SIP) is intended to guarantee non-disruptive coexistence with SIR-only systems which might otherwise interfere with Fast IR links.A SIP is defined as a 1.6 microsecondtransmitter on pulse followed by 7.1 microseconds of off time (Figure 12). Once aFast connection has been established the stationmust generate one SIP every 500ms.19The SIR Interaction Pulse is controlled by the IrCC configuration register SIP ENABLE bit and a timer. The IrCC transmits an SIR Interaction Pulse every 500ms when the SIP enable is active, an IrDA FIR mode has been selected, and the transmitter or receiver is not otherwise engaged. The timer that controls the SIP pulse is reset whenever 1) the SIP enable is inactive, 2) an active FIR frame is being transmitted or received or, 3) during an active SIP pulse. The timer is decrementing whenever the SIP enable bit is active and the SIP pulse generator, the transmitter, and the receiver are inactive. When the timer reaches zero, the SIP pulse generator is activated (Figure 13).20HDLC BOF CountingThe IrCC can account for system-dependent limitations such as long interrupt latencies and transceiver stabilization times by increasing the number of STA flags at the beginning of every HDLC frame (Figure 14). The BOF COUNT register contains the number additional start flags that are to be appended to the standard BOF characters.NOTE: the BOF COUNT extensions only apply to messages that start from an idle line state; i.e., BOF counting does not apply to brick walled messages.HDLC Back-to-Back Frame Transmission HDLC back-to-back, or brick walled frames are allowed with two or more flags, '7E'hex, in between. If two consecutive frames are not back-to-back, the gap between the last STO flag of the first frame and the first STA field of the second frame are separated by at least seven bit times (abort sequence). The IrDA FIR 1.152Mbps and .576Mbps physical layer specification allows back-to-back message packets with three flag characters which act as the closing flag of the first frame and the opening flags of the brick walled packet. Additional flags can be added by programming the Brick Wall Count register (Figure 15).NOTE: The BOF COUNT extensions do not apply to brick walled messages.214PPM BOF CountingThe IrCC can account for system-dependent limitations such as long interrupt latencies and transceiver stabilization times by increasing the number of PA flags at the beginning of every 4PPM frame (Figure 16).The BOF COUNT register contains the number of additional PA bytes that are to be appended to the standard 4PPM BOF characters.NOTE: the BOF COUNT extensions only apply to messages that start from an idle line state; i.e., BOF counting does not apply to brick walled messages.224PPM Back-to-Back Frame Transmission Back-to-back, or brick walled frames are allowed with 32 or more PA flag bytes between the STO field of the first frame and the STA field of the second frame. Additional flags can be added by programming the Brick Wall Count register.NOTE: the BOF COUNT extensions do not apply to brick walled messages.23REGISTERSThe IrCC is partially enabled through binary controls found in two 8-byte register banks. The banks, the ACE550 UART Controls and the SCE Controls, are selected with the nACE and nSCE register-bank selector inputs found in the Interface Description.If nACE is zero, the three least significant bits of the Host Address Bus decode the 16550A UART control registers. If nSCE is zero, the SCE control bank is addressed. All of the IrCC registers are 8 bits wide.ACE UART CONTROLSThe table below (Table 12) lists the ACE UART Control Registers (see the ACE UART section).Table 12 - 16550A UART AddressingDLAB A2 A1 A0 DIRECTION REGISTERNAME0 0 0 0 Read ReceiveBuffer0 0 0 0 Write TransmitBuffer0 0 0 1 Read/Write InterruptEnableX 0 1 0 Read Interrupt IdentificationX 0 1 0 Write FIFOControlX 0 1 1 Read/Write LineControlX 1 0 0 Read/Write ModemControlX 1 0 1 Read/Write LineStatusX 1 1 0 Read/Write ModemStatus X 1 1 1 Read/Write Scratchpad1 0 0 0 Read/Write Divisor(LSB)1 0 0 1 Read/Write Divisor(MSB)24SCE CONTROLSThe IrCC SCE Registers are arranged in 7-byte blocks. Of the eight possible register blocks, five are used in this implementation. The Master Block Control Register controls access to the register blocks.Table 13 lists all of the SCE registers in all blocks.Table 13 - SCE Register AddressingBLOCK ADDRESS DIRECTION REGISTERNAME X 7 R/W MasterControl0 0 R/W DataRegister0 1 RO Interrupt Identification0 2 R/W InterruptEnable0 3 RO Line Status (read)0 3 WO Line Status Address (write)0 4 R/W Line Control A0 5 R/W Line Control B0 6 R/W BusStatus1 0 R/W SCE Configuration A1 1 R/W SCE Configuration B1 2 R/W FIFOThreshold2 0 R/W Consumer IR Control2 1 R/W Consumer IR Carrier Rate2 2 R/W Consumer IR Bit Rate3 0 RO SMSC ID (high)3 1 RO SMSC ID (low)3 2 RO CHIPID3 3 RO VERSIONNumber3 4 RO IRQ Level DMA Channel4 0 R/W IrDA Control BOF Count (high)4 1 R/W BOF Count (low)4 2 R/W Brick Wall Count (low)4 3 R/W BW Count (high) Tx Data Size (high)4 4 R/W Tx Data Size (low)4 5 R/W Rx Data Size (high)4 6 R/W Rx Data Size (low)25MASTER BLOCK CONTROL REGISTERThe Master Block Control Register contains the IrCC Power Down bit, two reset bits, the Master Interrupt Enable bit, and the Register Block Select lines (Table 14). Address seven is solely reserved for the Master Block Control register. If the nSCE input is zero, the MBC is always visible, regardless of the state of the Register Block Select lines.Table 14 - SCE Master Block Control RegisterAddress Direction Description Default A2A1A0D7 D6 D5 D4 D3 D2 D1D01 1 1 R/W Master Block Control Register '00'hexpower down masterresetmasterint en.errorresetregisterblockselectRegister Block Select, bits 0-2The Register Block Select bits enable access to each of the eight possible register blocks. To access a register block other than the default (0), write a 3-bit register block number to the least significant bits of the Master Block Control Register. All subsequent reads and writes to addresses 0 through 6 will access the registers in the new block. To return to register block 0, rewrite zeros to the register block select bits. Error Reset, bit 4Writing a one to the Error Reset bit will return all of the SCE Line Status Register bits (Register Block Zero) to their inactive states and reset the Message Count bits to zero.Master Interrupt Enable, bit 5Setting the Master Interrupt Enable to a one enables all of the SCE interrupts only if their individual controls are enabled. Setting this bit to a zero disables all SCE interrupts regardless of the state of their individual enables.Master Reset, bit 6Setting the Master Reset bit to a one forces data in the SCE registers and SCE logical blocks into the Power-On-Reset state. The Master Reset bit is reset to zero following the reset operation. NOTE: The Legacy bits (Register Block One, Address Zero, Bits D0-D6) are unaffected by Master Reset.Power Down, bit 7Setting this bit to a one causes only the SCE to enter the low-power state. Power down mode does not preclude access to the Master Block Control register so that this mode can be maintained entirely under software control.2627REGISTER BLOCK ZERORegister Block Zero contains the SCE Data Register, the Interrupt Control/Status registers,the Line Control/Status registers, and the Bus Status register (Table 15).Typically, the controls in Register Block Zero are used during IrDA FIR and Consumer IR message transactions. Table 15 - Register Block ZeroAddress Directio Description Default A2 A1 A0D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 R/W Data Register0 0 1 ROInterrupt Identification Register'00'hexactive frame eom rawmodefifo0 1 0 R/WInterrupt Enable Register'00'hexactive frame eom raw modefifo11ROLine Status Register (read)'00'hex under-runover- runframe errorsize errorcrc errorframe abort11WOLine Status Address Register (write)status register address1R/WLine Control Register A'00'hexfifo reset fast g. p. data rawtxraw rxabort datadone 11R/WLine Control Register B'00'hexsce modes bits sip enable brickwallmessage count1 1 0 ROBus Status Register'00'hexnot empty fifo full time-outData Register (Address 0)The Data Register is the FIFO access port. Typically, the user will only write to the FIFO when transmitting and read from the FIFO when receiving. The Host always has read access to the FIFO regardless of the state of the SCE Modes bits or the Loopback bit. Host read access to the FIFO is blocked when the FIFO is empty. The Host has write access to the FIFO only when the Loopback bit is inactive and the SCE Modes bits are zero or Transmit mode isenabled. Host write access to the FIFO is blocked when the FIFO is full.Interrupt Identification Register (Address 1)Active Frame, bit 7When this bit is one, an Active Frame has occurred (see the Active Frame Indicator section). The Active Frame typically indicates that the SCE receiver has detected a valid incoming IrDA FIR or TV Remote start-of-frame sequence. Reading the Interrupt Identification register resets the Active Frame bit.。

Maximum Ratings (Each Channel)
Emitter Peak Reverse Voltage .....................................6.0 V Peak Pulsed Current (1 µs, 300 pps) .................1 A Continuous Forward Current per Channel ....30 mA Power Dissipation at 25°C............................45 mW Derate Linearly from 25°C......................0.5 mW/°C
CTR (nonsat) normalized @ If=10ma Vce=10v Ta=25°C
100
Package Power Dissipation (mw)
Figure 7. Power dissipation versus ambient temperature
200 Total pkg
150
元器件交易网
FEATURES • Two Channel Coupler • Industry Standard SOIC-8 Surface Mountable
Package • Standard Lead Spacing of .05" • Available in Tape and Reel Option
.230±.002 (4.88±.05)
Pin 1
Anode 1
CL
.154±.002 (3.91±.05)
Cathode Anode
2 3
Cathode 4