CD74FCT843A(844A)
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SN74CBT3306CDUAL FET BUS SWITCH5ĆV BUS SWITCH WITH ć2ĆV UNDERSHOOT PROTECTIONSCDS127A − SEPTEMBER 2003 − REVISED OCTOBER 2003D Undershoot Protection for Off-Isolation on A and B Ports Up To −2 VD Bidirectional Data Flow, With Near-Zero Propagation DelayD Low ON-State Resistance (r on )Characteristics (r on = 3 Ω Typical)D Low Input/Output Capacitance Minimizes Loading and Signal Distortion (C io(OFF) = 5 pF Typical)D Data and Control Inputs Provide Undershoot Clamp Diodes D Low Power Consumption (I CC = 3 µA Max)D V CC Operating Range From 4 V to 5.5 V DData I/Os Support 0 to 5-V Signaling Levels (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)D Control Inputs Can Be Driven by TTL or 5-V/3.3-V CMOS OutputsD I off Supports Partial-Power-Down Mode OperationD Latch-Up Performance Exceeds 100 mA Per JESD 78, Class IIDESD Performance Tested Per JESD 22− 2000-V Human-Body Model (A114-B, Class II)− 1000-V Charged-Device Model (C101)DSupports Both Digital and AnalogApplications: USB Interface, Bus Isolation,Low-Distortion Signal GatingD OR PW PACKAGE(TOP VIEW)123487651OE 1A 1B GNDV CC 2OE 2B 2Adescription/ordering informationThe SN74CBT3306C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (r on ),allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the SN74CBT3306C provides protection for undershoot up to −2 V by sensing an undershoot event and ensuring that the switch remains in the proper OFF state.The SN74CBT3306C is organized as two 1-bit bus switches with separate output-enable (1OE, 2OE) inputs.It can be used as two 1-bit bus switches or as one 2-bit bus switch. When OE is low, the associated 1-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 1-bit bus switch is OFF, and the high-impedance state exists between the A and B ports.ORDERING INFORMATIONT APACKAGE †ORDERABLE PART NUMBER TOP-SIDE MARKING Tube SN74CBT3306CD SOIC − DTape and reel SN74CBT3306CDR CU306C −40°C to 85°CTube SN74CBT3306CPW TSSOP − PWTape and reelSN74CBT3306CPWRCU306C†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at /sc/package.Copyright 2003, Texas Instruments IncorporatedPlease be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.SN74CBT3306CDUAL FET BUS SWITCH5ĆV BUS SWITCH WITH ć2ĆV UNDERSHOOT PROTECTIONSCDS127A − SEPTEMBER 2003 − REVISED OCTOBER 2003description/ordering information (continued)This device is fully specified for partial-power-down applications using I off . The I off feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off.To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.FUNCTION TABLE (each bus switch)INPUT INPUT/OUTPUTOE AFUNCTION L B A port = B port HZDisconnectlogic diagram (positive logic)1A 1OESW1B2A 2OESW2B215736simplified schematic, each FET switch (SW)AEN †B†EN is the internal enable signal applied to the switch.Undershoot Protection CircuitSN74CBT3306CDUAL FET BUS SWITCH5ĆV BUS SWITCH WITH ć2ĆV UNDERSHOOT PROTECTIONSCDS127A − SEPTEMBER 2003 − REVISED OCTOBER 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Supply voltage range, V CC−0.5 V to 7 V Control input voltage range, V IN (see Notes 1 and 2) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Switch I/O voltage range, V I/O (see Notes 1, 2, and 3) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Control input clamp current, I IK(V IN< 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I/O port clamp current, I I/OK(V I/O< 0) −50 mA ON-state switch current, I I/O (see Note 4) ±128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Continuous current through V CC or GND terminals ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Package thermal impedance, θJA (see Note 5):D package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PW package 149°C/W Storage temperature range, T stg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.NOTES: 1.All voltages are with respect to ground unless otherwise specified.2.The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.3.V I and V O are used to denote specific conditions for V I/O.4.I I and I O are used to denote specific conditions for I I/O.5.The package thermal impedance is calculated in accordance with JESD 51-7.recommended operating conditions (see Note 6)MIN MAX UNITV CC Supply voltage4 5.5VV IH High-level control input voltage2 5.5VV IL Low-level control input voltage00.8VV I/O Data input/output voltage0 5.5VT A Operating free-air temperature−4085°C NOTE 6:All unused control inputs of the device must be held at V CC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.SN74CBT3306CDUAL FET BUS SWITCH5ĆV BUS SWITCH WITH ć2ĆV UNDERSHOOT PROTECTIONSCDS127A − SEPTEMBER 2003 − REVISED OCTOBER 2003electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)PARAMETER TEST CONDITIONS MINTYP †MAX UNIT V IK Control inputs V CC = 4.5 V,I IN = −18 mA−1.8V V IKU Data inputs V CC = 5 V,0 mA > I I ≥ −50 mA,V IN = V CC or GND,Switch OFF−2V I IN Control inputsV CC = 5.5 V,V IN = V CC or GND ±1µA I OZ ‡V CC = 5.5 V,V O = 0 to 5.5 V,V I = 0,Switch OFF,V IN = V CC or GND ±10µA I off V CC = 0,V O = 0 to 5.5 V,V I = 010µA I CC V CC = 5.5 V,I I/O = 0,V IN = V CC or GND,Switch ON or OFF3µA ∆I CC §Control inputs V CC = 5.5 V,One input at 3.4 V,Other inputs at V CC or GND2.5mA C in Control inputs V IN = 3 V or 0 3.5pF C io(OFF)V I/O = 3 V or 0,Switch OFF,V IN = V CC or GND 5pF C io(ON)V I/O = 3 V or 0,Switch ON,V IN = V CC or GND 12.5pFV CC = 4 V,TYP at V CC = 4 VV I = 2.4 V,I O = −15 mA 812on ¶V I O = 64 mA 36r V I = 0I O = 30 mA36ΩCC = 4.5 VV I = 2.4 V,I O = −15 mA 510V IN and I IN refer to control inputs. V I , V O , I I , and I O refer to data pins.†All typical values are at V CC = 5 V (unless otherwise noted), T A = 25°C.‡For I/O ports, the parameter I OZ includes the input leakage current.§This is the increase in supply current for each input that is at the specified voltage level, rather than V CC or GND.¶Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two (A or B) terminals.switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)FROM TO V CC = 4 V V CC = 5 V ± 0.5 V PARAMETER(INPUT)(OUTPUT)MINMAX MINMAX UNITt pd # A or B B or A 0.240.15ns t en OE A or B 4.6 1.5 4.2ns t disOEA or B4.31.5 4.3ns #The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance,when driven by an ideal voltage source (zero output impedance).SN74CBT3306CDUAL FET BUS SWITCH5ĆV BUS SWITCH WITH ć2ĆV UNDERSHOOT PROTECTIONSCDS127A − SEPTEMBER 2003 − REVISED OCTOBER 2003undershoot characteristics (see Figures 1 and 2)PARAMETERTEST CONDITIONSMIN TYP †MAXUNIT V OUTU V CC = 5.5 V,Switch OFF,V IN = V CC or GND2V OH −0.3V†All typical values are at V CC = 5 V (unless otherwise noted), T A = 25°C.Figure 1. Device Test Setup50 ΩV SV CC11 V 100 k Ω100 k Ω10 pFDUTInputGeneratorAxBxFigure 2. Transient Input Voltage (V I ) and OutputVoltage (V OUTU ) Waveforms(Switch OFF)−2 V5.5 V10 %20 ns10 %90 %90 %2 ns2 nsV OH − 0.3V OHOutput (V OUTU )Input (Open Socket)SN74CBT3306CDUAL FET BUS SWITCH5ĆV BUS SWITCH WITH ć2ĆV UNDERSHOOT PROTECTIONSCDS127A − SEPTEMBER 2003 − REVISED OCTOBER 2003PARAMETER MEASUREMENT INFORMATIONV OH V OLC L(see Note A)TEST CIRCUITS17 VOpen GNDR LR Lt PLH t PHLOutput Waveform 1S1 at 7 V (see Note B)Output Waveform 2S1 at Open (see Note B)t PZLt PZHt PLZt PHZ 3 V0 V V OH V OL0 VV OL + V ∆V OH − V ∆0 VOutput Control (V IN )3 V3.5 VVOLTAGE WAVEFORMSPROPAGATION DELAY TIMES (t pd(s))VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMESOutputNOTES: A.C L includes probe and jig capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, Z O = 50 Ω, t r ≤2.5 ns, t f ≤2.5 ns.D.The outputs are measured one at a time with one transition per measurement.E.t PLZ and t PHZ are the same as t dis .F.t PZL and t PZH are the same as t en .G.t PLH and t PHL are the same as t pd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-stateresistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).H.All parameters and waveforms are not applicable to all devices.1.5 V1.5 V1.5 V1.5 V1.5 V 1.5 V1.5 V1.5 V50 ΩV G1V CCDUT50 ΩV IN50 ΩV G250 ΩV ITEST R L S1V ∆C L 5 V ±0.5 V4 V V CC V I t PHZ /t PZHt PLZ /t PZL t pd(s) 5 V ±0.5 V4 V5 V ±0.5 V4 VOpen Open 7 V 7 V Open Open500 Ω500 Ω500 Ω500 Ω500 Ω500 ΩV CC or GND V CC or GNDGND GND V CC V CC 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF0.3 V 0.3 V 0.3 V 0.3 VOutput Control (V IN )Input GeneratorInput GeneratorV OFigure 3. Test Circuit and Voltage WaveformsPACKAGING INFORMATION(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement.(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andAddendum-Page 1continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.Addendum-Page 2TAPE AND REEL INFORMATION*All dimensions are nominalDevicePackage Type Package Drawing Pins SPQReel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant SN74CBT3306CDR SOIC D 82500330.012.4 6.4 5.2 2.18.012.0Q1SN74CBT3306CPWR TSSOP PW 82000330.012.47.0 3.6 1.68.012.0Q1SN74CBT3306CPWRTSSOPPW82000330.012.47.03.61.68.012.0Q1*All dimensions are nominalDevice Package Type Package Drawing Pins SPQ Length(mm)Width(mm)Height(mm) SN74CBT3306CDR SOIC D8*******.5336.125.0 SN74CBT3306CPWR TSSOP PW82000367.0367.035.0SN74CBT3306CPWR TSSOP PW82000364.0364.027.0TUBE*All dimensions are nominalDevice Package NamePackage TypePins SPQ L (mm)W (mm)T (µm)B (mm)SN74CBT3306CD D SOIC 87550783940 4.32SN74CBT3306CPWPWTSSOP815053010.236003.5PACKAGE MATERIALS INFORMATION5-Jan-2022PACKAGE OUTLINESOIC - 1.75 mm max heightD0008ASMALL OUTLINE INTEGRATED CIRCUITNOTES:1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M.2. This drawing is subject to change without notice.3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side.4. This dimension does not include interlead flash.5. Reference JEDEC registration MS-012, variation AA.EXAMPLE BOARD LAYOUTSOIC - 1.75 mm max heightD0008ASMALL OUTLINE INTEGRATED CIRCUITNOTES: (continued)6. Publication IPC-7351 may have alternate designs.7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.EXAMPLE STENCIL DESIGNSOIC - 1.75 mm max heightD0008ASMALL OUTLINE INTEGRATED CIRCUITNOTES: (continued)8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.9. Board assembly site may have different recommendations for stencil design.PACKAGE OUTLINETSSOP - 1.2 mm max heightPW0008ASMALL OUTLINE PACKAGENOTES:1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.2. This drawing is subject to change without notice.3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.5. Reference JEDEC registration MO-153, variation AA.EXAMPLE BOARD LAYOUT PW0008ATSSOP - 1.2 mm max heightSMALL OUTLINE PACKAGE ArrayNOTES: (continued)6. Publication IPC-7351 may have alternate designs.7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.EXAMPLE STENCIL DESIGN PW0008ATSSOP - 1.2 mm max heightSMALL OUTLINE PACKAGE ArrayNOTES: (continued)8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternatedesign recommendations.9. Board assembly site may have different recommendations for stencil design.IMPORTANT NOTICE AND DISCLAIMERTI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements.These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources.TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on or provided in conjunction with such TI products. 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Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself.Renesas Technology Home Page: Renesas Technology Corp.Customer Support Dept.April 1, 2003CautionsKeep safety first in your circuit designs!1. Renesas Technology Corporation puts the maximum effort into making semiconductor products betterand more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.Notes regarding these materials1. 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If these products or technologies are subject to the Japanese export control restrictions, they must beexported under a license from the Japanese government and cannot be imported into a country other than the approved destination.Any diversion or reexport contrary to the export control laws and regulations of Japan and/or thecountry of destination is prohibited.8. Please contact Renesas Technology Corporation for further details on these materials or the productscontained therein.HA17431 SeriesShunt RegulatorADE-204-049A (Z)Rev.1Sep. 2002 DescriptionThe HA17431 series is temperature-compensated variable shunt regulators. The main application of these products is in voltage regulators that provide a variable output voltage. The on-chip high-precisionmax of 16 volts. reference voltage source can provide ±1% accuracy in the V versions, which have a VKAThe HA17431VLP, which is provided in the MPAK-5 package, is designed for use in switching mode power supplies. It provides a built-in photocoupler bypass resistor for the PS pin, and an error amplifier can be easily constructed on the supply side.Features•The V versions provide 2.500 V ±1% at Ta = 25°C•The HA17431VLP includes a photocoupler bypass resistor (2 kΩ)•The reference voltage has a low temperature coefficient•The MPAK-5(5-pin), MPAK(3-pin) and UPAK miniature packages are optimal for use on high mounting density circuit boards•Car use is providedBlock DiagramHA17431 SeriesRev.1, Sep. 2002, page 2 of 24Application Circuit ExampleOrdering InformationVersionItemV VersionA Version Normal VersionPackage Operating Temperature Range Accuracy ±1% ±2.2% ±4% Max 2.525 V 2.550 V 2.595 V Typ 2.500 V 2.495 V 2.495 V Reference voltage (at 25°C)Min2.475 V 2.440 V 2.395 V Cathode voltage 16 V max 40 V max 40 V max Cathode current 50 mA max150 mA max150 mA maxHA17431VPJHA17431PNAJTO-92HA17431PAJ HA17431PJ TO-92MOD HA17431FPAJ Car useHA17431FPJFP-8D –40 to +85°CHA17431 SeriesRev.1, Sep. 2002, page 3 of 24Ordering Information (cont.)VersionItemV VersionA VersionNormal VersionPackage Operating Temperature Range HA17431VLTP HA17432VLTP MPAKHA17431VLP MPAK-5 HA17431VP HA17431PNA TO-92 HA17431VUP HA17431UPA HA17432VUPHA17432UPAUPAK HA17431PA HA17431P TO-92MOD HA17431FPA Industrial useHA17431FPFP-8D HA17431UA Commercial use HA17432UAUPAK –20 to +85°CPin ArrangementHA17431 SeriesRev.1, Sep. 2002, page 4 of 24Absolute Maximum Ratings(Ta = 25°C)Item Symbol HA17431VLP HA17431VP HA17431VPJ Unit Notes Cathode voltage V KA 16 16 16 V 1 PS term. voltage V PS V KA to 16 — — V 1,2,3Continuous cathode current I K –50 to +50 –50 to +50 –50 to +50 mA Reference input currentIref–0.05 to +10–0.05 to +10–0.05 to +10mAPower dissipation P T 150 *4 500 *5 500 *5 mW 4, 5 Operating temperature range Topr–20 to +85–20 to +85–40 to +85°CStorage temperatureTstg –55 to +150 –55 to +150 –55 to +150 °CItem Symbol HA17431VUP/HA17432VUP HA17431VLTP/HA17432VLTP Unit Notes Cathode voltage V KA 16 16V 1PS term. voltage V PS — — V 1,2,3 Continuouscathode current I K –50 to +50 –50 to +50 mA Reference input currentIref–0.05 to +10–0.05 to +10mAPower dissipation P T 800 *8 150 *4 mW 4, 8 Operating temperature range Topr–20 to +85–20 to +85°CStorage temperatureTstg –55 to +150 –55 to +150 °CItemSymbol HA17431PNA HA17431P/PAHA17431FP/FPA HA17431UA/UPA/ HA17432UA/UPAUnitNotes Cathode voltage V KA 4040 40 40 V 1Continuous cathode current I K –100 to +150 –100 to +150 –100 to +150 –100 to +150 mA Reference input currentIref–0.05 to +10–0.05 to +10–0.05 to +10–0.05 to +10mAPower dissipation P T 500 *5 800 *6 500 *7 800 *8 mW 5,6,7,8 Operating temperature range Topr–20 to +85–20 to +85–20 to +85–20 to +85°CStorage temperatureTstg –55 to +150 –55 to +150 –55 to +125 –55 to +150 °CHA17431 SeriesRev.1, Sep. 2002, page 5 of 24Absolute Maximum Ratings (cont.)(Ta = 25°C)Item Symbol HA17431PNAJ HA17431PJ/PAJ HA17431FPJ/FPAJ Unit Notes Cathode voltage V KA 40 40 40 V 1 Continuous cathode current I K –100 to +150 –100 to +150 –100 to +150 mA Reference input currentIref–0.05 to +10–0.05 to +10–0.05 to +10mAPower dissipation P T 500 *5 800 *6 500 *7 mW 5,6,7 Operating temperature range Topr–40 to +85–40 to +85–40 to +85°CStorage temperatureTstg –55 to +150 –55 to +150 –55 to +125 °CNotes: 1. Voltages are referenced to anode.2. The PS pin is only provided by the HA17431VLP.3. The PS pin voltage must not fall below the cathode voltage. If the PS pin is not used, the PS pinis recommended to be connected with the cathode.4. Ta ≤ 25°C. If Ta > 25°C, derate by 1.2 mW/°C.5. Ta ≤ 25°C. If Ta > 25°C, derate by 4.0 mW/°C.6. Ta ≤ 25°C. If Ta > 25°C, derate by 6.4 mW/°C.7. 50 mm × 50 mm × 1.5mmt glass epoxy board(5% wiring density), Ta ≤ 25°C. If Ta > 25°C,derate by 5 mW/°C.8. 15 mm × 25 mm × 0.7mmt alumina ceramic board,Ta ≤ 25°C. If Ta > 25°C, derate by 6.4mW/°C.HA17431 SeriesRev.1, Sep. 2002, page 6 of 24Electrical CharacteristicsHA17431VLP/VP/VPJ/VUP/VLTP, HA17432VUP/VLTP (Ta = 25°C, I K = 10 mA)Item Symbol Min Typ Max Unit Test Conditions Notes Reference voltage Vref 2.475 2.500 2.525 VV KA = VrefReference voltage temperature deviationVref(dev)— 10 — mV V KA = Vref,Ta = –20°C to +85°C 1Reference voltage temperature coefficient ∆Vref/∆Ta— ±30 — ppm/°C V KA = Vref,0°C to 50°C gradientReference voltage regulation ∆Vref/∆V KA — 2.0 3.7 mV/V V KA = Vref to 16 V Reference input currentIref — 2 6 µA R 1 = 10 k Ω, R 2 = ∞ Reference current temperature deviation Iref(dev)— 0.5 —µA R 1 = 10 k Ω, R 2 = ∞,Ta = –20°C to +85°CMinimum cathode currentImin — 0.4 1.0 mA V KA = Vref2 Off state cathode current Ioff — 0.001 1.0 µA V KA = 16 V, Vref = 0 V Dynamic impedance Z KA — 0.2 0.5 Ω V KA = Vref,I K = 1 mA to 50 mA Bypass resistance R PS 1.6 2.0 2.4 k ΩI PS = 1 mA3 Bypass resistance temperature coefficient ∆R PS /∆Ta— +2000 — ppm/°C I PS = 1 mA,0°C to 50°C gradient3HA17431 SeriesRev.1, Sep. 2002, page 7 of 24Electrical Characteristics (cont.)HA17431PJ/PAJ/FPJ/FPAJ/P/PA/UA/UPA/FP/FPA/PNA/PNAJ, HA17432UA/UPA (Ta = 25°C, I K = 10 mA)Item Symbol Min Typ Max Unit Test Conditions Notes 2.440 2.495 2.550 A Reference voltage Vref 2.395 2.495 2.595 V V KA = Vref Normal —11(30)Ta =–20°C to +85°C 1, 4Reference voltage temperature deviationVref(dev)— 5 (17)mV V KA = VrefTa = 0°C to +70°C1, 4 — 1.4 3.7 V KA = Vref to 10 V Reference voltage regulation ∆Vref/∆V KA — 1 2.2mV/V V KA = 10 V to 40 VReference input currentIref — 3.8 6 µA R 1 = 10 k Ω, R 2 = ∞ Reference current temperature deviation Iref(dev)— 0.5 (2.5) µA R 1 = 10 k Ω, R 2 = ∞,Ta = 0°C to +70°C 4Minimum cathode currentImin — 0.4 1.0 mA V KA = Vref2 Off state cathode current Ioff — 0.001 1.0 µA V KA = 40 V, Vref = 0 V Dynamic impedanceZ KA— 0.2 0.5 ΩV KA = Vref,I K = 1 mA to 100 mANotes: 1. Vref(dev) = Vref(max) – Vref(min)2. Imin is given by the cathode current at Vref = Vref (IK=10mA) – 15 mV.3. R PS is only provided in HA17431VLP.4. The maximum value is a design value (not measured).HA17431 SeriesRev.1, Sep. 2002, page 8 of 24MPAK-5(5-pin), MPAK(3-pin) and UPAK Marking PatternsThe marking patterns shown below are used on MPAK-5, MPAK and UPAK products. Note that the product code and mark pattern are different. The pattern is laser-printed.Notes: 1. Boxes (1) to (5) in the figures show the position of the letters or numerals, and are not actuallymarked on the package.2. The letters (1) and (2) show the product specific mark pattern.Product (1)(2) HA17431VLP 4 P HA17431VUP 4 R HA17432VUP 4 S HA17431VLTP 3 A HA17432VLTP 3 B HA17431UA 4 A HA17431UPA 4 B HA17432UA 4 C HA17432UPA 4F3. The letter (3) shows the production year code (the last digit of the year) for UPAK products.4. The bars (a), (b) and (c) show a production year code for MPAK-5 and MPAK products as shownbelow. After 2010 the code is repeated every 8 years.Year 2002 2003 2004 2005 2006 2007 2008 2009 (a) None None None Bar Bar Bar Bar None (b) None Bar Bar None None Bar Bar None (c) Bar None Bar None Bar None Bar None5. The letter (4) shows the production month code (see table below).Production month Jan. Feb. Mar. Apr. May. Jun. Jul. Aug. Sep. Oct. Nov. Dec. Marked code A B C D E F G H J K L M6. The letter (5) shows manufacturing code. For UPAK products.Characteristics CurvesHA17431VLP/VP/VPJ/VUP/VLTP, HA17432VUP/VLTPHA17431PJ/PAJ/FPJ/FPAJ/P/PA/UA/UPA/FP/FPA/PNA/PNAJ, HA17432UA/UPAApplication ExamplesAs shown in the figure on the right, this IC operates as an inverting amplifier, with the REF pin as input pin. The open-loop voltage gain is given by the reciprocal of “reference voltage deviation by cathodevoltage change ” in the electrical specifications, and is approximately 50 to 60 dB. The REF pin has a high input impedance, with an input current Iref of 3.8 µA Typ (V version: Iref = 2 µA Typ). The outputimpedance of the output pin K (cathode) is defined as dynamic impedance Z KA , and Z KA is low (0.2 Ω) over a wide cathode current range. A (anode) is used at the minimum potential, such as ground.Figure 1 Operation DiagramApplication HintsNo. Application Example Description1Reference voltage generation circuitVoutGND VinGNDThis is the simplest reference voltage circuit. The valueof the resistance R is set so that cathode current I K ≥ 1 mA.Output is fixed at Vout ≅ 2.5 V.The external capacitor C L (C L ≥ 3.3 µF) is used to prevent oscillation in normal applications.2 Variable output shunt regulator circuitThis is circuit 1 above with variable output provided.Vout ≅ 2.5 V ×Here,(R 1 + R 2)R 2Since the reference input current Iref = 3.8 µA Typ (V version: Iref = 2 µA Typ) flows through R 1, resistance values are chosen to allow the resultant voltage drop to be ignored.3Single power supply invertingcomparator circuitThis is an inverting type comparator with an input threshold voltage of approximately 2.5 V. Rin is the REF pin protection resistance, with a value of several k Ω to several tens of k Ω.R L is the load resistance, selected so that the cathode current I K • 1 mA when Vout is low.Condition C1C2Vin Less then 2.5 V 2.5 V or moreVout V CC (V OH )Approx. 2 V (V OL )ICOFF ON4 AC amplifier circuitGain G =(DC gain)R 1R 2 // R 3Cutoff frequency fc =12π Cf (R 1 // R 2 // R 3)This is an AC amplifier with voltage gain G = –R 1 / (R 2//R 3). The input is cut by capacitance Cin, so that the REF pin is driven by the AC input signal, centered on 2.5 V DC .R 2 also functions as a resistance that determines the DC cathode potential when there is no input, but if the input level is low and there is no risk of Vout clipping to V CC , this can be omitted.To change the frequency characteristic, Cf should be connected as indicated by the dotted line.5Switching power supply erroramplification circuit12Note:LED R3R4: Light emitting diode in photocoupler : Bypass resistor to feed IK(>Imin) when LED current vanishes : LED protection resistanceThis circuit performs control on the secondary side of a transformer, and is often used with a switching power supply that employs a photocoupler for offlining.The output voltage (between V+ and V –) is given by the following formula:Vout ≅ 2.5 V ×(R 1 + R 2)R 2In this circuit, the gain with respect to the Vout error is as follows:G =×R 2(R 1 + R 2)HA17431 open loop gain ×photocoupler total gainAs stated earlier, the HA17431 open-loop gain is 50 to60 dB.6Constant voltage regulator circuitV CCVoutGNDGNDThis is a 3-pin regulator with a discrete configuration, inwhich the output voltageVout = 2.5 V ×(R 2 + R 3)R 3R 1 is a bias resistance for supplying the HA17431 cathode current and the output transistor Q base current.7Discharge type constant current circuitV SI LThis circuit supplies a constant current ofI L ≅[A] into the load. Caution is required2.5 V R Ssince the HA17431 cathode current is also superimposed on IL .The requirement in this circuit is that the cathode current must be greater than Imin = 1 mA. The I Lsetting therefore must be on the order of several mA or more.8Induction type constant current circuitV I L SIn this circuit, the load is connected on the collector side of transistor Q in circuit 7 above. In this case, the load floats from GND, but the HA17431 cathode current is not superimposed on I L , so that I L can be kept small (1 mA or less is possible). The constant current value is the same as for circuit 7 above:I L ≅[A]2.5 V R SDesign Guide for AC-DC SMPS (Switching Mode Power Supply)Use of Shunt Regulator in Transformer Secondary Side ControlThis example is applicable to both forward transformers and flyback transformers. A shunt regulator is used on the secondary side as an error amplifier, and feedback to the primary side is provided via a photocoupler.Figure 2 Typical Shunt Regulator/Error AmplifierDetermination of External Constants for the Shunt RegulatorDC characteristic determination: In figure 2, R1 and R2are protection resistor for the light emitting diodein the photocoupler, and R2 is a bypass resistor to feed IKminimum, and these are determined as shownbelow. The photocoupler specification should be obtained separately from the manufacturer. Using the parameters in figure 2, the following formulas are obtained:R1 =V0– V F– V KI F + I B, R2 =V FI BVKis the HA17431 operating voltage, and is set at around 3 V, taking into account a margin for fluctuation.R2 is the current shunt resistance for the light emitting diode, in which a bias current IBof around 1/5 IFflows.Next, the output voltage can be determined by R3 and R4, and the following formula is obtained:V0 =R3 + R4R4× Vref, Vref = 2.5 V TypThe absolute values of R3 and R4are determined by the HA17431 reference input current Iref and the ACcharacteristics described in the next section. The Iref value is around 3.8 µA Typ. (V version: 2 µA Typ)AC characteristic determination: This refers to the determination of the gain frequency characteristic of the shunt regulator as an error amplifier. Taking the configuration in figure 2, the error amplifier characteristic is as shown in figure 3.Figure 3 HA17431 Error Amplification CharacteristicIn Figure 3, the following formulas are obtained: GainG 1 = G 0 ≈ 50 dB to 60 dB (determined by shunt regulator)G 2 =R 5R 3Corner frequenciesf 1 = 1/(2π C 1 G 0 R 3) f 2 = 1/(2π C 1 R 5)G 0 is the shunt regulator open-loop gain; this is given by the reciprocal of the reference voltage fluctuation ∆Vref/∆V KA , and is approximately 50 dB.Practical ExampleConsider the example of a photocoupler, with an internal light emitting diode V F = 1.05 V and I F = 2.5 mA, power supply output voltage V 2 = 5 V, and bias resistance R 2 current of approximately 1/5 I F at 0.5 mA. If the shunt regulator V K = 3 V, the following values are found.R 1 =5V – 1.05V – 3V2.5mA + 0.5mA= 316(Ω) (330Ω from E24 series)R 2 =1.05V0.5mA= 2.1(k Ω) (2.2k Ω from E24 series)Next, assume that R 3 = R 4 = 10 k Ω. This gives a 5 V output. If R 5 = 3.3 k Ω and C 1 = 0.022 µF, the following values are found.G 2 = 3.3 k Ω / 10 k Ω = 0.33 times (–10 dB) f 1 = 1 / (2 × π × 0.022 µF × 316 × 10 k Ω) = 2.3 (Hz) f 2 = 1 / (2 × π × 0.022 µF × 3.3 k Ω) = 2.2 (kHz)Package DimensionsDisclaimer1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2.Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use.3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support.4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installationconditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant.6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi.7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products.Sales OfficesHitachi, Ltd.Semiconductor & Integrated CircuitsNippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: (03) 3270-2111 Fax: (03) 3270-5109Copyright © Hitachi, Ltd., 2002. All rights reserved. Printed in Japan.Hitachi Asia Ltd. Hitachi Tower16 Collyer Quay #20-00 Singapore 049318Tel : <65>-6538-6533/6538-8577 Fax : <65>-6538-6933/6538-3877URL : .sg URL /Hitachi Asia Ltd.(Taipei Branch Office)4/F, No. 167, Tun Hwa North Road Hung-Kuo Building Taipei (105), Taiwan Tel : <886>-(2)-2718-3666 Fax : <886>-(2)-2718-8180 Telex : 23222 HAS-TPURL : Hitachi Asia (Hong Kong) Ltd.Group III (Electronic Components) 7/F., North TowerWorld Finance Centre,Harbour City, Canton RoadTsim Sha Tsui, Kowloon Hong Kong Tel : <852>-2735-9218 Fax : <852>-2730-0281URL : Hitachi Europe GmbHElectronic Components Group Dornacher Straße 3D-85622 FeldkirchenPostfach 201, D-85619 Feldkirchen GermanyTel: <49> (89) 9 9180-0Fax: <49> (89) 9 29 30 00Hitachi Europe Ltd.Electronic Components Group Whitebrook ParkLower Cookham Road MaidenheadBerkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000Fax: <44> (1628) 585200Hitachi Semiconductor (America) Inc.179 East Tasman Drive San Jose,CA 95134 Tel: <1> (408) 433-1990Fax: <1>(408) 433-0223For further information write to:Colophon 6.0。
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NJW21194NJW21193/D (90.0kB)Pb-freeActive NJX1675P NJX1675P/D (380.0kB)Pb-freeHalide freeActive NS2029M3NS2029M3/D (69.0kB)Pb-freeHalide freeActive NSS1C200NSS1C200MZ4/D (100.0kB)Pb-freeHalide freeActive NSS40300NSS40300MZ4/D (109.0kB)Pb-freeHalide freeActive。