5STP20F1201中文资料

System OverviewThe processor core has three ports and can generate up to the following simultaneous off-core accesses per core clock cycle (CCLK):•One DMA data transfer through the D port•One L2 or external memory access through the P port•One MMR register access through the MMR portThe L2 or external memory access through the P port includes normal data or instruction access and cache read or write operation. System OverviewThe ADSP-BF54x processor processor system includes a Blackfin proces-sor core, a 128K byte level 2 (L2) memory, the peripheral set (seeFigure2-1 on page2-3), the external memory controller (EBIU, AMC and DDR), the DMA controllers, and bus interfaces.The external bus interface unit (EBIU) is the primary interface to the chip pins. Detailed information about the EBIU is discussed in “External Bus Interface Unit” on page5-1.P Port InterfaceFigure2-3 shows the interface between the processor core P port andmemory other than L1 through the 64-bit core L2 bus and shows theinterface between processor core P port and the EBIU through the 32-bit EAB bus.ADSP-BF54x Blackfin Processor Hardware ReferenceNFC Programming ExamplesP1 = (2048/256)(z);R3.L = lo(_Buffer);R3.H = hi(_Buffer);R4 = (2048/4)(z);R5 = 0x4(x);[P4 + (DMA22_START_ADDR - DMA22_CONFIG)] = R3;w[P4 + lo(DMA22_X_COUNT - DMA22_CONFIG)] = R4;w[P4 + lo(DMA22_X_MODIFY - DMA22_CONFIG)] = R5;R7 = 0x89(z);w[P4] = R7;LSETUP(_write_data_begin, _write_data_end) LC0 = P1;_write_data_begin:P1 = (256/4)(z);/* Reset the NFC */R7 = ECC_RST(z);w[P5 + lo(NFC_RST - NFC_CTL)] = R7;ssync;_wait_for_nfc_reset_completion:R7 = w[P5 + lo(NFC_RST - NFC_CTL)](z);CC = bittst(R7, bitpos(ECC_RST));_wait_for_nfc_reset_completion.END:if CC jump _wait_for_nfc_reset_completion;R7 = PG_WR_START(x);w[P5 + lo(NFC_PGCTL - NFC_CTL)] = R7;ADSP-BF54x Blackfin Processor Hardware Reference。

Fixed Frequency White LED Step-Up ConverterFeaturesInherently Matched LED Current High Efficiency: 87%Drives Up to Five LEDs from 2.5V Supply 24V Internal Power SwitchFast 1MHz Switching Frequency Uses Tiny 1mm Tall InductorsRequires Only 1µF Output Capacitors19.5V Over Voltage Protection SOT-23-6 and TSOT-23-6 PackageApplicationsWhite LED Backlight Display for PDA Pocket PC Smart PhonesHandheld Devices Cellular PhonesGeneral DescriptionThe G5121 is a step-up DC/DC converter specifically designed to drive up to 5 series white LEDs with con-stant current. Series connection of the LEDs provides identical LED currents resulting in uniform brightness and eliminates the need for ballast resistors. The G5121 switches at 1MHz, allowing the use of tiny ex-ternal components. A low 0.254V feedback voltage minimizes power loss in the current setting resistor for high efficiency. The OVP pin monitors the output volt-age and turns off the converter whenever the LEDs are open.The G5121 is available in low profile SOT-23-6 and TSOT-23-6 package.Ordering InformationORDER NUMBERMARKINGTEMP. RANGE PACKAGE (Pb free)G5121TB1U 5121x -40°C ~ +85°C SOT-23-6G5121TP1U5121x -40°C ~ +85°C TSOT-23-6Note:TB: SOT23-6 TP: TSOT-23-6 1: Bonding CodeU: Tape & ReelPin ConfigurationTypical Application CircuitVCCSHDNSOT-23-6/TSOT-23-6C1:TAIYO YUDEN, JMK212BJ475KD SWGND FB OVPC2:TAIYO YUDEN, TMK316BJ105KDG5121Absolute Maximum RatingsVCC, SHDN to GND. . . . . . . . . . . . . . . . .-0.3V to +7V FB to GND. . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to VCC SW, OVP to GND. . . . . . . . . . . . . . . . . . . -0.3V to +24V Operating Temperature . . . . . . . . . . . . . .-40°C to 85°C Junction Temperature. . . . . . . . . . . . . . . . . . . . . .125°C Storage Temperature . . . . . . . . . . . . . ..-65°C to 150°C Reflow Temperature (soldering, 10sec) . . . . . . . 260°C ESD Rating (Human Body Model) . . . . . . . . . . . . . .2kVStress beyond those listed under “Absolute Maximum Rating” may cause permanent damage to the device. Electrical Characteristics(V CC=V SHDN=3.6V, T A=25°C)Typical Performance Characteristics(V CC= +3.6V, V SHDN= +3.6V, L=4.7µH, T A=25°C, unless otherwise noted.)Stability for Driving 5 WLEDs Stability for Driving 4 WLEDsStability for Driving 3 WLEDs Stability for Driving 2 WLEDsInrush Current for Driving 5 WLEDs Inrush Current for Driving 4 WLEDsInrush Current for Driving 3 WLEDsInrush Current for Driving 2 WLEDsOVP Waveform Dimming Control for Driving 4 WLEDsRecommended Minimum FootprintBlock DiagramGNDSHDN VCCSOT-23-6/TSOT-23-6Pin DescriptionFunction DescriptionNormal OperationThe G5121 uses a constant frequency control scheme to provide excellent line and load regulation. Operation can be best understood by referring to the block dia-gram. At the start of each oscillator cycle, the SR latch is set, which turns on the power switch M1. An artificial ramp is generated to the positive terminal of the PWM comparator A2. When this voltage exceeds the level at the negative input of A2, the SR latch is reset turning off the power switch. The level at the negative input of A2 is set by the error amplifier A1, and is simply an amplified version of the difference between the feed-back voltage and the reference voltage of 0.254V. In this manner, the error amplifier sets the correct peak current level to keep the output in regulation. If the error amplifier’s output increases, more current is de-livered to the output, if it decreases, less current is delivered.Over Voltage ProtectionOver voltage protection function is designed to prevent the damage of internal NMOS switch in case the in-creased impedance of the LED load (include the LED opened). Once the device detects over voltage (typical 19.5V) at the output, the internal NMOS switch is kept off until the output voltage drops below 15V. Application InformationInductor SelectionA 4.7µF inductor is recommended for G5121 applica-tions. Small size and high efficiency are the major concerns for most G5121 applications. Inductor with low core losses and small DCR (cooper wire resis-tance) at 1MHz are good choice for G5121 applica-tions. Since the G5121 is designed to operate in discontinu-ous mode, the inductor current reaches zero during discharge phase. After the inductor current reaches zero, the switch pin exhibits ringing due to the LC tank circuit formed by the inductor in combination with switch and diode capacitance. This ringing is not harmful; far less spectral energy is contained in the ringing than in the switch transitions. The ringing can be damped by application of a 300Ω resistor across the inductor, although this will degrade efficiency. Capacitor SelectionThe small size of ceramic capacitors makes them suit-able for G5121 applications. X5R and X7R types are recommended because they retain their capacitance over wider voltage and temperature ranges than other types such as Y5V or Z5U. A minimum 1µF capacitor for output is required for most applications. Larger in-put/output capacitor minimizes input/output ripple. Diode SelectionSchottky diodes, with their low forward voltage drop and fast reverse recovery, are the ideal choices for G5121 applications. The forward voltage drop of a Schottky diode represents the conduction losses in the diode, while the diode capacitance (C T or C D) repre-sents the switching losses. For diode selection, both forward voltage drop and diode capacitance need to be considered. Schottky diodes with higher current ratings usually have lower forward voltage drop and larger diode capacitance, which can cause significant switching losses at the 1MHz switching frequency of the G5121. A Schottky diode rated at 500mA is suffi-cient for most G5121 applications.Package InformationSOT-23-6 (TB) PackageNote:1. Package body sizes exclude mold flash protrusions or gate burrs2. Tolerance ±0.1000 mm (4mil) unless otherwise specified3. Coplanarity: 0.1000mm4. Dimension L is measured in gage planeDIMENSION IN MM DIMENSION IN INCHSYMBOLMIN. NOM. MAX. MIN. NOM. MAX.A 1.00 1.10 1.30 0.039 0.043 0.051A1 0.00 ----- 0.10 0.000 ----- 0.004 A2 0.70 0.80 0.90 0.028 0.031 0.035 b 0.35 0.40 0.50 0.014 0.016 0.020 C 0.10 0.15 0.25 0.004 0.006 0.010 D 2.70 2.90 3.10 0.106 0.114 0.122 E 1.40 1.60 1.80 0.055 0.0630.071 e ----- 1.90(TYP) ----- ----- 0.075(TYP) ----- H 2.60 2.80 3.00 0.102 0.110 0.118 L 0.37 ------ ----- 0.015 ----- ----- θ1 1º 5º 9º 1º 5º 9ºTSOT-23-6 (TP) PackageNote:1. Dimension D does not include mold flash, protrusions or tate burrs. Mold flash, protrusions or gate burrs shall not exceed0.1mm PER end. Dimension E1 does not include interlead flash or protrusion. Interlead flash or protrusion shall not ex-ceed 0.15mm PER side.2. The package top may be smaller than the package bottom. Dimensions D and E1 are determined at the outermost ex-tremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mis-match between the top and bottom of the plastic body.DIMENSION IN MM DIMENSION IN INCHSYMBOLMIN. NOM. MAX. MIN. NOM. MAX.A 0.75 ----- 1.00 0.030 ----- 0.039A1 0.00 ----- 0.10 0.000 ----- 0.004 A2 0.70 0.75 0.80 0.028 0.030 0.031 b 0.35 ----- 0.51 0.014 ----- 0.020 C 0.10 ----- 0.25 0.004 ----- 0.010 D 2.80 2.90 3.00 0.110 0.114 0.118 E 2.60 2.80 3.00 0.102 0.1100.118 E1 1.50 1.60 1.70 0.059 0.063 0.067 e 0.95 BSC 0.0374 BSC e1 1.90 BSC 0.0748 BSCL 0.37 ----- ----- 0.015 ----- ----- y ----- ----- 0.10 ----- 0.004 θ1 0° ----- 8° 0° ----- 8°Taping SpecificationPACKAGE Q ’TY/REELSOT-23-6 3,000 ea TSOT-23-6 3,000 eaGMT Inc. does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and GMT Inc. reserves the right at any time without notice to change said circuitry and specifications.SOT-23-6 / TSOT-23-6Package Orientation。

Advanced Boot TechniquesADSP-BF54x Blackfin Processor Hardware ReferenceIf both the global BFLAG_WAKEUP and the block-specific BFLAG_QUICKBOOT flags are set, the boot kernel ignores those blocks. But since the BFLAG_INIT , BFLAG_CALLBACK , BFLAG_FINAL, and BFLAG_AUX flags are inter-nally cleared and the BFLAG_IGNORE flag is toggled, through doublenegation, the “ignore the ignore block” command instructs the boot ker-nel to process the block.Although the BFLAG_INIT flag is suppressed in quick boot, the user may not want to combine the BFLAG_INIT flag with the BFLAG_QUICKBOOT flag. The initialization code can interrogate the BFLAG_WAKEUP flag and execute conditional instructions. For more information see “Quickboot With Restore From SDRAM” on page 17-152.Indirect BootingThe processor’s boot kernel provides a control mechanism to let blocks either boot directly to their final destination or load to an intermediate storage place, then copy the data to the final destination in a second step. This feature is motivated by the following requirements.•Some boot modes such as TWI do not use DMA. They load data by core instruction. The core cannot access some memories directly (for example L1 instruction SRAM), or is less efficient than the DMA in accessing some memories (for example, externalSDRAM).•In some advanced booting scenarios, the core needs to access the boot data during the booting process, for example in processing decompression, decryption and checksum algorithms at boot time.The indirect booting option helps speed-up and simplify such sce-narios. Software accesses off-chip memory less efficiently andcannot access data directly if it resides in L1 instruction SRAM.Indirect booting is not a global setting. Every boot block can control its own processing by the BFLAG_INDIRECT flag in the block header.Media Transceiver Module (MXVR) 0, Lock Mechanism 0 is selected. If the LMECH bit is set to 1, Lock Mecha-nism 1 is selected. When the MXVR is in Slave Mode (MMSM = 0), theLMECH bit has no meaning. The LMECH bit is reset to 0.MXVR State (MXVR_STATE_0, MXVR_STATE_1) RegistersThe MXVR_STATE_x registers indicate the current state of the MXVR. All bits in the MXVR_STATE_x registers are read-only bits.Figure 29-2. MXVR State RegisterADSP-BF54x Blackfin Processor Hardware Reference。

UPF2012 12W, 2.0 GHz, 26V Broadband RF Power N-ChannelEnhancement-Mode Lateral MOSFETUPF2012Maximum RatingsRating SymbolValueUnit Drain to Source Voltage, gate connected to source BV DSS 65 VoltsGate to Source Voltage BV GSS +/-20 VoltsTotal Device Dissipation @ Tcase = 70o C Derate above 70o C P D20.00.2WattsW/o CStorage Temperature Range T STG-65 to +150 o COperating Junction Temperature T J 200 o CThermal CharacteristicsCharacteristics SymbolTypicalUnit Thermal Resistance, Junction to Case Θjc 4.0 / 3.8* o C/W*The 4.0 value applies to the 440095 package. The 3.8 value applies to the 440109 & 440178 packages.Electrical DC Characteristics (T C =25°C unless otherwise specified)Rating SymbolMinTypMaxUnitDrain to Source Voltage, gate connected to source (V GS = 0, I DS = 1mA) BV DSS 65 - -VoltsDrain to Source Leakage current (V DS = 26V, V GS = 0) I DSS - -0.5µAGate to Source Leakage current (V GS = 20V, V DS = 0) I GSS - -1.0µAThreshold Voltage (V DS = 10V, I DS = 1mA) V TH 2.03.05.0VoltsGate Quiescent Voltage (V DS = 26 V, I DS = 115mA) V GS(on) 3.0 4.0 5.3VoltsDrain to Source On Voltage (V GS = 10V, I DS = 200mA) V DS(on) - -0.21VoltsForward Transconductance (V DS = 10V, I D = 0.5A) G M-0.6 - SUPF2012AC Characteristics(T C =25°C unless otherwise specified)Rating SymbolMinTypMaxUnitInput Capacitance(V DS=26V, V GS=0V, freq= 1MHz) C ISS - 15-pFOutput capacitance(V DS= 26V, V GS=0V, freq= 1MHz) C OSS - 10-pFFeedback capacitance(V DS=26V, V GS=0V, freq= 1MHz C RSS - 0.7-pFRF and Functional Tests (Tc=25°C unless otherwise specified, Cree Microwave Broadband Fixture)Rating SymbolMinTypMaxUnitLinear Power Gain, Single Tone(V DS=26V, I DQ=96mA, P OUT=6W, f=1840 MHz) G L 12.515.5-dBCompressed Power Gain, Single Tone(V DS=26V, I DQ=96mA, P OUT =12W, f=1840 MHz) G P 13.015.0-dBDrain Efficiency, Single Tone(V DS=26V, I DQ=96mA, P OUT =12W, f=1840 MHz) ηD - 47 -%Intermodulation Distortion, Two Tone(V DS=26V, I DQ=96mA, P OUT =12W PEP, 37.78dBm f1=1840 MHz, f2=1840.1MHz) IMD - --30dBcLoad Mismatch Tolerance(V DS=26V, I DQ=96mA, P OUT =12W, f=1840 MHz)VSWR* 10:1 - - ΨNote (unless otherwise specified):1. Source and load impedance shall be 50 ohms.*No degradation in device performance after test.CAUTION - MOS Devices are susceptible to damage from Electrostatic Discharge (ESD). Appropriate precautions in handling, packaging and testing MOS devices must be observed.UPF2012 Disclaimer: Specifications are subject to change without notice. Cree Microwave, Inc. believes the information contained within this data sheet to be accurate and reliable. However, no responsibility is assumed by Cree Microwave for any infringement of patents or other rights of third partieswhich may result from its use. No license is granted by implication or otherwise under anypatent or patent rights of Cree Microwave. Cree Microwave makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose. “Typical” parameters are the average values expected by Cree Microwave in large quantities and are provided for information purposes only. These values can and do vary in different applications, and actual performance can vary over time. All operating parameters should be validated by customer’s technical experts for each application. Cree Microwave products are not designed, intended, or authorized for use as components in applications intended for surgical implant into the body or to support or sustain life, in applications in which the failure of the Cree product could result in personal injury or death, or in applications for planning, construction, maintenance or direct operation of a nuclear facility. Cree Microwave is a trademark and Cree and the Cree logo are registered trademarks of Cree, Inc.Contact Information:Cree Microwave, Inc.160 Gibraltar CourtSunnyvale, CA 94089-1319Sheryle Henson (Cree Microwave—Marketing Manager) 408-962-7783Tom Dekker (Cree Microwave—Sales Director) 919-313-5639。