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FQI5N80中文资料

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©2000 Fairchild Semiconductor International

September 2000

Rev. A, September 2000FQB5N80 / FQI5N80

QFETTM

FQB5N80 / FQI5N80

800V N-Channel MOSFET

General Description

These N-Channel enhancement mode power field effecttransistors are produced using Fairchild’s proprietary,planar stripe, DMOS technology.This advanced technology has been especially tailored tominimize on-state resistance, provide superior switchingperformance, and withstand high energy pulse in theavalanche and commutation mode. These devices are wellsuited for high efficiency switch mode power supply.Features

•4.8A, 800V, RDS(on) = 2.6Ω @VGS = 10 V•Low gate charge ( typical 25 nC)•Low Crss ( typical 11 pF)•Fast switching•100% avalanche tested•Improved dv/dt capability

Absolute Maximum Ratings TC = 25°C unless otherwise noted

Thermal Characteristics SymbolParameterFQB5N80 / FQI5N80UnitsVDSSDrain-Source Voltage800V

IDDrain Current - Continuous (TC = 25°C)4.8A- Continuous (TC = 100°C)3.04AIDMDrain Current - Pulsed(Note 1)19.2A

VGSSGate-Source Voltage± 30V

EASSingle Pulsed Avalanche Energy(Note 2)590mJ

IARAvalanche Current(Note 1)4.8A

EARRepetitive Avalanche Energy(Note 1)14mJ

dv/dtPeak Diode Recovery dv/dt(Note 3)4.0V/ns

PDPower Dissipation (TA = 25°C) *3.13WPower Dissipation (TC = 25°C)140W

- Derate above 25°C1.12W/°CTJ, TSTGOperating and Storage Temperature Range-55 to +150°C

TLMaximum lead temperature for soldering purposes,1/8" from case for 5 seconds300°C

SymbolParameterTypMaxUnitsRθJCThermal Resistance, Junction-to-Case--0.89°C/W

RθJAThermal Resistance, Junction-to-Ambient *--40°C/WRθJAThermal Resistance, Junction-to-Ambient--62.5°C/W

* When mounted on the minimum pad size recommended (PCB Mount)"35!

!!""

SD

G D2-PAKFQB Series I2-PAKFQI SeriesGSD

GSD元器件交易网www.cecb2b.com Rev. A, September 2000FQB5N80 / FQI5N80

(Note 4)

(Note 4, 5)

(Note 4, 5)

(Note 4)

©2000 Fairchild Semiconductor InternationalElectrical Characteristics TC = 25°C unless otherwise noted

Notes:1. Repetitive Rating : Pulse width limited by maximum junction temperature2. L = 48mH, IAS = 4.8A, VDD = 50V, RG = 25 Ω, Starting TJ = 25°C3. ISD ≤ 4.8A, di/dt ≤ 200A/µs, VDD ≤ BVDSS, Starting TJ = 25°C 4. Pulse Test : Pulse width ≤300µs, Duty cycle ≤2%5. Essentially independent of operating temperatureSymbolParameterTest ConditionsMinTypMaxUnits

Off Characteristics

BVDSSDrain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA800----V∆BVDSS/ ∆TJBreakdown Voltage Temperature Coefficient ID = 250 µA, Referenced to 25°C--0.9--V/°C

IDSSZero Gate Voltage Drain CurrentVDS = 800 V, VGS = 0 V----10µA

VDS = 640 V, TC = 125°C----100µA

IGSSFGate-Body Leakage Current, ForwardVGS = 30 V, VDS = 0 V ----100nA

IGSSRGate-Body Leakage Current, ReverseVGS = -30 V, VDS = 0 V -----100nA

On Characteristics

VGS(th)Gate Threshold Voltage VDS = VGS, ID = 250 µA3.0--5.0V

RDS(on)Static Drain-Source On-ResistanceVGS = 10 V, ID = 2.4 A --2.02.6Ω

gFSForward TransconductanceVDS = 50 V, ID = 2.4 A --4.9--S

Dynamic Characteristics

CissInput CapacitanceVDS = 25 V, VGS = 0 V, f = 1.0 MHz --9501250pF

CossOutput Capacitance--95125pF

CrssReverse Transfer Capacitance--1115pF

Switching Characteristics

td(on)Turn-On Delay TimeVDD = 400 V, ID = 4.8 A,RG = 25 Ω

--2255ns

trTurn-On Rise Time--60130ns

td(off)Turn-Off Delay Time--55120ns

tfTurn-Off Fall Time--4090ns

QgTotal Gate ChargeVDS = 640 V, ID = 4.8 A,VGS = 10 V --2533nC

QgsGate-Source Charge--5.6--nC

QgdGate-Drain Charge--12--nC

Drain-Source Diode Characteristics and Maximum Ratings

ISMaximum Continuous Drain-Source Diode Forward Current----4.8A

ISMMaximum Pulsed Drain-Source Diode Forward Current----19.2A

VSDDrain-Source Diode Forward VoltageVGS = 0 V, IS = 4.8 A ----1.4VtrrReverse Recovery TimeVGS = 0 V, IS = 4.8 A,dIF / dt = 100 A/µs --610--nsQrrReverse Recovery Charge--4.7--µC元器件交易网www.cecb2b.comFQB5N80 / FQI5N80

Rev. A, September 2000©2000 Fairchild Semiconductor International

0.20.40.60.81.01.210-1100101

150℃※ Notes : 1. VGS = 0V 2. 250μs Pulse Test25℃

IDR, Reverse Drain Current [A]

VSD, Source-Drain voltage [V]0369121512345

VGS = 20VVGS = 10V

※ Note : TJ = 25℃

RDS(ON) [Ω],

Drain-Source On-Resistance

ID, Drain Current [A]24681010-1100101

150oC

25oC

-55oC

※ Notes : 1. VDS = 50V 2. 250μs Pulse Test

ID, Drain Current [A]

VGS, Gate-Source Voltage [V]10-110010110-210-1100101 VGSTop : 15.0 V 10.0 V 8.0 V 7.0 V 6.5 V 6.0 VBottom : 5.5 V

※ Notes : 1. 250μs Pulse Test 2. TC = 25℃

ID, Drain Current [A]

VDS, Drain-Source Voltage [V]

0481216202428024681012

VDS = 400VVDS = 160V

VDS = 640V

※ Note : ID = 4.8A

VGS, Gate-Source Voltage [V]

QG, Total Gate Charge [nC]10-110010102004006008001000120014001600Ciss = Cgs + Cgd (Cds = shorted)Coss = Cds + CgdCrss = Cgd

※ Notes : 1. VGS = 0 V 2. f = 1 MHzCrssCossCiss

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FPGA可编程逻辑器件芯片5SGXEA7N2F45I2N中文规格书

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Document Revision HistoryFigure6–1.CycloneII Device Packaging Ordering Information

Document Revision HistoryTable6–1 shows the revision history for this document.Device TypePackage Type6, 7, or 8, with 6 being the fastestNumber of pins for a particular packageES:

T:Q:F:U:Thin quad flat pack (TQFP)Plastic quad flat pack (PQFP)FineLine BGAUltra FineLine BGAEP2C:Cyclone II581520355070C:Commercial temperature (tJ = 0° C to 85° C)Industrial temperature (tJ = -40° C to 100° C)Optional SuffixFamily SignatureOperating TemperatureSpeed GradePin CountEngineering sample7EP2C70C324FESIndicates specific device options or shipment method.N:Lead-free devicesI:AFast-OnIndicates devices with fast POR (Power on Reset) time.

Table6–1.Document Revision HistoryDate & Document VersionChanges MadeSummary of ChangesFebruary 2007 v1.5●Added document revision history.●Updated Figure6–1.●Added Ultra FineLine BGAdetail in UBGA Packageinformation in Figure6–1.November 2005 v1.2Updated software introduction.November 2004 v1.1Updated Figure6–1.June 2004 v1.0Added document to the CycloneII Device Handbook.PLLs in CycloneII DevicesFigure7–1.CycloneII Device PLL LocationsNote(1)

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FPGA可编程逻辑器件芯片5SGXEA5N3F40I3N中文规格书

Supported I/O Standards

3.3-V PCI-XThe 3.3-V PCI-X I/O standard is formulated under PCI-X Local Bus Specification Revision1.0 developed by the PCI SIG. The PCI-X 1.0 standard is used for applications that interface to the PCI local bus. The standard enables the design of systems and devices that operate at clock speeds up to 133MHz, or 1gigabit per second (Gbps) for a 64-bit bus. The PCI-X 1.0 protocol enhancements enable devices to operate much more efficiently, providing more usable bandwidth at any clock frequency. By using the PCI-X 1.0 standard, devices can be designed to meet PCI-X 1.0 requirements and operate as conventional 33- and 66-MHz PCI devices when installed in those systems. This standardrequires 3.3-V VCCIO. CycloneII devices are fully compliant with the 3.3-V PCI-X Specification Revision 1.0a and meet the 133MHz operatingfrequency and timing requirements. The 3.3-V PCI-X standard does notrequire input reference voltages or board terminations. CycloneII devices support both input and output levels operation for left and right I/Obanks.Easy-to-Use, Low-Cost PCI Express SolutionPCI Express is rapidly establishing itself as the successor to PCI, providing higher performance, increased flexibility, and scalability for next-generation systems without increasing costs, all while maintaining software compatibility with existing PCI applications. Now you can easily design high volume, low-cost PCI Express ×1 solutions today featuring:

FPGA可编程逻辑器件芯片5SGXMB5R2F40I3N中文规格书

FPGA可编程逻辑器件芯片5SGXMB5R2F40I3N中文规格书

14.IEEE 1149.1 (JTAG)

Boundary-Scan Testing for

CycloneII Devices

IntroductionAs printed circuit boards (PCBs) become more complex, the need for

thorough testing becomes increasingly important. Advances in surface-

mount packaging and PCB manufacturing have resulted in smaller

boards, making traditional test methods (e.g., external test probes and

“bed-of-nails” test fixtures) harder to implement. As a result, cost savings

from PCB space reductions are sometimes offset by cost increases in

traditional testing methods.

In the 1980s, the Joint Test Action Group (JTAG) developed a specification

for boundary-scan testing that was later standardized as the

IEEEStd.1149.1 specification. This boundary-scan test (BST) architecture

offers the capability to efficiently test components on PCBs with tight lead

spacing.

FPGA可编程逻辑器件芯片5SGXMABN2F45I3N中文规格书

FPGA可编程逻辑器件芯片5SGXMABN2F45I3N中文规格书

The Intel® Arria® 10 device family consists of high-performance and power-efficient

20 nm mid-range FPGAs and SoCs.

Intel Arria 10 device family delivers:

•Higher performance than the previous generation of mid-range and high-end

FPGAs.

•Power efficiency attained through a comprehensive set of power-saving

technologies.

The Intel Arria 10 devices are ideal for high performance, power-sensitive, midrange

applications in diverse markets.

Table 1.Sample Markets and Ideal Applications for Intel Arria 10 DevicesMarketApplications

Wireless•Channel and switch cards in remote radio heads

•Mobile backhaul

Wireline•40G/100G muxponders and transponders

•100G line cards

•Bridging

•Aggregation

Broadcast•Studio switches

•Servers and transport

•Videoconferencing

•Professional audio and video

Computing and Storage•Flash cache

•Cloud computing servers