DYNAMAX DLIS-2K开发文档
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Before a detailed timing sequence discussion can ensue for the different modes of operation, a good conceptual explanation of row selection, sampling and readout must be understood first. Also, the necessary jargon is defined to aid the subsequent detailed discussions that follow. Row Selection Row Sampling/Digitization reference and video data Row Readout
Copyright 2013 Dynamax ImagingREV D 01/15/13 Subject to change without notice. Page 1 of 37
CONFIDENTIAL - DYNAMAX IMAGING, LLC
In addition to sections on each of the different modes, a section is also included on advanced options. Many of these options can be utilized in some or all of the operating modes, but separated out for clarity. A section on how to write a setup file for the Unified Demo board, is also included at the end of this document. The DLIS demonstration kit provides all the listed setup timing files to accomplish different readout modes listed above. Please refer to the Unified GUI User Manual (latest rev.) to setup the demonstration kit. The modes listed above are not the only modes of operation, combinations and permutations are possible by experienced operator. Contact the company for engineering assistance if needed. Digital Linear Image Sensor (DLIS) Timing Overview The CMOS imager is an array of individual pixels that are accessed in a sequential order for display. The readout occurs after the selected row and associated timing for the desired readout mode has occurred. The different readout modes are listed above. No matter what mode is selected, the information is none the less read out in a predetermined sequential order. It is this predetermined sequence that this application note will explain and explore the options available to the camera designer. The order of timing will be referenced to the DLIS sensors. The DLIS sensors are based on a Distributed Analog to Digital per pixel (D/ADTM) architecture patented by Dynamax Imaging. The predetermined sequence, follows three top level functions. The three top level functions are: row selection, sampling, digitizing the pixel data from the selected row, and reading the stored data out to the camera. In short we will refer to these operations as: row selection, sampling, digitizing and readout.
Fig. # 1 Top level imager timing sequence.
Row sampling/digitizing consists of two operations, background (reference level) capture and video capture. Row selection for background capture occurs by programming one of four Row_Reset registers to reset the sense node. When the sense node is reset this becomes the reference level (a.k.a. background level) that is digitized. The sense node is the node that is digitized by the Distributed Analog to Digital (D/ADTM) per pixel. The sense node is common for the four photodiodes. Row selection for video capture occurs by programming one of four Shutter registers to transfer the pixel charge to the sense node for reading. After the pixel charge has been transferred and digitized by the D/ADTM the sense node needs to be reset to accept the next transfer. The difference between the reference level and the video, is the Correlated Double Sampled (CDS) information that is output to the user. Since the video is digitized and has the reference level subtracted from the video there are a couple of items that need to be understood by the user. Subtraction of the reference level from the video level is done to remove all or most of the Fixed Pattern Noise (FPN) that exists at black. Black is used here as the signal generated by the imager without any light exposure. If at black the video and reference level are identical the output is zero counts. Add in some noise then it is possible that one can generate a negative value for video. Since the DLIS sensor doesn‟t have the ability to show a negative value it will output the rollover of data. Unfortunately, the data will appear as if it is bright white on the output instead of black. To eliminate this problem, and keep the digital block as simple as possible to keep costs down, we added in a programmable offset to the video data and the default value is 128 counts to account for the extreme cases of wide temperature ranges and noisy environments the imager may be used in. The user can reprogram if needed to maximize the dynamic range of the system. When the imager is approaching saturation the video information becomes non-linear in its response and the offset information is lost and stronger FPN is noticed on the output. To minimize FPN, the exposure can be reduced or utilize one of the modes like, Ambient light subtraction, High dynamic range (HDR), or Correlated Multi-Sampling (CMS). Another aspect of reading digital data, is the10 bit external data bus and 11 bit internal latches in that the user with some of the modes, like HDR and CMS, could have data in the eleventh bit and not be reading out the data. If there is data in the eleventh bit that is not readout the data effectively has 1023 counts subtracted from those pixels and the data that should appear bright will now be dark. Proper set up of the D/AD for resolution and the number of reads will eliminate any potential issues. Also, the user should they decide that data in the eleventh bit is proper the user has the option to read out the upper ten bits. The reason for the 11 bit latches is to have good 10 bits of information after CDS the signal internally should be 11 bits. The DLIS sensors are very flexible and allow the user to program the bit depth of the DAC from 8 to 12 bits per sample.
Copyright 2013 Dynamax ImagingREV D 01/15/13 Subject to change without notice. Page 1 of 37
CONFIDENTIAL - DYNAMAX IMAGING, LLC
In addition to sections on each of the different modes, a section is also included on advanced options. Many of these options can be utilized in some or all of the operating modes, but separated out for clarity. A section on how to write a setup file for the Unified Demo board, is also included at the end of this document. The DLIS demonstration kit provides all the listed setup timing files to accomplish different readout modes listed above. Please refer to the Unified GUI User Manual (latest rev.) to setup the demonstration kit. The modes listed above are not the only modes of operation, combinations and permutations are possible by experienced operator. Contact the company for engineering assistance if needed. Digital Linear Image Sensor (DLIS) Timing Overview The CMOS imager is an array of individual pixels that are accessed in a sequential order for display. The readout occurs after the selected row and associated timing for the desired readout mode has occurred. The different readout modes are listed above. No matter what mode is selected, the information is none the less read out in a predetermined sequential order. It is this predetermined sequence that this application note will explain and explore the options available to the camera designer. The order of timing will be referenced to the DLIS sensors. The DLIS sensors are based on a Distributed Analog to Digital per pixel (D/ADTM) architecture patented by Dynamax Imaging. The predetermined sequence, follows three top level functions. The three top level functions are: row selection, sampling, digitizing the pixel data from the selected row, and reading the stored data out to the camera. In short we will refer to these operations as: row selection, sampling, digitizing and readout.
Fig. # 1 Top level imager timing sequence.
Row sampling/digitizing consists of two operations, background (reference level) capture and video capture. Row selection for background capture occurs by programming one of four Row_Reset registers to reset the sense node. When the sense node is reset this becomes the reference level (a.k.a. background level) that is digitized. The sense node is the node that is digitized by the Distributed Analog to Digital (D/ADTM) per pixel. The sense node is common for the four photodiodes. Row selection for video capture occurs by programming one of four Shutter registers to transfer the pixel charge to the sense node for reading. After the pixel charge has been transferred and digitized by the D/ADTM the sense node needs to be reset to accept the next transfer. The difference between the reference level and the video, is the Correlated Double Sampled (CDS) information that is output to the user. Since the video is digitized and has the reference level subtracted from the video there are a couple of items that need to be understood by the user. Subtraction of the reference level from the video level is done to remove all or most of the Fixed Pattern Noise (FPN) that exists at black. Black is used here as the signal generated by the imager without any light exposure. If at black the video and reference level are identical the output is zero counts. Add in some noise then it is possible that one can generate a negative value for video. Since the DLIS sensor doesn‟t have the ability to show a negative value it will output the rollover of data. Unfortunately, the data will appear as if it is bright white on the output instead of black. To eliminate this problem, and keep the digital block as simple as possible to keep costs down, we added in a programmable offset to the video data and the default value is 128 counts to account for the extreme cases of wide temperature ranges and noisy environments the imager may be used in. The user can reprogram if needed to maximize the dynamic range of the system. When the imager is approaching saturation the video information becomes non-linear in its response and the offset information is lost and stronger FPN is noticed on the output. To minimize FPN, the exposure can be reduced or utilize one of the modes like, Ambient light subtraction, High dynamic range (HDR), or Correlated Multi-Sampling (CMS). Another aspect of reading digital data, is the10 bit external data bus and 11 bit internal latches in that the user with some of the modes, like HDR and CMS, could have data in the eleventh bit and not be reading out the data. If there is data in the eleventh bit that is not readout the data effectively has 1023 counts subtracted from those pixels and the data that should appear bright will now be dark. Proper set up of the D/AD for resolution and the number of reads will eliminate any potential issues. Also, the user should they decide that data in the eleventh bit is proper the user has the option to read out the upper ten bits. The reason for the 11 bit latches is to have good 10 bits of information after CDS the signal internally should be 11 bits. The DLIS sensors are very flexible and allow the user to program the bit depth of the DAC from 8 to 12 bits per sample.
