SN54LVTH162244WD中文资料

11G NhomakorabeaD 2A1
TA –40°C to 85°C
–40°C to 125°C
ORDERING INFORMATION
PACKAGE (1)
ORDERABLE PART NUMBER
QFN – RGY
Reel of 1000
SN74LVC244ARGYR
VFBGA – GQN Reel of 1000
Copyright © 1992–2005, Texas Instruments Incorporated
元器件交易网
SN74LVC244A OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCAS414X – NOVEMBER 1992 – REVISED MARCH 2005
at VCC = 3.3 V, TA = 25°C • Typical VOHV (Output VOH Undershoot) > 2 V
at VCC = 3.3 V, TA = 25°C • Supports Mixed-Mode Signal Operation on All
Ports (5-V Input/Output Voltage With 3.3-V VCC) • Ioff Supports Partial-Power-Down Mode Operation • Latch-Up Performance Exceeds 250 mA Per JESD 17 • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A)
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

© 2005 Fairchild Semiconductor Corporation DS012446January 1999Revised June 200574LVT162245 • 74LVTH162245 Low Voltage 16-Bit Transceiver with 3-STATE Outputs and 25: Series Resistors in A Port Outputs74LVT162245 • 74LVTH162245Low Voltage 16-Bit Transceiver with 3-STATE Outputs and 25: Series Resistors in A Port OutputsGeneral DescriptionThe LVT162245 and LVTH162245 contains sixteen non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. Each byte has separate control inputs which can be shorted together for full 16-bit operation. The T/R inputs determine the direction of data flow through the device. The OE inputs disable both the A and B ports by placing them in a high impedance state.The LVT162245 and LVTH162245 are designed with equivalent 25: series resistance in both the HIGH and LOW states on the A Port outputs. This design reduces line noise in applications such as memory address drivers,clock drivers, and bus transceivers/transmitters.The LVTH162245 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs.These non-inverting transceivers are designed for low volt-age (3.3V) V CC applications, but with the capability to pro-vide a TTL interface to a 5V environment. The LVT162245and LVTH162245 are fabricated with an advanced BiCMOS technology to achieve high speed operation simi-lar to 5V ABT while maintaining a low power dissipation.Featuress Input and output interface capability to systems at 5V V CC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH162245),also available without bushold feature (74LVT162245).s Live insertion/extraction permitteds Power Up/Down high impedance provides glitch-free bus loading s A Port outputs include equivalent series resistance of 25: making external termination resistors unnecessary and reducing overshoot and undershoot s A Port outputs source/sink r 12 mA.B Port outputs source/sink 32 mA/ 64 mA s Functionally compatible with the 74 series 162245s Latch-up performance exceeds 500 mA s ESD performance:Human-body model ! 2000V Machine model ! 200V Charged-device model ! 1000Vs Also packaged in plastic Fine Pitch Ball Grid Array (FBGA)Ordering Code:Note 1: Ordering code “G” indicates Trays.Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.Order Number Package Number Package Description74LVT162245G (Note 1)(Note 2)BGA54A (Preliminary)54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 74LVT162245MEA (Note 2)MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74LVT162245MTD (Note 2)MTD4848-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 74LVTH162245G (Note 1)(Note 2)BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 74LVTH162245MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TUBE]74LVTH162245MEX MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TAPE and REEL]74LVTH162245MTD MTD4848-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TUBE]74LVTH162245MTXMTD4848-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TAPE and REEL] 274L V T 162245 • 74L V T H 162245Logic SymbolConnection DiagramsPin Assignments for SSOP and TSSOPPin Assignment for FBGA(Top Thru View)Pin DescriptionsFBGA Pin AssignmentsTruth TablesH HIGH Voltage LevelL LOW Voltage Level X ImmaterialZ High ImpedancePin Names DescriptionOE n Output Enable Input (Active LOW)T/R n Transmit/Receive Input A 0–A 15Side A Inputs/3-STATE Outputs B 0–B 15Side B Inputs/3-STATE Outputs NCNo Connect123456A B 0NC T/R 1OE 1NC A 0B B 2B 1NC NC A 1A 2C B 4B 3V CC V CC A 3A 4D B 6B 5GND GND A 5A 6E B 8B 7GND GND A 7A 8F B 10B 9GND GND A 9A 10G B 12B 11V CC V CC A 11A 12H B 14B 13NC NC A 13A 14JB 15NCT/R 2OE 2NCA 15Inputs OutputsOE 1T/R 1L L Bus B 0–B 7 Data to Bus A 0–A 7L H Bus A 0–A 7 Data to Bus B 0–B 7HXHIGH-Z State on A 0–A 7, B 0–B 7Inputs OutputsOE 2T/R 2L L Bus B 8–B 15 Data to Bus A 8–A 15L H Bus A 8–A 15 Data to Bus B 8–B 15HXHIGH-Z State on A 8–A 15, B 8–B 1574LVT162245 • 74LVTH162245Functional DescriptionThe LVT162245 and LVTH162245 contain sixteen non-inverting bidirectional buffers with 3-STATE outputs. The device is byte controlled with each byte functioning identi-cally, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation.Logic DiagramsPlease note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. 474L V T 162245 • 74L V T H 162245Absolute Maximum Ratings (Note 3)Recommended Operating ConditionsNote 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 4: I O Absolute Maximum Rating must be observed.DC Electrical CharacteristicsSymbol ParameterValueConditionsUnits V CC Supply Voltage 0.5 to 4.6V V I DC Input Voltage 0.5 to 7.0VV O Output Voltage 0.5 to 7.0Output in 3-STATEV 0.5 to 7.0Output in HIGH or LOW State (Note 4)I IK DC Input Diode Current 50V I GND mA I OK DC Output Diode Current 50V O GND mA I O DC Output Current64V O ! V CC Output at HIGH State mA 128V O ! V CCOutput at LOW StateI CC DC Supply Current per Supply Pin r 64mA I GND DC Ground Current per Ground Pin r 128mAT STGStorage Temperature65 to 150q CSymbol ParameterMin Max Units V CC Supply Voltage 2.7 3.6V V I Input Voltage5.5V I OH HIGH-Level Output Current B Port 32mA A Port 12I OL LOW-Level Output Current B Port 64mAA Port12T AFree Air Operating Temperature40 85q C 't/'VInput Edge Rate, V IN 0.8V –2.0V, V CC 3.0V10ns/VSymbol ParameterV CC T A 40q C to 85q C Units Conditions(V)MinMax V IK Input Clamp Diode Voltage 2.7 1.2V I I 18 mA V IH Input HIGH Voltage 2.7–3.6 2.0V V O d 0.1V or V IL Input LOW Voltage 2.7–3.60.8V V O t V CC 0.1V V OHOutput HIGH VoltageA Port 3.0 2.0V I OH 12 mA 2.7–3.6V CC 0.2V I OH 100 P A B Port2.7 2.4V I OH 8 mA3.0 2.0I OH 32 mA V OLOutput LOW VoltageA Port3.00.8V I OL 12 mA 2.70.2VI OL 100 P A B Port2.70.5VI OL 24 mA 3.00.4I OL 16 mA 3.00.5I OL 32 mA 3.00.55I OL 64 mA I I(HOLD)Bushold Input Minimum Drive3.075P A V I 0.8V (Note 5) 75V I 2.0V I I(OD)Bushold Input Over-Drive 3.0500P A (Note 6)(Note 5)Current to Change State 500(Note 7)I IInput Current3.610P AV I 5.5V Control Pins 3.6r 1V I 0V or V CC Data Pins3.6 5V I 0V 1V I V CCI OFFPower Off Leakage Current 0r 100P A 0V d V I or V O d 5.5V74LVT162245 • 74LVTH162245DC Electrical Characteristics (Continued)Note 5: Applies to Bushold versions only (74LVTH162245).Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH.Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW.Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than V CC or GND.Dynamic Switching Characteristics (Note 9)Note 9: Characterized in SSOP package. Guaranteed parameter, but not tested.Note 10: Max number of outputs defined as (n). n 1 data inputs are driven 0V to 3V. Output under test held LOW.Symbol ParameterV CC T A 40q C to 85q C Units Conditions(V)MinMax I PU/PD Power Up/Down 0–1.5V r 100P A V O 0.5V to 3.0V 3-STATE CurrentV I GND to V CC I OZL 3-STATE Output Leakage Current 3.6 5P A V O 0.5V I OZL 3-STATE Output Leakage Current 3.6 5P A V O 0.0V (Note 5)I OZH 3-STATE Output Leakage Current 3.65P A V O 3.0V I OZH 3-STATE Output Leakage Current3.65P A V O 3.6V (Note 5)I OZH 3-STATE Output Leakage Current 3.610P A V CC V O d 5.5V I CCH Power Supply Current 3.60.19mA Outputs HIGH I CCL Power Supply Current 3.65mA Outputs LOW I CCZ Power Supply Current 3.60.19mA Outputs Disabled I CCZ Power Supply Current3.60.19mA V CC d V O d 5.5V,Outputs Disabled 'I CCIncrease in Power Supply Current 3.60.2mAOne Input at V CC 0.6V (Note 8)Other Inputs at V CC or GNDSymbol ParameterV CC T A 25q C Units Conditions (V)MinTyp MaxC L 50 pF, R L 500:V OLP Quiet Output Maximum Dynamic V OL 3.30.8V (Note 10)V OLVQuiet Output Minimum Dynamic V OL3.30.8V(Note 10) 674L V T 162245 • 74L V T H 162245AC Electrical CharacteristicsNote 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t OSHL ) or LOW-to-HIGH (t OSLH ).Capacitance (Note 12)Note 12: Capacitance is measured at frequency f 1 MHz, per MIL-STD-883, Method 3012.SymbolParameterT A 40q C to 85q CUnitsC L 50 pF, R L 500:V CC 3.3V r 0.3V V CC 2.7V MinMax MinMax t PLH Propagation Delay Data to A Port Output1.0 4.0 1.0 4.6ns t PHL 1.0 3.7 1.0 4.1t PLH Propagation Delay Data to B Port Output 1.0 3.5 1.0 3.9ns t PHL 1.0 3.5 1.0 3.9t PZH Output Enable Time for A Port Output 1.0 5.3 1.0 6.3ns t PZL 1.0 5.6 1.07.2t PZH Output Enable Time for B Port Output 1.0 4.6 1.0 5.4ns t PZL 1.0 5.3 1.0 6.9t PHZ Output Disable Time for A Port Output 1.5 5.6 1.5 6.3ns t PLZ 1.5 5.5 1.5 5.5t PHZ Output Disable Time for B Port Output 1.5 5.4 1.5 6.1ns t PLZ 1.55.1 1.55.4t OSHL A Port Output to Output Skew 1.0 1.0ns t OSLH (Note 11)t OSHL B Port Output to Output Skew 1.01.0ns t OSLH(Note 11)Symbol ParameterConditionsTypical Units C IN Input Capacitance V CC 0V, V I 0V or V CC 4pF C I/OInput/Output CapacitanceV CC 3.0V, V O 0V or V CC8pF74LVT162245 • 74LVTH162245Physical Dimensionsinches (millimeters) unless otherwise noted54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm WidePackage Number BGA54A 874L V T 162245 • 74L V T H 162245Physical Dimensions inches (millimeters) unless otherwise noted (Continued)48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" WidePackage Number MS48A974LVT162245 • 74LVTH162245 Low Voltage 16-Bit Transceiver with 3-STATE Outputs and 25: Series Resistors in A Port OutputsPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm WidePackage Number MTD48Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICYFAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user.2. A critical component in any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.。

5
PACKAGE OPTION ADDENDUM

PACKAGING INFORMATION
Orderable Device JM38510/08003BCA
Status Package Type Package Pins Package
(1)
Drawing
Qty
ACTIVE
CDIP
1
TBD
J
14
1
TBD
N
14
TBD
N
14
TBD
N
14
TBD
N
14
TBD
D
14
50 Green (RoHS
& no Sb/Br)
D
14
50 Green (RoHS
& no Sb/Br)
Lead/Ball Finish
(6)
POST-PLATE
POST-PLATE
A42
A42
A42
A42
A42
A42
A42
N / A for Pkg Type -55 to 125
N / A for Pkg Type -55 to 125
N / A for Pkg Type -55 to 125
N / A for Pkg Type -55 to 125
N / A for Pkg Type -55 to 125
N / A for Pkg Type -55 to 125
N / A for Pkg Type -55 to 125
N / A for Pkg Type -55 to 125
N / A for Pkg Type
N / A for Pkg Type

1/11February 2003s 3.6V TOLERANT INPUTS AND OUTPUTS sHIGH SPEED :t PD =2.5ns (MAX.)at V CC =3.0to 3.6V t PD =3.0ns (MAX.)at V CC =2.3to 2.7VsPOWER DOWN PROTECTION ON INPUTS AND OUTPUTSsSYMMETRICAL OUTPUT IMPEDANCE:|I OH |=I OL =24mA (MIN)at V CC =3.0V |I OH |=I OL =18mA (MIN)at V CC =2.3V sOPERATING VOLTAGE RANGE:V CC (OPR)=2.3V to 3.6VsPIN AND FUNCTION COMPATIBLE WITH 74SERIES H16244s BUS HOLD PROVIDED ON DATA INPUTS sLATCH-UP PERFORMANCE EXCEEDS 300mA (JESD 17)sESD PERFORMANCE:HBM >2000V (MIL STD 883method 3015);MM >200VDESCRIPTIONThe 74VCXH16244is a low voltage CMOS 16BIT BUS BUFFER (NON INVERTED)fabricated with sub-micron silicon gate and five-layer metal wiring C 2MOS technology.It is ideal for low power and very high speed 2.3to 3.6V applications;it can be interfaced to 3.6V signal environment for both inputs and outputs.Any nG output control governs four BUS BUFFERS.Output Enable input tied together gives full 16-bit operation.When nG is LOW,the outputs are on.When nG is HIGH,the output are in high impedance state.This device is designed to be used with 3state memory address drivers,etc.Bus hold on data inputs is provided in order to eliminate the need for external pull-up or pull-down resistor.All inputs and outputs are equipped with protection circuits against static discharge,giving them 2KV ESD immunity and transient excess voltage.74VCXH16244LOW VOLTAGE CMOS 16-BIT BUS BUFFER (3-STATE INV.)WITH 3.6V TOLERANT INPUTS ANDOUTPUTSORDER CODESPACKAGE TUBET &RTSSOP74VCXH16244TTRPIN CONNECTION74VCXH162442/11INPUT AND OUTPUT EQUIVALENT CIRCUITPIN DESCRIPTIONTRUTH TABLEX :Don‘t CareZ :High ImpedanceIEC LOGIC SYMBOLSPIN No SYMBOL NAME AND FUNCTION 11G Output Enable Input 2,3,5,61Y1to 1Y4Data Outputs 8,9,11,122Y1to 2Y4Data Outputs 13,14,16,173Y1to 3Y4Data Outputs 19,20,22,234Y1to 4Y4Data Outputs244G Output Enable Input 253G Output Enable Input 30,29,27,264A1to 4A4Data Outputs 36,35,33,323A1to 3A4Data Outputs 41,40,38,372A1to 2A4Data Outputs 47,46,44,431A1to 1A4Data Outputs482G Output Enable Input 4,10,15,21,28,34,39,45GND Ground (0V)7,18,31,42V CCPositive Supply VoltageINPUTS OUTPUTG An Yn L L L L H H HXZ74VCXH162443/11ABSOLUTE MAXIMUM RATINGSAbsolute Maximum Ratings are those values beyond which damage to the device may occur.Functional operation under these conditions isnot implied1)I O absolute maximum rating must be observed 2)V O <GND,V O >V CCRECOMMENDED OPERATING CONDITIONS1)V IN from 0.8V to 2V at V CC =3.0VSymbol ParameterValue Unit V CC Supply Voltage -0.5to +4.6V V I DC Input Voltage-0.5to +4.6V V O DC Output Voltage (OFF State)-0.5to +4.6V V O DC Output Voltage (High or Low State)(note 1)-0.5to V CC +0.5V I IK DC Input Diode Current-50mA I OK DC Output Diode Current (note 2)-50mA I ODC Output Current±50mA I CC or I GND DC V CC or Ground Current per Supply Pin±100mA P DPower Dissipation 400mW T stg Storage Temperature -65to +150°C T LLead Temperature (10sec)300°CSymbol ParameterValue Unit V CC Supply Voltage 2.3to 3.6V V I Input Voltage-0.3to 3.6V V O Output Voltage (OFF State)0to 3.6V V O Output Voltage (High or Low State)0to V CC V I OH ,I OL High or Low Level Output Current (V CC =3.0to 3.6V)±24mA I OH ,I OL High or Low Level Output Current (V CC =2.3to 2.7V)±18mA T op Operating Temperature-55to 125°C dt/dvInput Rise and Fall Time (note 1)0to 10ns/V74VCXH162444/11DC SPECIFICATIONS (2.7V <V CC <3.6V unless otherwise specified)SymbolParameterTest ConditionValueUnitV CC (V)-40to 85°C -55to 125°C Min.Max.Min.Max.V IH High Level Input Voltage2.7to3.62.02.0VV IL Low Level Input Voltage0.80.8V OHHigh Level Output Voltage2.7to3.6I O =-100µA V CC -0.2V CC -0.2V2.7I O =-12mA 2.2 2.23.0I O =-18mA 2.4 2.4I O =-24mA 2.22.2V OLLow Level Output Voltage2.7to3.6I O =100µA 0.20.2V 2.7I O =12mA 0.40.43.0I O =18mA 0.40.4I O =24mA 0.550.55I I Input Leakage Current2.7to3.6V I =V CC or GND±5±5µA I I(HOLD)Input Hold Current3.0V I =0.8V 7575µAV I =2V -75-753.6V I =0to 3.6V ±500±500I off Power Off Leakage Current0V I or V O =0to 3.6V 1010µA I OZ High Impedance Output Leakage Current2.7to3.6V I =V IH or V IL V O =0to 3.6V ±10±10µA I CCQuiescent Supply Current2.7to3.6V I =V CC or GND 2020µA V I or V O =V CC to3.6V±20±20∆I CCI CC incr.per Input2.7to3.6V IH =V CC -0.6V750750µA74VCXH162445/11DC SPECIFICATIONS (2.3V <V CC <2.7V unless otherwise specified)DYNAMIC SWITCHING CHARACTERISTICS (T a =25°C,Input t r =t f =2.0ns,C L =30pF ,R L =500Ω)1)Number of outputs defined as "n".Measured with "n-1"outputs switching from HIGH to LOW or LOW to HIGH.The remaining output is measured in the LOW state.2)Number of outputs defined as "n".Measured with "n-1"outputs switching from HIGH to LOW or LOW to HIGH.The remaining output is measured in the HIGH state.3)Parameters guaranteed by design.SymbolParameterTest ConditionValueUnitV CC (V)-40to 85°C -55to 125°C Min.Max.Min.Max.V IH High Level Input Voltage2.3to 2.71.61.6VV IL Low Level Input Voltage0.70.7V OHHigh Level Output Voltage2.3to 2.7I O =-100µA V CC -0.2V CC -0.2V2.3I O =-6mA 2.0 2.0I O =-12mA 1.8 1.8I O =-18mA 1.71.7V OLLow Level Output Voltage2.3to 2.7I O =100µA 0.20.2V 2.3I O =12mA 0.40.4I O =18mA 0.60.6I I Input Leakage Current2.3to 2.7V I =V CC or GND±5±5µA I I(HOLD)Input Hold Current 2.3V I =0.7V 4545µA V I =1.7V -45-45I off Power Off Leakage Current0V I or V O =0to 3.6V 1010µA I OZ High Impedance Output Leakage Current2.3to 2.7V I =V IH or V IL V O =0to 3.6V ±10±10µA I CCQuiescent Supply Current2.3to 2.7V I =V CC or GND 2020µAV I or V O =V CC to3.6V±20±20SymbolParameterTest ConditionValue UnitV CC (V)T A =25°C Min.Typ.Max.V OLP Dynamic Low Voltage Quiet Output (note 1,3)2.5V IL =0V V IH =V CC 0.6V3.30.8V OLV Dynamic Low Voltage Quiet Output (note 1,3)2.5V IL =0V V IH =V CC -0.6V3.3-0.8V OHVDynamic High Voltage Quiet Output (note 2,3)2.5V IL =0V V IH =V CC1.9V 3.32.274VCXH162446/11AC ELECTRICAL CHARACTERISTICS (C L =30pF,R L =500Ω, Input t r =t f =2.0ns )1)Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-ing in the same direction,either HIGH or LOW (t OSLH =|t PLHm -t PLHn |,t OSHL =|t PHLm -t PHLn |)2)Parameter guaranteed by designCAPACITIVE CHARACTERISTICS1)C PD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load.(Refer to Test Circuit).Average operating current can be obtained by the following equation.I CC(opr)=C PD x V CC x f IN +I CC /16(per circuit)SymbolParameterTest ConditionValueUnitV CC (V)-40to 85°C -55to 125°C Min.Max.Min.Max.t PLH t PHL Propagation Delay Time2.3to 2.7 1.03.0 1.0 3.6ns 3.0to 3.60.8 2.50.8 3.1t PZL t PZH Output Enable Time 2.3to 2.7 1.04.1 1.0 4.8ns 3.0to 3.60.8 3.50.8 4.1t PLZ t PHZOutput Disable Time2.3to 2.7 1.03.8 1.04.5ns 3.0to 3.60.83.50.84.1t OSLH t OSHL Output To OutputSkew Time (note1,2)2.3to 2.70.50.5ns3.0to 3.60.50.5SymbolParameterTest ConditionValue UnitV CC (V)T A =25°C Min.Typ.Max.C IN Input Capacitance 2.5or 3.3V IN =0or V CC 6pF C OUT Output Capacitance2.5or3.3V IN =0or V CC 7pF C PDPower Dissipation Capacitance (note 1)2.5or3.3f IN =10MHz V IN =0or V CC20pF74VCXH162447/11TEST CIRCUITC L =30pF or equivalent (includes jig and probe capacitance)R L =R1=500Ω or equivalentR T =Z OUT of pulse generator (typically 50Ω)WAVEFORM SYMBOL VALUESTESTSWITCH t PLH ,t PHLOpen t PZL ,t PLZ (V CC =3.0to 3.6V)6V t PZL ,t PLZ (V CC =2.3to 2.7V)2V CC t PZH ,t PHZGNDSymbolV CC3.0to3.6V2.3to 2.7VV IH 2.7V V CC V M 1.5V V CC /2V X V OL +0.3V V OL +0.15V V YV OH -0.3VV OH -0.15V74VCXH162448/11WAVEFORM 1:PROPAGATION DELAYS (f=1MHz;50%duty cycle)WAVEFORM 2:OUTPUT ENABLE AND DISABLE TIME (f=1MHz;50%dutycycle)元器件交易网74VCXH16244 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result fromits use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specificationsmentioned in this publication are subject to change without notice. This publication supersedes and replaces all informationpreviously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices orsystems without express written approval of STMicroelectronics.© The ST logo is a registered trademark of STMicroelectronics© 2003 STMicroelectronics - Printed in Italy - All Rights ReservedSTMicroelectronics GROUP OF COMPANIESAustralia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - MoroccoSingapore - Spain - Sweden - Switzerland - United Kingdom - United States.© 11/11。