AT89S52 (51)单片机的引脚图及各引脚功能说明

AT89S51系列单片机的特点（AT89S51引脚功能及应用电路）AT89S51概述AT89S51是一个低功耗，高性能CMOS 8位单片机，片内含4k Bytes ISP（In-system programmable）的可反复擦写1000次的Flash只读程序存储器，器件采用ATMEL公司的高密度、非易失性存储技术制造，兼容标准MCS-51指令系统及80C51引脚结构，芯片内集成了通用8位中央处理器和ISP Flash存储单元，AT89S51在众多嵌入式控制应用系统中得到广泛应用。

AT89S51性能参数1、4k Bytes Flash片内程序存储器；
2、128 bytes的随机存取数据存储器（RAM）；
3、32个外部双向输入/输出（I/O）口；
4、2个中断优先级、2层中断嵌套中断；
5、5个中断源；
6、2个16位可编程定时器/计数器；
7、1个全双工串行通信口；
8、看门狗（WDT）电路；
9、片内振荡器和时钟电路；
10、与MCS-51兼容；
11、全静态工作：0Hz-33MHz；
12、三级程序存储器保密锁定；
13、可编程串行通道；
14、低功耗的闲置和掉电模式。

AT89S51引脚及功能VCC：电源电压输入端。

GND：电源地。

P0口：P0口为一个8位漏级开路双向I/O口，每脚可吸收8TTL门电流。

当P1口的管脚第一次写1时，被定义为高阻输入。

P0能够用于外部程序数据存储器，它可以被定义为数据/地址的低八位。

在FIASH编程时，P0 口作为原码输入口，当FIASH进行校验时，。

AT89S52单片机简介本系统采用AT89S52作为核心部件，AT89S52为 ATMEL 所生产的一种低功耗、高性能CMOS8位微控制器，具有8K在系统可编程Flsah 存储器。

（一）、AT89S52主要功能列举如下：1、拥有灵巧的8位CPU和在系统可编程Flash2、晶片内部具时钟振荡器（传统最高工作频率可至 12MHz）3、内部程序存储器（ROM）为 8KB4、内部数据存储器（RAM）为 256字节5、32 个可编程I/O 口线6、8 个中断向量源7、三个 16 位定时器/计数器8、三级加密程序存储器9、全双工UART串行通道（二）、AT89S52各引脚功能介绍：AT89S52各引脚图VCC：AT89S52电源正端输入，接+5V。

VSS：电源地端。

XTAL1：单芯片系统时钟的反相放大器输入端。

XTAL2：系统时钟的反相放大器输出端，一般在设计上只要在XTAL1 和 XTAL2 上接上一只石英振荡晶体系统就可以动作了，此外可以在两引脚与地之间加入一 20PF 的小电容，可以使系统更稳定，避免噪声干扰而死机。

RESET：AT89S52的重置引脚，高电平动作，当要对晶片重置时，只要对此引脚电平提升至高电平并保持两个机器周期以上的时间，AT89S51便能完成系统重置的各项动作，使得内部特殊功能寄存器之内容均被设成已知状态，并且至地址0000H处开始读入程序代码而执行程序。

EA/Vpp："EA"为英文"External Access"的缩写，表示存取外部程序代码之意，低电平动作，也就是说当此引脚接低电平后，系统会取用外部的程序代码（存于外部EPROM中）来执行程序。

因此在8031及8032中，EA引脚必须接低电平，因为其内部无程序存储器空间。

如果是使用 8751 内部程序空间时，此引脚要接成高电平。

此外，在将程序代码烧录至8751内部EPROM时，可以利用此引脚来输入21V 的烧录高压（Vpp）。

缩写英文解释中文解释RST （9）Reset 复位信号引脚RxD (10--P3.0) Receive Data 串口接收端TxD (11--P3.1) Transmit Data 串口发送端INT0 （12--P3.2）Interrupt0 外部中断0信号输入引脚INT1 （13--P3.3）Interrupt1 外部中断1信号输入引脚T0 (14--P3.4) Timer0 定时/计数器0输入信号引脚T1 (15--P3.5) Timer1 定时/计数器1输入信号引脚WR (16--P3.6) write 写信号引脚RD (17--P3.7) read 读信号引脚PSEN （29）progammer saving enable 外部程序存储器读选通信号ALE （30）Address Latch Enable 地址锁存允许信号EA (31) enable 外部ROM选择信号AT89S52引脚图ULN2803继电器接法51内部寄存器SFR special funtion register 特殊功能寄存器ACC accumulate 累加器APSW progammer status word 程序状态字CY (PSW.7) carry 进位标志位AC (PSW.6) assistant carry 辅助进位标志位OV (PSW.2) overflow 溢出标志位PC progammer counter 程序计数器DPTR data point register 数据指针寄存器SP stack point 堆栈指针TCON timer control 定时器控制寄存器TF1 （TCON.7） Timer1 flag T1中断标志位TR1 （TCON.6） Timer1 Run T1运行控制位TF0 （TCON.5） Timer0 flag T0中断标志位TR0 （TCON.4） Timer0 Run T0运行控制位IE1 （TCON.3） Interrupt1 exterior 外部中断1中断标志位IT1 （TCON.2） Interrupt1 touch 外部中断1 触发方式选择位IE0 （TCON.1） Interrupt0 exterior 外部中断0中断标志位IT0 （TCON.0） Interrupt0 touch 0-电平触发 1-下降沿触发IE （A8H） interrupt enable 中断允许寄存器EA (IE.7) enable all interrupt 中断总允许位ES (IE.4) enable serial 串行口中断允许位ET1 （IE.3） enable timer 1 T1中断允许位EX1 （IE.2） enable exterior 1 外部中断1中断允许位ET0 （IE.1） enable timer 0 T0中断允许位EX0 （IE.0） enable exterior 0 外部中断0中断允许位IP （B8H） interrupt priority 中断优先级寄存器PS (IP.4) priority serial 串口优先级标志位PT1 (IP.3) priority timer 1 定时器1优先级标志位PX1 (IP.2) priority exterior 1 外部中断1优先级标志位PT0 (IP.1) priority timer 0 定时器0优先级标志位PX0 (IP.0) priority exterior 0 外部中断0优先级标志位PCON (87H) power control 电源控制和波特率选择TMOD （89H） timer mode 定时器方式控制寄存器MSB = most significant bit//最高有效位LSB = last significant bit//最低有效位OE = output enable //输出使能MCS-51指令（1）数据传送类指令（7种助记符）助记符英文注释功能MOV Move 对内部数据寄存器RAM和特殊功能寄存器SFR的数据进行传送MOVC Move Code 读取程序存储器数据表格的数据传送MOVX Move External RAM 对外部RAM的数据传送XCH Exchange 字节交换XCHD Exchange low-order Digit 低半字节交换PUSH Push onto Stack) 入栈POP Pop from Stack) 出栈（2）算术运算类指令（8种助记符）ADD Addition 加法ADDC Add with Carry 带进位加法SUBB Subtract with Borrow 带借位减法DA Decimal Adjust 十进制调整INC Increment 加1DEC Decrement 减1MUL Multiplication、Multiply 乘法DIV Division、Divide 除法(3)逻辑运算类指令（10种助记符）ANL And Logic 逻辑与ORL OR Logic 逻辑或XRL Exclusive-OR Logic 逻辑异或CLR Clear 清零CPL Complement 取反RL Rotate left 循环左移RLC Rotate Left throught the Carry flag 带进位循环左移RR Rotate Right 循环右移RRC Rotate Right throught the Carry flag 带进位循环右移SWAP Swap 低4位与高4位交换(4)控制转移类指令（17种助记符）ACALL Absolute subroutine Call 子程序绝对调用LCALL Long subroutine Call 子程序长调用RET Return from subroutine 子程序返回RETI Return from Interruption 中断返回JMP Jump IndirectSJMP Short Jump 短转移AJMP Absolute Jump 绝对转移LJMP Long Jump 长转移CJNE Compare and Jump if Not Equal 比较不相等则转移DJNZ Decrement and Jump if Not Zero 减１后不为０则转移JZ Jump if Zero 结果为０则转移JNZ Jump if Not Zero 结果不为０则转移JC Jump if the Carry flag is set 有进位则转移JNC Jump if Not Carry 无进位则转移JB Jump if the Bit is set) B位为１则转移JNB Jump if the Bit is Not set B位为０则转移JBC Jump if the Bit is set and Clear the bit 位为１则转移，并清除该位NOP No Operation 空操作（5）位操作指令（1种助记符）SETB Set Bit 置位51伪指令助记符英文注释功能ORG OriginDB Define ByteDW Define WordEQU EqualDATA DataXDATA External Data BIT BitEND End。

Features·Compatible with MCS®-51Products·8K Bytes of In-System Programmable(ISP)Flash Memory –Endurance:10,000Write/Erase Cycles·4.0V to5.5V Operating Range·Fully Static Operation:0Hz to33MHz·Three-level Program Memory Lock·256x8-bit Internal RAM·32Programmable I/O Lines·Three16-bit Timer/Counters·Eight Interrupt Sources·Full Duplex UART Serial Channel·Low-power Idle and Power-down Modes·Interrupt Recovery from Power-down Mode ·Watchdog Timer·Dual Data Pointer·Power-off Flag·Fast Programming Time·Flexible ISP Programming(Byte and Page Mode)·Green(Pb/Halide-free)Packaging Option1.DescriptionThe AT89S52is a low-power,high-performance CMOS8-bit microcontroller with8K bytes of in-system programmable Flash memory.The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the indus-try-standard80C51instruction set and pinout.The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory pro-grammer.By combining a versatile8-bit CPU with in-system programmable Flash on a monolithic chip,the Atmel AT89S52is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.The AT89S52provides the following standard features:8K bytes of Flash,256bytes of RAM,32I/O lines,Watchdog timer,two data pointers,three16-bit timer/counters,a six-vector two-level interrupt architecture,a full duplex serial port,on-chip oscillator, and clock circuitry.In addition,the AT89S52is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM,timer/counters,serial port,and interrupt system to continue functioning.The Power-down mode saves the RAM con-tents but freezes the oscillator,disabling all other chip functions until the next interrupt or hardware reset.P 1.4 P 1.3 P 1.2P 1.1(T 2E X )P 1.0(T 2)N CV C CP 0.0(A D 0) P 0.1(A D 1) P 0.2(A D 2) P 0.3(A D 3)P 1.4 P 1.3 P 1.2P 1.1(T 2E X )P 1.0(T 2)N CV C CP 0.0(A D 0) P 0.1(A D 1) P 0.2(A D 2) P 0.3(A D 3)44 43 42 41 40 39 38 37 36 35 3412 13 14 15 16 17 18 19 20 21 22(W R )P 3.6 (R D )P 3.7 X T A L 2 X T A L 1 G N D G N D (A 8)P 2.0 (A 9)P 2.1 (A 10)P 2.2 (A 11)P 2.3 (A 12)P 2.4(W R )P 3.6 (R D )P 3.7 X T A L 2 X T A L 1 G N D N C (A 8)P 2.0 (A 9)P 2.1 (A 10)P 2.2 (A 11)P 2.3 (A 12)P 2.418 19 20 21 22 23 24 25 26 27 286 5 4 3 2 1 44 43 42 41 402. Pin Configurations2.140-lead PDIP2.3 44-lead PLCC(MOSI) P1.5 (MISO) P1.6 (SCK) P1.7RST(RXD) P3.0NC(TXD ) P3.1 (INT0 ) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.57 8 9 10 11 12 13 14 15 16 1739 38 37 36 35 34 33 32 31 30 29P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPPNCALE/PROGPSENP2.7 (A15) P2.6 (A14) P2.5 (A13)2.244-lead TQFP(MOSI) P1.5 (MISO) P1.6 (SCK) P1.7RST(RXD) P3.0NC(TXD) P3.1(INT0 ) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.51 2 3 4 5 6 7 8 9 10 1133 32 31 30 29 28 27 26 25 24 23P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPPNCALE/PROGPSENP2.7 (A15) P2.6 (A14) P2.5 (A13)2AT89S521919D –MICRO –6/08DOGISP PORTPROGRAMLOGICAT89S523. Block DiagramV CCGNDP0.0 - P0.7PORT 0 DRIVERSP2.0 - P2.7PORT 2 DRIVERSBREGISTERRAM ADDR. REGISTERACCRAMPORT 0 LATCHPORT 2 LATCHFLASHSTACK POINTERPROGRAM ADDRESS REGISTERBUFFERTMP2TMP1PCPSENPSWALUINTERRUPT, SERIAL PORT, AND TIMER BLOCKS INCREMENTERPROGRAM COUNTER ALE/PROG EA / V PPTIMINGANDCONTROLINSTRUCTIONREGISTERDUAL DPTRRSTWATCHPORT 3 PORT 1 LATCHLATCHOSCPORT 3 DRIVERSP3.0 - P3.7PORT 1 DRIVERSP1.0 - P1.731919D –MICRO –6/084. Pin Description4.1 VCCSupply voltage.4.2 GNDGround.4.3 Port 0Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups.Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur- ing program verification. External pull-ups are required during program verification .4.4 Port 1Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the inter- nal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (I IL ) because of the internal pull-ups.In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the follow- ing table.Port 1 also receives the low-order address bytes during Flash programming and verification.4.5 Port 2Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the inter- nal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (I IL ) because of the internal pull-ups.Port 2 emits the high-order address byte during fetches from external program memory and dur- ing accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash program- ming and verification.4AT89S521919D –MICRO –6/08AT89S524.6 Port 3Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the inter- nal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (I IL ) because of the pull-ups.Port 3 receives some control signals for Flash programming and verification.Port 3 also serves the functions of various special features of the AT89S52, as shown in the fol- lowing table.4.7 RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives high for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled.4.8 ALE/PROGAddress Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped dur- ing each access to external data memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.51919D –MICRO –6/084.9 PSENProgram Store Enable (PSEN) is the read strobe to external program memory.When the AT89S52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to exter- nal data memory.4.10 EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to V CC for internal program executions.This pin also receives the 12-volt programming enable voltage (V PP ) during Flash programming.4.11 XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.4.12 XTAL2Output from the inverting oscillator amplifier.5. Special Function RegistersA map of the on-chip memory area called the Special Function Register (SFR) space is shown in T able 5-1.Note that not all of the addresses are occupied, and unoccupied addresses may not be imple- mented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.Timer 2 Registers: Control and status bits are contained in registers T2CON (shown in T able 5- 2) and T2MOD (shown in T able 10-2) for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode. Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register.6AT89S521919D –MICRO –6/08AT89S52Table 5-1.AT89S52 SFR Map and Reset Values0F8H0FFH0F0H0F7H0E8H0EFH0E0H0E7H0D8H0DFH0D0H0C8H0D7H0CFH0C0H0C7H0B8H0B0H0A8H0A0H98H90H88H80H0BFH0B7H0AFH0A7H9FH97H8FH87H71919D –MICRO –6/08Table 5-2.T2CON – Timer/Counter 2 Control Register8AT89S521919D –MICRO –6/08AT89S52Table 5-3.AUXR: Auxiliary RegisterDual Data Pointer Registers: T o facilitate accessing both internal and external data memory, two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1. The user should ALWAYS initialize the DPS bit to the appropriate value before accessing the respective Data Pointer Register.Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to “1” during power up. It can be set and rest under software control and is not affected by reset.Table 5-4.AUXR1: Auxiliary Register 191919D –MICRO –6/086. Memory OrganizationMCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed.6.1 Program MemoryIf the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S52, if EA is connected to V CC , program fetches to addresses 0000H through 1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are to external memory.6.2 Data MemoryThe AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space.When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions which use direct addressing access the SFR space.For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2).MOV 0A0H, #dataInstructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).MOV @R0, #dataNote that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.7. Watchdog Timer (One-time Enabled with Reset-out)The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. T o enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT over- flows, it will drive an output RESET HIGH pulse at the RST pin.7.1 Using the WDTT o enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycles. T o reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written. When10AT89S521919D –MICRO –6/08AT89S52WDT overflows,it will generate an output RESET pulse at the RST pin.The RESET pulse dura-tion is98xTOSC,where TOSC=1/FOSC.T o make the best use of the WDT,it should beserviced in those sections of code that will periodically be executed within the time required toprevent a WDT reset.7.2WDT During Power-down and IdleIn Power-down mode the oscillator stops,which means the WDT also stops.While in Power-down mode,the user does not need to service the WDT.There are two methods of exitingPower-down mode:by a hardware reset or via a level-activated external interrupt which isenabled prior to entering Power-down mode.When Power-down is exited with hardware reset,servicing the WDT should occur as it normally does whenever the AT89S52is reset.ExitingPower-down with an interrupt is significantly different.The interrupt is held low long enough forthe oscillator to stabilize.When the interrupt is brought high,the interrupt is serviced.T o preventthe WDT from resetting the device while the interrupt pin is held low,the WDT is not started untilthe interrupt is pulled high.It is suggested that the WDT be reset during the interrupt service forthe interrupt used to exit Power-down mode.T o ensure that the WDT does not overflow within a few states of exiting Power-down,it is best toreset the WDT just before entering Power-down mode.Before going into the IDLE mode,the WDIDLE bit in SFR AUXR is used to determine whetherthe WDT continues to count if enabled.The WDT keeps counting during IDLE(WDIDLE bit=0)as the default state.T o prevent the WDT from resetting the AT89S52while in IDLE mode,theuser should always set up a timer that will periodically exit IDLE,service the WDT,and reenterIDLE mode.With WDIDLE bit enabled,the WDT will stop to count in IDLE mode and resumes the countupon exit from IDLE.8.UARTThe UART in the AT89S52operates the same way as the UART in the AT89C51and AT89C52.For further information on the UART operation,please click on the document link below:9.Timer0and1Timer0and Timer1in the AT89S52operate the same way as Timer0and Timer1in theAT89C51and AT89C52.For further information on the timers’operation,please click on thedocument link below:111919D–MICRO–6/0810. Timer 2Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in T able 5-2). Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in T able 10-1. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscil- lator frequency.Table 10-1. Timer 2 Operating ModesIn the Counter function, the register is incremented in response to a 1-to-0 transition at its corre- sponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. T o ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.10.1 Capture ModeIn the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 1-to-0 transi- tion at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt. The capture mode is illus- trated in Figure 10-1.10.2 Auto-reload (Up or Down Counter)Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD (see T able 10-2). Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin.12AT89S521919D –MICRO –6/08AT89S52Figure 10-1.Timer in Capture ModeOSC÷12C/T2 = 0TH2 TL2 TF2CONTROLOVERFLOWT2 PINC/T2 = 1TR2CAPTURERCAP2H RCAP2LTRANSITION DETECTORTIMER 2 INTERRUPTT2EX PINEXF2CONTROLEXEN2Table 10-2. T2MOD – Timer 2 Mode Control RegisterFigure 10-2 shows Timer 2 automatically counting up when DCEN = 0. In this mode, two optionsare selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in Timer in Capture ModeRCAP2H and RCAP2L are preset by software. If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt if enabled.Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure 10-2. In this mode, the T2EX pin controls the direction of the count. A logic 1 at T2EX makes Timer 2 count up. The timer will overflow at 0FFFFH and set the TF2 bit. This overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2, respectively.A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers.The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt.131919D –MICRO –6/08Figure10-2.Timer2Auto Reload Mode(DCEN=0)OSC÷12C/T2=0TH2TL2CONTR OLTR2OVERFLOWT2PINC/T2=1RELOADTIMER2RCAP2H RCAP2L INTERRUPTTF2TRANSITIONDETECTORT2EX PINCONTROLEXEN2Figure10-3.Timer2Auto Reload Mode(DCEN=1)(DOWN COUNTING RELOAD VALUE)EXF2 TOGGLE0FFH0FFH EXF2OSC÷12T2PIN C/T2=0C/T2=1OVERFLOWTH2TL2CONTROLTR2RCAP2H RCAP2L(UP COUNTING RELOAD VALUE)COUNTDIRECTION1=UP0=DOWNT2EX PINTF2TIMER2INTERRUPT14AT89S521919D–MICRO–6/08万联芯城是国内的一家电子元器件线上电商平台，专为客户提供原装现货电子元器件物料，所售产品范围包括IC集成电路，二三极管，电阻电容等多样主动类，被动类电子元器件，原厂及代理商直供渠道，价格有明显优势，只需提交BOM表，即可为您报价。

AT89S52简介AT89S52是一个8位单片机，片内ROM全部采用FLASH ROM技术，与MCS-51系列完全兼容，它能以3V的超低电压工作，晶振时钟最高可达24MHz。

AT89S52是标准的40引脚双列直插式集成电路芯片，有4个八位的并行双向I/O 端口，分别记作P0、P1、P2、P3。

第31引脚需要接高电位使单片机选用内部程序存储器；第9引脚是复位引脚，要接一个上电手动复位电路；第40脚为电源端VCC，接+5V电源，第20引脚为接地端VSS，通常在VCC和VSS引脚之间接0.1μF高频滤波电容。

第18、19脚之间接上一个12MHz的晶振为单片机提供时钟信号。

AT89S52单片机说明如下:此芯片是一种高性能低功耗的采用CMOS工艺制造的8位微控制器，它提供下列标准特征：8K字节的程序存储器，256字节的RAM,32条I/O线，2个16位定时器/计数器, 一个5中断源两个优先级的中断结构，一个双工的串行口, 片上震荡器和时钟电路。

引脚说明：·V CC：电源电压·GND:地·P0口：P0口是一组8位漏极开路型双向I/O口，作为输出口用时，每个引脚能驱动8个TTL逻辑门电路。

当对0端口写入1时，可以作为高阻抗输入端使用。

当P0口访问外部程序存储器或数据存储器时，它还可设定成地址数据总线复用的形式。

在这种模式下，P0口具有内部上拉电阻。

在EPROM编程时，P0口接收指令字节，同时输出指令字节在程序校验时。

程序校验时需要外接上拉电阻。

·P1口：P1口是一带有内部上拉电阻的8位双向I/O口。

P1口的输出缓冲能接受或输出4个TTL逻辑门电路。

当对P1口写1时，它们被内部的上拉电阻拉升为高电平，此时可以作为输入端使用。

当作为输入端使用时，P1口因为内部存在上拉电阻，所以当外部被拉低时会输出一个低电流（I IL）。

·P2口：P2是一带有内部上拉电阻的8位双向的I/O端口。

课题序号101 教学班级教学课时 1 教学形式多媒体教学课题名称音乐彩灯--认识AT89S52单片机使用教具课件，多媒体教学了解AT89S52单片机的硬件结构及其作用，能够在任务教学目的中加以应用教学重点单片机的组成及引脚功能教学难点单片机各部分电路及引脚功能更新、补充、无删节内容课前准备制作课件，整理任务指导书课外作业浏览各个单片机学习网站，培养兴趣，拓宽视野，提高板书设计一、认识AT89S52单片机（一）AT89S52的内部结构（二）引脚功能介绍教学自主学习能力感想课堂教学安排教学环节主要教学内容教学手段与方式课程导入（以启发式引入本课的主要内容）讲授新课（讲解本课的主要内容）我们知道，一台能够工作的计算机要有这样几个部分构成：CPU、存储器、I/O接口和定时与中断系统。

在个人计算机上这些部分被分成若干块芯片，安装一个称之为主板的印刷线路板上。

当这些部分全部被做到一块集成电路芯片中了，就称为单片（单芯片）机。

单片机在家电产品以及控制领域中运用越来越广泛，从现在开始我们就进入单片机的学习。

一、认识AT89S52单片机（一）AT89S52的内部结构1.CPU（Central Processing Unit，中央处理器）是AT89S52内部的字长为8位的中央启发式（引导学生思考问题，引出课程内容）实物展示（单片机实物展示）讲授法（结合课件及实物，讲解单片机的基本结构，处理单元，它由运算器和控制器两部分组成。

CPU是单片机的核心。

（1）运算器运算器以ALU（Arithmetic Logic Unit，算术逻辑单元）为核心，包括累加器A （Accumulator）、PSW（Program Status Word，程序状态字寄存器）、B寄存器、两个8位暂存器TMP1和TMP2等部件。

其中，ALU的运算功能很强，可以运行加、减、乘、除、加1、减1、BCD数十进制数调整、比较等算术运算，也可以进行与、或、非、异或等逻辑运算，同时还能完成循环移位、判断和程序转移等控制功能。

单片机的引脚电平与功能配置解析
AT89S52单片机的引脚接高电平或低电平的区别主要取决于引脚的功能和配置。

一般来说，一些引脚会有高电平和低电平两种状态，而另一些引脚则可能只有一种状态。

对于那些有两种状态的引脚，高电平和低电平通常对应于不同的功能。

例如，在单片机内部，一些引脚可能会被配置为输入引脚，用于接收外部设备的信号，而另一些引脚可能会被配置为输出引脚，用于向外部设备发送信号。

如果一个引脚被配置为输入引脚，那么当它接收到高电平时，它可能会被认为是在接收一个有效的信号；而当它接收到低电平时，这个信号可能被认为是无效的。

相反，如果一个引脚被配置为输出引脚，那么当它输出高电平时，它可能会驱动外部设备的一个特定状态；而当它输出低电平时，它可能是在关闭或禁用这个设备。

然而，具体的情况会根据单片机的型号和设计以及引脚的具体配置而有所不同。

为了理解特定单片机的行为，您可能需要查阅相关的技术手册或数据表。

51单片机各引脚及端口详解51单片机引脚功能：MCS-51是标准的40引脚双列直插式集成电路芯片,引脚分布请参照----单片机引脚图：l P0.0~P0.7 P0口8位双向口线（在引脚的39~32号端子）。

l P1.0~P1.7 P1口8位双向口线（在引脚的1~8号端子）。

l P2.0~P2.7 P2口8位双向口线（在引脚的21~28号端子）。

l P3.0~P3.7 P2口8位双向口线（在引脚的10~17号端子）。

这4个I/O口具有不完全相同的功能,大家可得学好了,其它书本里虽然有,但写的太深,对于初学者来说很难理解的,我这里都是按我自已的表达方式来写的,相信你也能够理解的。

P0口有三个功能：1、外部扩展存储器时,当做数据总线（如图1中的D0~D7为数据总线接口）2、外部扩展存储器时,当作地址总线（如图1中的A0~A7为地址总线接口）3、不扩展时,可做一般的I/O使用,但内部无上拉电阻,作为输入或输出时应在外部接上拉电阻。

P1口只做I/O口使用：其内部有上拉电阻。

P2口有两个功能：1、扩展外部存储器时,当作地址总线使用2、做一般I/O口使用,其内部有上拉电阻;P3口有两个功能：除了作为I/O使用外（其内部有上拉电阻）,还有一些特殊功能,由特殊寄存器来设置,具体功能请参考我们后面的引脚说明。

有内部EPROM的单片机芯片（例如8751）,为写入程序需提供专门的编程脉冲和编程电源,这些信号也是由信号引脚的形式提供的,即：编程脉冲：30脚（ALE/PROG）编程电压（25V）：31脚（EA/Vpp）接触过工业设备的兄弟可能会看到有些印刷线路板上会有一个电池,这个电池是干什么用的呢？这就是单片机的备用电源,当外接电源下降到下限值时,备用电源就会经第二功能的方式由第9脚（即RST/VPD）引入,以保护内部RAM中的信息不会丢失。

在介绍这四个I/O口时提到了一个“上拉电阻”那么上拉电阻又是一个什么东东呢？他起什么作用呢？都说了是电阻那当然就是一个电阻啦,当作为输入时,上拉电阻将其电位拉高,若输入为低电平则可提供电流源;所以如果P0口如果作为输入时,处在高阻抗状态,只有外接一个上拉电阻才能有效。