下载文档原格式
EZ-USB FX2LP™ USB MicrocontrollerCY7C68013A/CY7C68014A CY7C68015A/CY7C68016A1.0Features (CY7C68013A/14A/15A/16A)•USB 2.0–USB-IF high speed certified (TID # 40440111)•Single-chip integrated USB 2.0 transceiver, smart SIE, and enhanced 8051 microprocessor•Fit, form and function compatible with the FX2—Pin-compatible—Object-code-compatible—Functionally-compatible (FX2LP is a superset)•Ultra Low power: I CC no more than 85 mA in any mode —Ideal for bus and battery powered applications •Software: 8051 code runs from:—Internal RAM, which is downloaded via USB —Internal RAM, which is loaded from EEPROM —External memory device (128 pin package)•16 KBytes of on-chip Code/Data RAM•Four programmable BULK/INTERRUPT/ISOCHRO-NOUS endpoints—Buffering options: double, triple, and quad•Additional programmable (BULK/INTERRUPT) 64-byte endpoint•8- or 16-bit external data interface •Smart Media Standard ECC generation •GPIF (General Programmable Interface)—Allows direct connection to most parallel interface—Programmable waveform descriptors and configu-ration registers to define waveforms—Supports multiple Ready (RDY) inputs and Control (CTL) outputs•Integrated, industry-standard enhanced 8051—48-MHz, 24-MHz, or 12-MHz CPU operation —Four clocks per instruction cycle —Two USARTS—Three counter/timers—Expanded interrupt system —Two data pointers•3.3V operation with 5V tolerant inputs•Vectored USB interrupts and GPIF/FIFO interrupts •Separate data buffers for the Set-up and Data portions of a CONTROL transfer•Integrated I 2C controller, runs at 100 or 400 kHz •Four integrated FIFOs—Integrated glue logic and FIFOs lower system cost —Automatic conversion to and from 16-bit buses —Master or slave operation—Uses external clock or asynchronous strobes —Easy interface to ASIC and DSP ICs•Available in Commercial and Industrial temperature grade (all packages except VFBGA)A d d r e s s (16)x20PLL/0.5/1.0/2.08051 Core 12/24/48 MHz,four clocks/cycleI 2CVCC1.5kD+D–A d d r e s s (16) / D a t aB u s (8)FX2LPGPIFCY Smart USB 1.1/2.0EngineUSB 2.0XCVR16 KB RAM4 kB FIFOIntegrated full- and high-speedXCVRAdditional I/Os (24)ADDR (9)CTL (6)RDY (6)8/16D a t a (8)24 MHz Ext. XTALEnhanced USB core Simplifies 8051 code “Soft Configuration”Easy firmware changes FIFO and endpoint memory (master or slave operation)Up to 96 MBytes/s burst rateGeneralprogrammable I/F to ASIC/DSP or bus standards such as ATAPI, EPP , etc.Abundant I/Oincluding two USARTS High-performance micro using standard toolswith lower-power optionsMasterFigure 1-1. Block Diagramconnected for full speedECC1.1Features (CY7C68013A/14A only)•CY7C68014A: Ideal for battery powered applications —Suspend current: 100 µA (typ)•CY7C68013A: Ideal for non-battery powered applica-tions—Suspend current: 300 µA (typ)•Available in five lead-free packages with up to 40 GPIOs —128-pin TQFP (40 GPIOs), 100-pin TQFP (40 GPIOs),56-pin QFN (24 GPIOs), 56-pin SSOP (24 GPIOs), and 56-pin VFBGA (24 GPIOs)1.2Features (CY7C68015A/16A only)•CY7C68016A: Ideal for battery powered applications—Suspend current: 100 µA (typ)•CY7C68015A: Ideal for non-battery powered applica-tions—Suspend current: 300 µA (typ)•Available in lead-free 56-pin QFN package (26 GPIOs)—2 more GPIOs than CY7C68013A/14A enabling addi-tional features in same footprintCypress Semiconductor Corporation’s (Cypress’s) EZ-USB FX2LP™ (CY7C68013A/14A) is a low-power version of the EZ-USB FX2™ (CY7C68013), which is a highly integrated, low-power USB 2.0 microcontroller. By integrating the USB 2.0 transceiver, serial interface engine (SIE), enhanced 8051 microcontroller, and a programmable peripheral interface in a single chip, Cypress has created a very cost-effective solution that provides superior time-to-market advantages with low power to enable bus powered applications.The ingenious architecture of FX2LP results in data transfer rates of over 53 Mbytes per second, the maximum-allowable USB 2.0 bandwidth, while still using a low-cost 8051 microcon-troller in a package as small as a 56 VFBGA (5mm x 5mm). Because it incorporates the USB 2.0 transceiver, the FX2LP is more economical, providing a smaller footprint solution than USB 2.0 SIE or external transceiver implementations. With EZ-USB FX2LP, the Cypress Smart SIE handles most of the USB 1.1 and 2.0 protocol in hardware, freeing the embedded microcontroller for application-specific functions and decreasing development time to ensure USB compatibility. The General Programmable Interface (GPIF) and Master/Slave Endpoint FIFO (8- or 16-bit data bus) provides an easy and glueless interface to popular interfaces such as ATA, UTOPIA, EPP, PCMCIA, and most DSP/processors. The FX2LP draws considerably less current than the FX2 (CY7C68013), has double the on-chip code/data RAM and is fit, form and function compatible with the 56-, 100-, and 128-pin FX2.Five packages are defined for the family: 56VFBGA, 56 SSOP, 56 QFN, 100 TQFP, and 128 TQFP.2.0 Applications•Portable video recorder•MPEG/TV conversion•DSL modems•ATA interface•Memory card readers•Legacy conversion devices•Cameras•Scanners•Home PNA•Wireless LAN•MP3 players•NetworkingThe “Reference Designs” section of the Cypress web site provides additional tools for typical USB 2.0 applications. Each reference design comes complete with firmware source and object code, schematics, and documentation. Please visit for more information.3.0Functional Overview3.1USB Signaling SpeedFX2LP operates at two of the three rates defined in the USB Specification Revision 2.0, dated April 27, 2000:•Full speed, with a signaling bit rate of 12 Mbps •High speed, with a signaling bit rate of 480 Mbps.FX2LP does not support the low-speed signaling mode of 1.5Mbps.3.28051 MicroprocessorThe 8051 microprocessor embedded in the FX2LP family has 256 bytes of register RAM, an expanded interrupt system,three timer/counters, and two USARTs.3.2.18051 Clock FrequencyFX2LP has an on-chip oscillator circuit that uses an external 24-MHz (±100-ppm) crystal with the following characteristics:•Parallel resonant •Fundamental mode •500-µW drive level•12-pF (5% tolerance) load capacitors.An on-chip PLL multiplies the 24-MHz oscillator up to 480MHz, as required by the transceiver/PHY , and internal counters divide it down for use as the 8051 clock. The default 8051 clock frequency is 12 MHz. The clock frequency of the 8051 can be changed by the 8051 through the CPUCS register, dynamically.The CLKOUT pin, which can be three-stated and inverted using internal control bits, outputs the 50% duty cycle 8051clock, at the selected 8051 clock frequency—48, 24, or 12MHz.3.2.2USARTSFX2LP contains two standard 8051 USARTs, addressed via Special Function Register (SFR) bits. The USART interface pins are available on separate I/O pins, and are not multi-plexed with port pins.UART0 and UART1 can operate using an internal clock at 230KBaud with no more than 1% baud rate error. 230-KBaud operation is achieved by an internally derived clock source that generates overflow pulses at the appropriate time. The internal clock adjusts for the 8051 clock rate (48, 24, 12 MHz)such that it always presents the correct frequency for 230-KBaud operation.[1]3.2.3Special Function RegistersCertain 8051 SFR addresses are populated to provide fast access to critical FX2LP functions. These SFR additions are shown in Table 3-1. Bold type indicates non-standard,enhanced 8051 registers. The two SFR rows that end with “0”and “8” contain bit-addressable registers. The four I/O ports A–D use the SFR addresses used in the standard 8051 for ports 0–3, which are not implemented in FX2LP . Because of the faster and more efficient SFR addressing, the FX2LP I/O ports are not addressable in external RAM space (using the MOVX instruction).3.3I 2C BusFX2LP supports the I 2C bus as a master only at 100-/400-KHz.SCL and SDA pins have open-drain outputs and hysteresis inputs. These signals must be pulled up to 3.3V, even if no I 2C device is connected.3.4BusesAll packages: 8- or 16-bit “FIFO” bidirectional data bus, multi-plexed on I/O ports B and D. 128-pin package: adds 16-bit output-only 8051 address bus, 8-bit bidirectional data bus.Figure 3-1. Crystal Configuration12 pf12 pf24 MHz20 × PLLC1C212-pF capacitor values assumes a trace capacitanceof 3 pF per side on a four-layer FR4 PCANote:1.115-KBaud operation is also possible by programming the 8051 SMOD0 or SMOD1 bits to a “1” for UART0 and/or UART1, respectively.3.5USB Boot MethodsDuring the power-up sequence, internal logic checks the I2C port for the connection of an EEPROM whose first byte is either 0xC0 or 0xC2. If found, it uses the VID/PID/DID values in the EEPROM in place of the internally stored values (0xC0), or it boot-loads the EEPROM contents into internal RAM (0xC2). If no EEPROM is detected, FX2LP enumerates using internally stored descriptors. The default ID values for FX2LP are VID/PID/DID (0x04B4, 0x8613, 0xAxxx where xxx = Chip revision).[2]3.6ReNumeration™Because the FX2LP’s configuration is soft, one chip can take on the identities of multiple distinct USB devices.When first plugged into USB, the FX2LP enumerates automat-ically and downloads firmware and USB descriptor tables over the USB cable. Next, the FX2LP enumerates again, this time as a device defined by the downloaded information. This patented two-step process, called ReNumeration™, happens instantly when the device is plugged in, with no hint that the initial download step has occurred.Two control bits in the USBCS (USB Control and Status) register control the ReNumeration process: DISCON and RENUM. To simulate a USB disconnect, the firmware sets DISCON to 1. To reconnect, the firmware clears DISCON to 0. Before reconnecting, the firmware sets or clears the RENUM bit to indicate whether the firmware or the Default USB Device will handle device requests over endpoint zero: if RENUM = 0, the Default USB Device will handle device requests; if RENUM = 1, the firmware will.3.7Bus-powered ApplicationsThe FX2LP fully supports bus-powered designs by enumer-ating with less than 100 mA as required by the USB 2.0 speci-fication.3.8Interrupt System3.8.1INT2 Interrupt Request and Enable RegistersFX2LP implements an autovector feature for INT2 and INT4. There are 27 INT2 (USB) vectors, and 14 INT4 (FIFO/GPIF) vectors. See EZ-USB Technical Reference Manual (TRM) for more details.3.8.2USB-Interrupt AutovectorsThe main USB interrupt is shared by 27 interrupt sources. To save the code and processing time that normally would be required to identify the individual USB interrupt source, the FX2LP provides a second level of interrupt vectoring, called Autovectoring. When a USB interrupt is asserted, the FX2LP pushes the program counter onto its stack then jumps to address 0x0043, where it expects to find a “jump” instruction to the USB Interrupt service routine.Table 3-1. Special Function Registersx8x9x Ax Bx Cx Dx Ex Fx 0IOA IOB IOC IOD SCON1PSW ACC B 1SP EXIF INT2CLR IOE SBUF12DPL0MPAGE INT4CLR OEA3DPH0OEB4DPL1OEC5DPH1OED6DPS OEE7PCON8TCON SCON0IE IP T2CON EICON EIE EIP 9TMOD SBUF0A TL0AUTOPTRH1EP2468STAT EP01STAT RCAP2LB TL1AUTOPTRL1EP24FIFOFLGS GPIFTRIG RCAP2HC TH0reserved EP68FIFOFLGS TL2D TH1AUTOPTRH2GPIFSGLDATH TH2E CKCON AUTOPTRL2GPIFSGLDATLXF reserved AUTOPTRSET-UP GPIFSGLDATLNOXTable 3-2. Default ID Values for FX2LPDefault VID/PID/DIDVendor ID0x04B4Cypress SemiconductorProduct ID0x8613EZ-USB FX2LPDevice release0xAnnn Depends on chip revision(nnn = chip revision where firstsilicon = 001)Note:2.The I2C bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this detection method does not work properly.The FX2LP jump instruction is encoded as follows.If Autovectoring is enabled (AV2EN = 1 in the INTSET-UP register), the FX2LP substitutes its INT2VEC byte. Therefore, if the high byte (“page”) of a jump-table address is preloaded at location 0x0044, the automatically-inserted INT2VEC byte at 0x0045 will direct the jump to the correct address out of the 27 addresses within the page.3.8.3FIFO/GPIF Interrupt (INT4)Just as the USB Interrupt is shared among 27 individual USB-interrupt sources, the FIFO/GPIF interrupt is shared among 14 individual FIFO/GPIF sources. The FIFO/GPIF Interrupt, like the USB Interrupt, can employ autovectoring. Table3-4 shows the priority and INT4VEC values for the 14 FIFO/GPIF interrupt sources.Table 3-3. INT2 USB InterruptsUSB INTERRUPT TABLE FOR INT2 Priority INT2VEC Value Source Notes1 00SUDAV Set-up Data Available2 04 SOF Start of Frame (or microframe)3 08SUTOK Set-up Token Received4 0C SUSPEND USB Suspend request5 10USB RESET Bus reset6 14HISPEED Enteredhigh speed operation7 18 EP0ACK FX2LP ACK’d the CONTROL Handshake8 1C reserved9 20 EP0-IN EP0-IN ready to be loaded with data10 24 EP0-OUT EP0-OUT has USB data11 28 EP1-IN EP1-IN ready to be loaded with data12 2C EP1-OUT EP1-OUT has USB data13 30 EP2 IN: buffer available. OUT: buffer has data14 34 EP4 IN: buffer available. OUT: buffer has data15 38 EP6 IN: buffer available. OUT: buffer has data16 3C EP8 IN: buffer available. OUT: buffer has data17 40 IBN IN-Bulk-NAK (any IN endpoint)18 44reserved19 48 EP0PING EP0 OUT was Pinged and it NAK’d20 4C EP1PING EP1 OUT was Pinged and it NAK’d21 50 EP2PING EP2 OUT was Pinged and it NAK’d22 54 EP4PING EP4 OUT was Pinged and it NAK’d23 58 EP6PING EP6 OUT was Pinged and it NAK’d24 5C EP8PING EP8 OUT was Pinged and it NAK’d25 60 ERRLIMIT Bus errors exceeded the programmed limit26 6427 68 reserved28 6C reserved29 70 EP2ISOERR ISO EP2 OUT PID sequence error30 74 EP4ISOERR ISO EP4 OUT PID sequence error31 78 EP6ISOERR ISO EP6 OUT PID sequence error32 7C EP8ISOERR ISO EP8 OUT PID sequence errorIf Autovectoring is enabled (AV4EN = 1 in the INTSET-UP register), the FX 2LP substitutes its INT4VEC byte. Therefore, if the high byte (“page”) of a jump-table address is preloaded at location 0x0054, the automatically-inserted INT4VEC byte at 0x0055 will direct the jump to the correct address out of the 14 addresses within the page. When the ISR occurs, the FX2LP pushes the program counter onto its stack then jumps to address 0x0053, where it expects to find a “jump” instruction to the ISR Interrupt service routine.3.9Reset and Wakeup3.9.1Reset PinThe input pin, RESET#, will reset the FX2LP when asserted. This pin has hysteresis and is active LOW. When a crystal is used with the CY7C680xxA the reset period must allow for the stabilization of the crystal and the PLL. This reset period should be approximately 5 ms after VCC has reached 3.0V. If the crystal input pin is driven by a clock signal the internal PLL stabilizes in 200 µs after VCC has reached 3.0V[3]. Figure3-2 shows a power-on reset condition and a reset applied during operation. A power-on reset is defined as the time reset is asserted while power is being applied to the circuit. A powered reset is defined to be when the FX2LP has previously been powered on and operating and the RESET# pin is asserted. Cypress provides an application note which describes and recommends power on reset implementation and can be found on the Cypress web site. For more information on reset imple-mentation for the FX2 family of products visit the .Table 3-4. Individual FIFO/GPIF Interrupt SourcesPriority INT4VEC Value Source Notes 180EP2PF Endpoint 2 Programmable Flag2 84 EP4PF Endpoint 4 Programmable Flag388EP6PF Endpoint 6 Programmable Flag48C EP8PF Endpoint 8 Programmable Flag590EP2EF Endpoint 2 Empty Flag694EP4EF Endpoint 4 Empty Flag798EP6EF Endpoint 6 Empty Flag89C EP8EF Endpoint 8 Empty Flag9A0 EP2FF Endpoint 2 Full Flag10A4EP4FF Endpoint 4 Full Flag11 A8EP6FF Endpoint 6 Full Flag12AC EP8FF Endpoint 8 Full Flag13 B0GPIFDONE GPIF Operation Complete14 B4GPIFWF GPIF WaveformNote:3.If the external clock is powered at the same time as the CY7C680xxA and has a stabilization wait period, it must be added to the 200 µs.3.9.2Wakeup PinsThe 8051 puts itself and the rest of the chip into a power-down mode by setting PCON.0 = 1. This stops the oscillator and PLL. When WAKEUP is asserted by external logic, the oscil-lator restarts, after the PLL stabilizes, and then the 8051receives a wakeup interrupt. This applies whether or not FX2LP is connected to the USB.The FX2LP exits the power-down (USB suspend) state using one of the following methods:•USB bus activity (if D+/D– lines are left floating, noise on these lines may indicate activity to the FX2LP and initiate a wakeup).•External logic asserts the WAKEUP pin •External logic asserts the PA3/WU2 pin.The second wakeup pin, WU2, can also be configured as a general purpose I/O pin. This allows a simple external R-C network to be used as a periodic wakeup source. Note that WAKEUP is by default active LOW.3.10Program/Data RAM3.10.1SizeThe FX2LP has 16 KBytes of internal program/data RAM,where PSEN#/RD# signals are internally ORed to allow the 8051 to access it as both program and data memory. No USB control registers appear in this space.Two memory maps are shown in the following diagrams:Figure 3-3 Internal Code Memory, EA = 0Figure 3-4 External Code Memory, EA = 1.3.10.2Internal Code Memory, EA = 0This mode implements the internal 16-KByte block of RAM (starting at 0) as combined code and data memory. When external RAM or ROM is added, the external read and write strobes are suppressed for memory spaces that exist inside the chip. This allows the user to connect a 64-KByte memory without requiring address decodes to keep clear of internal memory spaces.Only the internal 16 KBytes and scratch pad 0.5 KBytes RAM spaces have the following access:•USB download •USB upload •Set-up data pointer •I 2C interface boot load.3.10.3External Code Memory, EA = 1The bottom 16 KBytes of program memory is external, and therefore the bottom 16 KBytes of internal RAM is accessible only as data memory.Figure 3-2. Reset Timing PlotsV IL 0V3.3V 3.0VT RESETVCCRESET#Power on ResetT RESETVCCRESET#V IL Powered Reset3.3V0VTable 3-5. Reset Timing ValuesConditionT RESET Power-on Reset with crystal 5 msPower-on Reset with external clock200 µs + Clock stability timePowered Reset 200 µsFigure 3-3. Internal Code Memory, EA = 0Inside FX2LPOutside FX2LP7.5 KBytes USB regs and 4K FIFO buffers (RD#,WR#)0.5 KBytes RAM Data (RD#,WR#)*(OK to populate data memory here—RD#/WR#strobes are not active)40 KBytes External Data Memory (RD#,WR#)(Ok to populate data memory here—RD#/WR#strobes are not active)16 KBytes RAM Code and Data(PSEN#,RD#,WR#)*48 KBytes External Code Memory (PSEN#)(OK to populate programmemory here—PSEN# strobe is not active)*SUDPTR, USB upload/download, I 2C interface boot accessFFFFE200E1FF E0003FFF0000DataCodeFigure 3-4. External Code Memory, EA = 1Inside FX2LPOutside FX2LP7.5 KBytes USB regs and 4K FIFO buffers (RD#,WR#)0.5 KBytes RAM Data (RD#,WR#)*(OK to populatedata memory here—RD#/WR#strobes are not active)40 KBytes External Data Memory (RD#,WR#)(Ok to populate data memory here—RD#/WR#strobes are not active)16 KBytes RAM Data(RD#,WR#)*64 KBytes External Code Memory (PSEN#)*SUDPTR, USB upload/download, I 2C interface boot accessFFFFE200E1FFE0003FFF0000DataCode3.11Register Addresses3.12Endpoint RAM3.12.1Size•3× 64 bytes (Endpoints 0 and 1)•8 × 512 bytes (Endpoints 2, 4, 6, 8)3.12.2Organization•EP0•Bidirectional endpoint zero, 64-byte buffer •EP1IN, EP1OUT•64-byte buffers, bulk or interrupt •EP2,4,6,8•Eight 512-byte buffers, bulk, interrupt, or isochronous. EP4 and EP8 can be double buffered, while EP2 and 6 can be either double, triple, or quad buffered. For high-speed end-point configuration options, see Figure 3-5.3.12.3Set-up Data BufferA separate 8-byte buffer at 0xE6B8-0xE6BF holds the Set-up data from a CONTROL transfer.3.12.4Endpoint Configurations (High-speed Mode)Endpoints 0 and 1 are the same for every configuration.Endpoint 0 is the only CONTROL endpoint, and endpoint 1 can be either BULK or INTERRUPT. The endpoint buffers can be configured in any 1 of the 12 configurations shown in the vertical columns. When operating in full-speed BULK mode only the first 64 bytes of each buffer are used. For example in high-speed, the max packet size is 512 bytes but in full-speed it is 64 bytes. Even though a buffer is configured to be a 512byte buffer, in full-speed only the first 64 bytes are used. The unused endpoint buffer space is not available for other opera-tions. An example endpoint configuration would be:FFFFE800E7BF E740E73F E700E6FF E500E4FF E480E47F E400E200E1FFE000E3FF EFFF2 KBytes RESERVED64 Bytes EP0 IN/OUT 64 Bytes RESERVED 8051 Addressable RegistersReserved (128)128 bytes GPIF Waveforms512 bytes 8051 xdata RAMF000(512)Reserved (512)E78064 Bytes EP1OUT E77F 64 Bytes EP1IN E7FF E7C0 4 KBytes EP2-EP8buffers(8 x 512)EP2–1024 double buffered; EP6–512 quad buffered (column 8).3.12.5Default Full-Speed Alternate Settings3.12.6Default High-Speed Alternate Settings6464645125121024102410241024102410241024512512512512512512512512512512EP0 IN&OUTEP1 IN EP1 OUTFigure 3-5. Endpoint Configuration1024102410245125125125125125125125125125125125125125125125125125125125125125125125125125125125125125121024102410241024102410245125121024102451251251251251251251251210241024512512512512512512646464646464646464646464646464646464646464646464646464646464646464123456789101112Table 3-6. Default Full-Speed Alternate Settings [4, 5]Alternate Setting 0123ep064646464ep1out 064 bulk 64 int 64 int ep1in 064 bulk 64 int 64 int ep2064 bulk out (2×)64 int out (2×)64 iso out (2×)ep4064 bulk out (2×)64 bulk out (2×)64 bulk out (2×)ep6064 bulk in (2×)64 int in (2×)64 iso in (2×)ep8064 bulk in (2×)64 bulk in (2×)64 bulk in (2×)Notes:4.“0” means “not implemented.”5.“2×” means “double buffered.”6.Even though these buffers are 64 bytes, they are reported as 512 for USB 2.0 compliance. The user must never transfer packets larger than 64 bytes to EP1.Table 3-7. Default High-Speed Alternate Settings [4, 5]Alternate Setting 0123ep064646464ep1out 0512 bulk [6]64 int 64 int ep1in 0512 bulk [6]64 int64 intep20512 bulk out (2×)512 int out (2×)512 iso out (2×)ep40512 bulk out (2×)512 bulk out (2×)512 bulk out (2×)ep60512 bulk in (2×)512 int in (2×)512 iso in (2×)ep80512 bulk in (2×)512 bulk in (2×)512 bulk in (2×)3.13External FIFO Interface3.13.1ArchitectureThe FX2LP slave FIFO architecture has eight 512-byte blocks in the endpoint RAM that directly serve as FIFO memories, and are controlled by FIFO control signals (such as IFCLK, SLCS#, SLRD, SLWR, SLOE, PKTEND, and flags).In operation, some of the eight RAM blocks fill or empty from the SIE, while the others are connected to the I/O transfer logic. The transfer logic takes two forms, the GPIF for internally generated control signals, or the slave FIFO interface for externally controlled transfers.3.13.2Master/Slave Control SignalsThe FX2LP endpoint FIFOS are implemented as eight physi-cally distinct 256x16 RAM blocks. The 8051/SIE can switch any of the RAM blocks between two domains, the USB (SIE) domain and the 8051-I/O Unit domain. This switching is done virtually instantaneously, giving essentially zero transfer time between “USB FIFOS” and “Slave FIFOS.” Since they are physically the same memory, no bytes are actually transferred between buffers.At any given time, some RAM blocks are filling/emptying with USB data under SIE control, while other RAM blocks are available to the 8051 and/or the I/O control unit. The RAM blocks operate as single-port in the USB domain, and dual-port in the 8051-I/O domain. The blocks can be configured as single, double, triple, or quad buffered as previ-ously shown.The I/O control unit implements either an internal-master (M for master) or external-master (S for Slave) interface.In Master (M) mode, the GPIF internally controls FIFOADR[1..0] to select a FIFO. The RDY pins (two in the 56-pin package, six in the 100-pin and 128-pin packages) can be used as flag inputs from an external FIFO or other logic if desired. The GPIF can be run from either an internally derived clock or externally supplied clock (IFCLK), at a rate that transfers data up to 96 Megabytes/s (48-MHz IFCLK with 16-bit interface).In Slave (S) mode, the FX2LP accepts either an internally derived clock or externally supplied clock (IFCLK, max. frequency 48 MHz) and SLCS#, SLRD, SLWR, SLOE, PKTEND signals from external logic. When using an external IFCLK, the external clock must be present before switching to the external clock with the IFCLKSRC bit. Each endpoint can individually be selected for byte or word operation by an internal configuration bit, and a Slave FIFO Output Enable signal SLOE enables data of the selected width. External logic must insure that the output enable signal is inactive when writing data to a slave FIFO. The slave interface can also operate asynchronously, where the SLRD and SLWR signals act directly as strobes, rather than a clock qualifier as in synchronous mode. The signals SLRD, SLWR, SLOE and PKTEND are gated by the signal SLCS#.3.13.3GPIF and FIFO Clock RatesAn 8051 register bit selects one of two frequencies for the internally supplied interface clock: 30 MHz and 48 MHz. Alter-natively, an externally supplied clock of 5 MHz–48 MHz feeding the IFCLK pin can be used as the interface clock. IFCLK can be configured to function as an output clock when the GPIF and FIFOs are internally clocked. An output enable bit in the IFCONFIG register turns this clock output off, if desired. Another bit within the IFCONFIG register will invert the IFCLK signal whether internally or externally sourced. 3.14GPIFThe GPIF is a flexible 8- or 16-bit parallel interface driven by a user-programmable finite state machine. It allows the CY7C68013A/15A to perform local bus mastering, and can implement a wide variety of protocols such as ATA interface, printer parallel port, and Utopia.The GPIF has six programmable control outputs (CTL), nine address outputs (GPIFADRx), and six general-purpose ready inputs (RDY). The data bus width can be 8 or 16 bits. Each GPIF vector defines the state of the control outputs, and deter-mines what state a ready input (or multiple inputs) must be before proceeding. The GPIF vector can be programmed to advance a FIFO to the next data value, advance an address, etc. A sequence of the GPIF vectors make up a single waveform that will be executed to perform the desired data move between the FX2LP and the external device.3.14.1Six Control OUT SignalsThe 100- and 128-pin packages bring out all six Control Output pins (CTL0-CTL5). The 8051 programs the GPIF unit to define the CTL waveforms. The 56-pin package brings out three of these signals, CTL0–CTL2. CTLx waveform edges can be programmed to make transitions as fast as once per clock (20.8 ns using a 48-MHz clock).3.14.2Six Ready IN SignalsThe 100- and 128-pin packages bring out all six Ready inputs (RDY0–RDY5). The 8051 programs the GPIF unit to test the RDY pins for GPIF branching. The 56-pin package brings out two of these signals, RDY0–1.3.14.3Nine GPIF Address OUT SignalsNine GPIF address lines are available in the 100- and 128-pin packages, GPIFADR[8..0]. The GPIF address lines allow indexing through up to a 512-byte block of RAM. If more address lines are needed, I/O port pins can be used.3.14.4Long Transfer ModeIn master mode, the 8051 appropriately sets GPIF transaction count registers (GPIFTCB3, GPIFTCB2, GPIFTCB1, or GPIFTCB0) for unattended transfers of up to 232 transactions. The GPIF automatically throttles data flow to prevent under or overflow until the full number of requested transactions complete. The GPIF decrements the value in these registers to represent the current status of the transaction.。
SP601 Hardware User GuideUG518 (v1.7) September 26, 2012© Copyright 2009–2012 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. DISCLAIMERThe information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available “AS IS” and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR ST ATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials, or to advise you of any corrections or update. Y ou may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at /warranty.htm; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical Applications:/warranty.htm#critapps.Revision HistoryThe following table shows the revision history for this document.Date Version Revision07/15/09 1.0Initial Xilinx release.08/19/09 1.1•Added Appendix B, VITA 57.1 FMC LPC Connector Pinout.•Updated Figure1-17.•Updated Table1-4, Table1-19, and Table1-22.•Added introductory paragraph to Appendix C, SP601 Master UCF.•Miscellaneous typographical edits and new user guide template.05/17/10 1.2•Updated Figure1-1, Figure1-2, Figure1-14, Figure1-18, Table1-9, Table1-1,Table1-11, and Table1-16.•Added Figure1-7, Figure1-8, and Table1-13.•Updated 9. VITA 57.1 FMC-LPC Connector, page25, Appendix B, VITA 57.1 FMCLPC Connector Pinout, and Appendix C, SP601 Master UCF.06/16/10 1.3Reversed order of 15. Configuration Options and 16. Power Management. Updated 1.Spartan-6 XC6SLX16-2CSG324 FPGA and 2. 128 MB DDR2 Component Memory. AddedTable1-26. Added UG394, Spartan-6 FPGA Power Management User Guide to Appendix D,References.09/24/10 1.4Added Power System Test Points, including Table1-25.02/16/11 1.5Added note and revised header description to indicate the I/Os support LVCMOS25signaling on page34. Revised oscillator manufacturer information from Epson to SiTimeon page page23 and page51.07/18/11 1.6Corrected wording from “PPM frequency jitter” to “PPM frequency stability” in sectionOscillator (Differential), page23. Added Table1-15, page27.09/26/12 1.7Added Regulatory and Compliance Information, page53.SP601 Hardware User Guide UG518 (v1.7) September 26, 2012SP601 Hardware User Guide 3UG518 (v1.7) September 26, 2012Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Preface: About This GuideGuide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Additional Support Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Chapter 1: SP601 Evaluation BoardOverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Additional Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Related Xilinx Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101. Spartan-6 XC6SLX16-2CSG324 FPGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11I/O Voltage Rails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122. 128 MB DDR2 Component Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123. SPI x4 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154. Linear Flash BPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175. 10/100/1000 Tri-Speed Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196. USB-to-UART Bridge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217. IIC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228-Kb NV Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228. Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Oscillator (Differential). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Oscillator Socket (Single-Ended, 2.5V or 3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24SMA Connectors (Differential). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249. VITA 57.1 FMC-LPC Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2510. Status LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2811. FPGA Awake LED and Suspend Jumper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2912. FPGA INIT and DONE LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3013. User I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3114. FPGA_PROG_B Pushbutton Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3515. Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36JTAG Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3616. Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37AC Adapter and 5V Input Power Jack/Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Onboard Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Power System Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Table of ContentsAppendix A: Default Jumper and Switch SettingsAppendix B: VITA 57.1 FMC LPC Connector PinoutAppendix C: SP601 Master UCFAppendix D: ReferencesAppendix E: Regulatory and Compliance InformationDirectives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Standards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Electromagnetic Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 SP601 Hardware User GuideUG518 (v1.7) September 26, 2012SP601 Hardware User Guide 5UG518 (v1.7) September 26, 2012PrefaceAbout This GuideThis manual accompanies the Spartan®-6 FPGA SP601 Evaluation Board and contains information about the SP601 hardware and software tools.Guide ContentsThis manual contains the following chapters:•Chapter 1, SP601 Evaluation Board , provides an overview of the SP601 evaluation board and details the components and features of the SP601 board.•Appendix A, Default Jumper and Switch Settings .•Appendix B, VITA 57.1 FMC LPC Connector Pinout .•Appendix C, SP601 Master UCF .•Appendix D, References .Additional DocumentationThe following documents are available for download at /products/spartan6.•Spartan-6 Family OverviewThis overview outlines the features and product selection of the Spartan-6 family.•Spartan-6 FPGA Data Sheet: DC and Switching CharacteristicsThis data sheet contains the DC and switching characteristic specifications for the Spartan-6 family.•Spartan-6 FPGA Packaging and Pinout SpecificationsThis specification includes the tables for device/package combinations and maximum I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications.•Spartan-6 FPGA Configuration User GuideThis all-encompassing configuration guide includes chapters on configuration interfaces (serial and parallel), multi-bitstream management, bitstream encryption, boundary-scan and JTAG configuration, and reconfiguration techniques.•Spartan-6 FPGA SelectIO Resources User GuideThis guide describes the SelectIO™ resources available in all Spartan-6 devices.•Spartan-6 FPG A Clocking Resources User GuidePreface:About This GuideThis guide describes the clocking resources available in all Spartan-6 devices,including the DCMs and PLLs.•Spartan-6 FPGA Block RAM Resources User GuideThis guide describes the Spartan-6 device block RAM capabilities.•Spartan-6 FPGA DSP48A1 Slice User GuideThis guide describes the architecture of the DSP48A1 slice in Spartan-6FPGAs andprovides configuration examples.•Spartan-6 FPGA Memory Controller User GuideThis guide describes the Spartan-6 FPGA memory controller block, a dedicatedembedded multi-port memory controller that greatly simplifies interfacingSpartan-6FPGAs to the most popular memory standards.•Spartan-6 FPGA PCB Designer’s GuideThis guide provides information on PCB design for Spartan-6 devices, with a focus onstrategies for making design decisions at the PCB and interface level.Additional Support ResourcesTo search the database of silicon and software questions and answers or to create atechnical support case in WebCase, see the Xilinx website at:/support. SP601 Hardware User GuideUG518 (v1.7) September 26, 2012Chapter1 SP601 Evaluation BoardOverviewThe SP601 board enables hardware and software developers to create or evaluate designstargeting the Spartan®-6 XC6SLX16-2CSG324 FPGA.The SP601 provides board features for evaluating the Spartan-6 family that are common tomost entry-level development environments. Some commonly used features include aDDR2 memory controller, a parallel linear flash, a tri-mode Ethernet PHY, general-purposeI/O (GPIO), and a UART. Additional functionality can be added through the VITA 57.1.1expansion connector. Features, page8 provides a general listing of the board features withdetails provided in Detailed Description, page10.Additional InformationAdditional information and support material is located at:•/sp601This information includes:•Current version of this user guide in PDF format•Example design files for demonstration of Spartan-6 FPGA features and technology•Demonstration hardware and software configuration files for the SP601 linear and SPImemory devices•Reference Design Files•Schematics in PDF format and DxDesigner schematic format•Bill of materials (BOM)•Printed-circuit board (PCB) layout in Allegro PCB format•Gerber files for the PCB (Many free or shareware Gerber file viewers are available onthe internet for viewing and printing these files.)•Additional documentation, errata, frequently asked questions, and the latest newsFor information about the Spartan-6 family of FPGA devices, including product highlights,data sheets, user guides, and application notes, see the Spartan-6 FPGA website at/support/documentation/spartan-6.htm.SP601 Hardware User Guide 7 UG518 (v1.7) September 26, 2012Chapter 1:SP601 Evaluation BoardFeaturesThe SP601 board provides the following features (see Figure1-2 and Table1-1):• 1. Spartan-6 XC6SLX16-2CSG324 FPGA• 2. 128 MB DDR2 Component Memory• 3. SPI x4 Flash• 4. Linear Flash BPI• 5. 10/100/1000 Tri-Speed Ethernet PHY•7. IIC Bus•8Kb NV memory•External access 2-pin header•VITA 57.1 FMC-LPC connector•8. Clock Generation•Oscillator (Differential)•Oscillator Socket (Single-Ended, 2.5V or 3.3V)•SMA Connectors (Differential)•9. VITA 57.1 FMC-LPC Connector•10. Status LEDs•FPGA_AWAKE•INIT•DONE•13. User I/O•User LEDs•User DIP switch•User pushbuttons•GPIO male pin header•14. FPGA_PROG_B Pushbutton Switch•15. Configuration Options• 3. SPI x4 Flash (both onboard and off-board)• 4. Linear Flash BPI•JTAG Configuration•16. Power Management•AC Adapter and 5V Input Power Jack/Switch•Onboard Power Supplies SP601 Hardware User GuideUG518 (v1.7) September 26, 2012Related Xilinx DocumentsBlock DiagramFigure1-1 shows a high-level block diagram of the SP601 and its peripherals.Figure 1-1:SP601 Features and BankingRelated Xilinx DocumentsPrior to using the SP601 Evaluation Board, users should be familiar with Xilinx resources.See the following locations for additional documentation on Xilinx tools and solutions:•ISE: /ise•Answer Browser: /support•Intellectual Property: /ipcenterSP601 Hardware User Guide 9 UG518 (v1.7) September 26, 2012SP601 Hardware User GuideUG518 (v1.7) September 26, 2012Chapter 1:SP601 Evaluation BoardDetailed DescriptionFigure 1-2 shows a board photo with numbered features corresponding to Table 1-1 and the section headings in this document.The numbered features in Figure 1-2 correlate to the features and notes listed in Table 1-1.Figure 1-2:SP601 Board PhotoUG518_02_09100912843126137115109141581316Table 1-1:SP601 FeaturesNumberFeatureNotesSchematic Page1 Spartan-6 FP G A XC6SLX16-2CS G 3242DDR2 Component Elpida EDE1116ACBG 1Gb DDR2SDRAM53SPI x4 Flash and Headers SPI select and External Headers 84Linear Flash BPIStrataFlash 8-bit (J3 device), 3 pins shared w/ SPI x481. Spartan-6 XC6SLX16-2CSG 324 FPGAA Xilinx Spartan-6 XC6SLX16-2CSG324 FPGA is installed on the SP601 Evaluation Board.ReferencesSee the Spartan-6 FPGA Data Sheet . [Ref 1]ConfigurationThe SP601 supports configuration in the following modes:•Master SPI x4•Master SPI x4 with off-board device •BPI•JTAG (using the included USB-A to Mini-B cable)For details on configuring the FPGA, see 15. Configuration Options .The Mode DIP switch SW2 is set to M[1:0] = 01 Master SPI default.ReferencesSee the Spartan-6 FPGA Configuration User Guide for more information. [Ref 2]510/100/1000 Ethernet PHY GMII Marvell Alaska PHY76RS232 UART (USB Bridge)Uses CP2103 Serial-to-USB connection 107IICGoes to Header and VITA 57.1 FMC 108Clock, socket, SMA Differential, Single-Ended, Differential 99VITA 57.1 FMC-LPC connector LVDS signals, clocks, PRSNT 610LEDs Ethernet PHY Status711LED, Header FPGA Awake LED, Suspend Header 812LEDs FPGA INIT, DONE 913LED User I/O (active-High)9DIP SwitchUser I/O (active-High)9PushbuttonUser I/O, CPU_RESET (active-High)912-pin (8 I/O) Header6 pins x 2 male header with 8 I/Os (active-High)1014Pushbutton FPGA_PROG_B915USB JTAG Cypress USB to JTAG download cable logic14, 1516Onboard PowerPower Management11,12,13Table 1-1:SP601 Features (Cont’d)NumberFeatureNotesSchematic PageSP601 Hardware User Guide I/O Voltage RailsThere are four available banks on the LX16-CSG324 device. Banks 0, 1, and 2 are connected for 2.5V I/O. Bank 3 is used for the 1.8V DDR2 component memory interface of Spartan-6 FPGA’s hard memory controller. The voltage applied to the FPGA I/O banks used by the SP601 board is summarized in Table 1-2.ReferencesSee the Spartan-6 FPGA documentation for more information at /support/documentation/spartan-6.htm .2. 128 MB DDR2 Component MemoryThere are 128MB of DDR2 memory available on the SP601 board. A 1-Gb ElpidaEDE1116ACBG (84-ball) DDR2 memory component is accessible through Bank 3 of the LX16 device. The Spartan-6 FPGA hard memory controller is used for data transfer across the DDR2 memory interface’s 16-bit data path using SSTL18 signaling. The SP601 board supports the “standard” VCCINT setting of 1.20V ± 5%. This setting provides the standard memory controller block (MCB) performance of 625Mb/s for DDR2 memory in a -2 speed grade device. Signal integrity is maintained through DDR2 resistor terminations and memory on-die terminations (ODT), as shown in Table 1-3 and Table 1-4.Table 1-2:I/O Voltage Rail of FPGA BanksFPGA BankI/O Voltage Rail0 2.5V 1 2.5V 2 2.5V 31.8VTable 1-3:Termination Resistor RequirementsSignal NameBoard TerminationOn-Die TerminationDDR2_A[14:0]49.9Ω to V TT DDR2_BA[2:0]49.9Ω to V TT DDR2_RAS_N 49.9Ω to V TT DDR2_CAS_N 49.9Ω to V TT DDR2_WE_N 49.9Ω to V TT DDR2_CS_N 100Ω to GND DDR2_CKE 4.7K Ω to GND DDR2_ODT 4.7K Ω to GNDDDR2_DQ[15:0]ODT DDR2_UDQS[P ,N], DDR2_LDQS[P ,N]ODT DDR2_UDM, DDR2_LDMODTTable 1-5 shows the connections and pin numbers for the DDR2 Component Memory.DDR2_CK[P ,N]100Ω differential at memorycomponentNotes:1.Nominal value of V TT for DDR2 interface is 0.9V .Table 1-4:FPGA On-Chip (OCT) Termination External Resistor Requirements FPGA U1 PinFPGA Pin NumberBoard Connection for OCTZIO L6No Connect RZQC2100Ω to GROUNDTable 1-5:DDR2 Component Memory ConnectionsFPGA U1 PinSchematic Net Name Memory U2Pin NumberPin NameJ7DDR2_A0M8A0J6DDR2_A1M3A1H5DDR2_A2M7A2L7DDR2_A3N2A3F3DDR2_A4N8A4H4DDR2_A5N3A5H3DDR2_A6N7A6H6DDR2_A7P2A7D2DDR2_A8P8A8D1DDR2_A9P3A9F4DDR2_A10M2A10D3DDR2_A11P7A11G6DDR2_A12R2A12L2DDR2_DQ0G8DQ0L1DDR2_DQ1G2DQ1K2DDR2_DQ2H7DQ2K1DDR2_DQ3H3DQ3H2DDR2_DQ4H1DQ4H1DDR2_DQ5H9DQ5J3DDR2_DQ6F1DQ6Table 1-3:Termination Resistor Requirements (Cont’d)Signal NameBoard Termination On-Die TerminationSP601 Hardware User Guide ReferencesSee the Elpida DDR2 SDRAM Specifications for more information. [Ref 11]Also, see the Spartan-6 FPGA Memory Controller User Guide . [Ref 3]J1DDR2_DQ7F9DQ7M3DDR2_DQ8C8DQ8M1DDR2_DQ9C2DQ9N2DDR2_DQ10D7DQ10N1DDR2_DQ11D3DQ11T2DDR2_DQ12D1DQ12T1DDR2_DQ13D9DQ13U2DDR2_DQ14B1DQ14U1DDR2_DQ15B9DQ15F2DDR2_BA0L2BA0F1DDR2_BA1L3BA1E1DDR2_BA2L1BA2E3DDR2_WE_B K3WE L5DDR2_RAS_B K7RAS K5DDR2_CAS_B L7CAS K6DDR2_ODT K9ODT G3DDR2_CLK_P J8CK G1DDR2_CLK_N K8CK H7DDR2_CKE K2CKE L4DDR2_LDQS_P F7LDQS L3DDR2_LDQS_N E8LDQS P2DDR2_UDQS_P B7UDQS P1DDR2_UDQS_N A8UDQS K3DDR2_LDM F3LDM K4DDR2_UDMB3UDMTable 1-5:DDR2 Component Memory Connections (Cont’d)FPGA U1 PinSchematic Net Name Memory U2Pin NumberPin Name3. SPI x4 FlashThe Xilinx Spartan-6 FPGA hosts a SPI interface which is accessible to the Xilinx iMPACTconfiguration tool. The SPI memory device operates at 3.0V; the Spartan-6 FPGA I/Os are3.3V tolerant and provide electrically compatible logic levels to directly access the SPI flashthrough a 2.5V bank. The XC6SLX16-2CSG324 is a master device when accessing anexternal SPI flash memory device.The SP601 SPI interface has two parallel connected configuration options (see Figure1-4):an SPI X4 (Winbond W25Q64VSFIG) 64-Mb flash memory device and a flashprogramming header (J12). J12 supports a user-defined SPI mezzanine board. The SPIconfiguration source is selected via SPI select jumper J15. For details on configuring theFPGA, see 15. Configuration Options.Figure 1-3:J12 SPI Flash Programming HeaderSP601 Hardware User Guide ReferencesSee the Winbond Serial Flash Memory Data Sheet for more information. [Ref 12]See the XPS Serial Peripheral Interface Data Sheet for more information. [Ref 4]Figure 1-4:SPI Flash Interface TopologyTable 1-6:SPI x4 Memory ConnectionsFPGA U1 PinSchematic Net Name SPI MEM U17SPI HDR J12Pin #Pin NamePinNumberPin NameV2FPGA_PROG_B 1V14FPGA_D2_MISO31IO3_HOLD_B 2T14FPGA_D1_MISO2_R 9IO2_WP_B3V3SPI_CS_B4TMS T13FPGA_MOSI_CSI_B_MISO015DIN 5TDI R13FPGA_D0_DIN_MISO_MISO18IO1_DOUT6TDO R15FPGA_CCLK16CLK7TCK 8GND 9VCC3V3J15.2SPIX4_CS_B 7CS_B4. Linear Flash BPIAn 8-bit (16MB) Numonyx linear flash memory (TE28F128J3D-75) (J3D type) is used toprovide non-volatile bitstream, code, and data storage. The J3D devices operate at 3.0V; theSpartan-6 FPGA I/Os are 3.3V tolerant and provide electrically compatible logic levels todirectly access the linear flash BPI through a 2.5V bank. For details on configuring theFPGA, see 15. Configuration Options.Figure 1-5:Linear Flash BPI InterfaceTable 1-7:BPI Memory ConnectionsFPGA U1 Pin Schematic Net Name BPI Memory U10Pin Number Pin Name K18FLASH_A032A0K17FLASH_A128A1J18FLASH_A227A2J16FLASH_A326A3G18FLASH_A425A4G16FLASH_A524A5H16FLASH_A623A6H15FLASH_A722A7H14FLASH_A820A8H13FLASH_A919A9F18FLASH_A1018A10F17FLASH_A1117A11K13FLASH_A1213A12K12FLASH_A1312A13E18FLASH_A1411A14E16FLASH_A1510A15G13FLASH_A168A16SP601 Hardware User Guide Note:Memory U10 pin 56 address A24 is not connected on the 16 MB device. It is made availablefor larger density devices.ReferencesSee the Numonyx Embedded Flash Memory Data Sheet for more information. [Ref 13]In addition, see the Spartan-6 FPGA Configuration User Guide for more information. [Ref 2]H12FLASH_A177A17D18FLASH_A186A18D17FLASH_A195A19G14FLASH_A204A20F14FLASH_A213A21C18FLASH_A221A22C17FLASH_A2330A23F16FLASH_A2456A24R13FPGA_D0_DIN_MISO_MISO133DQ0T14FPGA_D1_MISO235DQ1V14FPGA_D2_MISO338DQ2U5FLASH_D340DQ3V5FLASH_D444DQ4R3FLASH_D546DQ5T3FLASH_D649DQ6R5FLASH_D751DQ7M16FLASH_WE_B 55WE_B L18FLASH_OE_B 54OE_B L17FLASH_CE_B14CE0B3FMC_PWR_GOOD_FLASH_RST_B16RP_BTable 1-7:BPI Memory Connections (Cont’d)FPGA U1 PinSchematic Net NameBPI Memory U10Pin NumberPin Name5. 10/100/1000 T ri-Speed Ethernet PHYThe SP601 uses the onboard Marvell Alaska PHY device (88E1111) for Ethernetcommunications at 10, 100, or 1000 Mb/s. The board supports a GMII/MII interface fromthe FPGA to the PHY. The PHY connection to a user-provided Ethernet cable is through aHalo HFJ11-1G01E RJ-45 connector with built-in magnetics.On power-up, or on reset, the PHY is configured to operate in GMII mode with PHYaddress 0b00111 using the settings shown in Table1-8. These settings can be overwrittenvia software commands passed over the MDIO interface.Table 1-8:PHY Configuration PinsPin Connection onBoardBit[2]Definition and ValueBit[1]Definition and ValueBit[0]Definition and ValueCFG0V CC 2.5V PHYADR[2] = 1PHYADR[1] = 1PHYADR[0] = 1 CFG1Ground ENA_PAUSE = 0PHYADR[4] = 0PHYADR[3] = 0 CFG2V CC 2.5V ANEG[3] = 1ANEG[2] = 1ANEG[1] = 1 CFG3V CC 2.5V ANEG[0] = 1ENA_XC = 1DIS_125 = 1 CFG4V CC 2.5V HWCFG_MD[2] = 1HWCFG_MD[1] = 1HWCFG_MD[0] = 1 CFG5V CC 2.5V DIS_FC = 1DIS_SLEEP = 1HWCFG_MD[3] = 1 CFG6PHY_LED_RX SEL_BDT = 0INT_POL = 175/50Ω = 0 Table 1-9:Ethernet PHY ConnectionsFPGA U1 Pin Schematic Net NameU3 M88E111Pin Number Pin NameP16PHY_MDIO33MDIO N14PHY_MDC35MDC J13PHY_INT32INT_B L13PHY_RESET36RESET_B M13PHY_CRS115CRS L14PHY_COL114COL L16PHY_RXCLK7RXCLK P17PHY_RXER8RXER N18PHY_RXCTL_RXDV4RXDV M14PHY_RXD03RXD0 U18PHY_RXD1128RXD1 U17PHY_RXD2126RXD2 T18PHY_RXD3125RXD3 T17PHY_RXD4124RXD4 N16PHY_RXD5123RXD5SP601 Hardware User GuideReferencesSee the Marvell Alaska Gigabit Ethernet Transceivers product page for more information.[Ref 16]Also, see the LogiCORE™ IP Tri-Mode Ethernet MAC User Guide . [Ref 5]N15PHY_RXD6121RXD6P18PHY_RXD7120RXD7A9 PHY_TXC_G TPCLK 14G TXCLKB9 PHY_TXCLK 10TXCLK A8 PHY_TXER 13TXER B8 PHY_TXCTL_TXEN 16TXEN F8 PHY_TXD018TXD0G 8 PHY_TXD119TXD1A6 PHY_TXD220TXD2B6 PHY_TXD324TXD3E6 PHY_TXD425TXD4F7 PHY_TXD526TXD5A5 PHY_TXD628TXD6C5 PHY_TXD729TXD7Table 1-9:Ethernet PHY Connections (Cont’d)FPGA U1 PinSchematic Net NameU3 M88E111Pin NumberPin Name6. USB-to-UART BridgeThe SP601 contains a Silicon Labs CP2103GM USB-to-UART bridge device (U4) which allows connection to a host computer with a USB cable. The USB cable is supplied in this evaluation kit (Type A end to host computer, Type Mini-B end to SP601 connector J9). Table 1-10 details the SP601 J9 pinout.Xilinx UART IP is expected to be implemented in the FPGA fabric. The FPGA supports the USB-to-UART bridge using four signal pins, transmit (TX), receive (RX), Request to Send (RTS), and Clear to Send (CTS).Silicon Labs provides royalty-free Virtual COM Port (VCP) drivers which permit the CP2103GM USB-to-UART bridge to appear as a COM port to host computercommunications application software (for example, HyperTerm or TeraTerm). The VCP device driver must be installed on the host PC prior to establishing communications with the SP601. Refer to the SP601 Getting Started Guide for driver installation instructions.ReferencesRefer to the Silicon Labs website for technical information on the CP2103GM and the VCP drivers.In addition, see some of the Xilinx UART IP specifications at:•/support/documentation/ip_documentation/xps_uartlite.pdf •/support/documentation/ip_documentation/xps_uart16550.pdfTable 1-10:USB Type B Pin Assignments and Signal DefinitionsUSB ConnectorPinSignal NameDescription1VBUS +5V from host system (not used)2USB_DATA_N Bidirectional differential serial data (N-side)3USB_DATA_P Bidirectional differential serial data (P-side)4GROUNDSignal groundTable 1-11:CP2103GM ConnectionsFPGA U1 PinUART Functionin FPGA Schematic Net Name U4 CP2103GMPinUART Function in CP2103GM U10RTS, output USB_1_CTS 22CTS, input T5CTS, input USB_1_RTS 23RTS, output L12TX, data out USB_1_RX 24RXD, data in K14RX, data inUSB_1_TX25TXD, data out。
康佳彩电总线进入方法详解1．康佳彩电18大系列K/N系列、SK系列、S系列、SE系列、SA系列、A系列、C系列、E系列、F系列、ST系列、TA8880CN机芯（画中画系列）、倍频机芯、W机芯（背投系列）、T系列(数字高清)、I系列(数字高清)、M、FM系列(数字高清)、FG、FT系列(数字高清)、MV系列(数字高清)。
2.1 K/N系列2.1.1彩电配置一览表主要IC：超级芯片TDA9380或TDA93832.1.2总线调整方法机型：TDA9380掩膜后的型号为CKP1402SA，代表机型有：P2162K、T2168K、T2168N、P2179K、T2176N、T2176K等；TDA9383掩膜后的型号为CKP1403SA，代表机型有：T3468K、P3460K、P2960K、P2961K、P2962K、P2962K1、P2998K、T2975K、T2968K、T2976K、T2968N、P2562K、P2579K、T2568K、T2568N按MENU(菜单)键调出菜单显示(注：菜单显示时间为10s)，在菜单未消失前连续按回看键5次便可进入工厂调整菜单。
按MENU键可依次选择菜单1到菜单4。
选中需调整的菜单后，可用节目+/-键选择需调整的项目(选中后变为红色)；用音量控制键调节选中项目的参数值，直至符合要求为止。
当所有调试完成后，再按一次回看键即可退出总线调整模式，回到正常收看状态。
2.1.3总线故障故障现象：接收PAL-I制信号时，伴音音轻且有杂音。
检修提示：进入维修状态，在维修菜单5内设有伴音制式设定项目，其中SOUND FILTER 即是伴音滤波器选择设定项目，数据为"00"时，选择内部SIF电路处理全制式伴音信号；"01"时，选择外部电路处理6.5MHz伴音信号；"02"时，选择外部电路处理6.0MHz伴音信号；"03"时，选择外部电路处理全制式伴音信号。
第1章电源电路模块第1节变压器电源电路（MCU+RS485）1.1 电路名称变压器电源电路（MCU+RS485）。
1.2 电路概述变压器输出电源电路，是将市电利用变压器的降压以及后续的整流稳压输出低压直流电的功能电源电路。
本文针对公司静止式电能表、预付费电能表等产品中，普遍使用的输出提供MCU计量和RS485通信的两路负载需要的变压器电源电路作介绍。
火线Line，缩写L零线Neutral，缩写N地线Earth line，缩写E保护接地线Protect earthing line，缩写PE1.3 电路图及原理分析1.4 MYN23-751K1.5 压敏电阻：主要用途：防雷，过压保护。
如电力变压器在进户端放入氧化锌避雷器可以有效防雷，电子设备在电网电源输入端放入压敏电阻，一但电网电压升高压敏电阻会不可恢复击穿短路同时保险丝也将断开，从而有效的放止过电压进入线路板。
在空调线线路板应用压敏电阻最为多。
图1-1230V变压器单相提供MCU+RS485电源电路1.5.1 变压器电源电路（MCU+RS485）一般原理如图1-1所示，变压器电源电路基本功能是将电网中的交流电，通过变压器的电磁转换从副极线圈输出低压交流电。
如图（编号6和7）的副边低压交流电经过整流桥堆的整流操作输出一个脉动电压，这个脉动电压通过（如C1类）的电解电容器的滤波，在DV1稳压二极管的钳位作用下转换成了可以用于LDO等低压稳压器件操作的直流电。
另一组（编号9、10）副边低压交流电通过二极管的半波整流操作输出一个脉动电压，之后通过C3的滤波和DV2的稳压二极管钳位作用输出一个可用于低压稳压器件操作的直流电。
然而，如C1电解电容器在整个电能表的供电模块中还扮演着掉电瞬间数据存储提供能量的重要角色，所以选取的时候需谨慎，详细请看1.3.2.5。
图1-1中红色虚框中的DV3稳压二极管是在客户需要380V过压的时候加上（或将DV1换成额定功率>2W的稳压二极管），没有过压要求的可以去掉，详见1.3.2.4。
PC-PPI编程电缆使用手册PC/PPI+编程电缆为RS232到PPI接口（RS485）的转换电缆，适用于西门子S7-200系列PLC，支持PPI协议和自由口通信协议，并可使用MODEM（调制解调器）通过电话线远程通信，光电隔离和内置的防静电、浪涌等瞬态过压保护电路很好地解决了容易烧通信口的问题。
主要技术参数：★隔离电压:1000V直流或3500V脉冲★具有瞬变电压抑制功能,能承受功率高达400W的瞬态过压，能防雷电和抗静电★波特率：0～28.8kbps自适应★最大通信距离：2公里（波特率为9600bps时）★带有电源指示灯和数据收、发指示灯★工作温度:-20～75℃★外形尺寸：103×50×26，电缆总长度3米产品的结构：PC-RS232插头和PPI-RS485插头的信号定义如下：PPI-RS485插头PC-RS232插头针号信号说明针号信号说明2 24V电源负（RS485逻辑地）2 接收数据RD（从PC/PPI输出）3 RS485信号B（RxD/TxD+）3 发送数据SD（输入到PC/PPI）7 24V电源正4 数据终端就绪DTR8 RS485信号A（RxD/TxD-）5 地（RS232逻辑地）9 协议选择7 请求发送RTS产品的使用：1、PLC与电脑连接作PPI或自由口通信、编程：只需将PC/PPI+电缆的RS485插头插入S7-200PLC的编程口，RS232插头插入电脑的RS232口，并在编程软件上选择对应的COM口号，将10bit、11bit选择开关拨到11bit位置及可。
本PC/PPI+电缆的波特率为0～28.8kbps自动适应，无需设置。
2、PLC与电脑的长距离通信：当长距离通信时PC/PPI+需另外接电源，并且在RS485插头的3、8之间并接120欧终端电阻以消除信号反射，如下图所示：2、PLC通过电话线与电脑的远程通信：PC/PPI+的RS232端与MODEM连接时需自制一个DCE/DTE交叉转接头，并根据是10位还是11位MODEM将电缆上的开关拨到对应位置。
