FPGA可编程逻辑器件芯片XC7K325T-2FFG900I中文规格书

Chapter 38:Debugging To see how much movement the PQTR and NQTR taps exhibit over environmental changes, monitor:VT_TRACK_PQTR_NIBBLE*VT_TRACK_NQTR_NIBBLE*VT_TRACK_PQTR_MAX_NIBBLE*VT_TRACK_NQTR_MAX_NIBBLE*VT_TRACK_PQTR_MIN_NIBBLE*VT_TRACK_NQTR_MIN_NIBBLE*Calibration TimesCalibration time depends on a number of factors, such as:•General Interconnect Clock Frequency•Number of DDR Ranks•Memory Width•Board Trace LengthsTable38-55 gives an example of calibration times for a DDR memory interface.Table 38-43:DDR Calibration TimesMemoryInterface Component Type Width Memory InterfaceSpeed (MT/s)Calibration Time (s)DDR3x8 components72-bit2,1330.831,866 1.101,6000.751,333 1.041,066 1.568000.84 Dual-Rank SO-DIMM x872-bit1,6000.851,333 1.15 Dual-Rank RDIMM x872-bit1,6000.941,333 1.28Chapter 25:Designing with the CoreSharing of Input Clock Source (sys_clk_p)If the same GCIO pin must be used for two IP cores, generate the two IP cores with the same frequency value selected for option Reference Input Clock Period (ps) and System Clock Configuration option as No Buffer. Perform the following changes in the wrapper file in which both IPs are instantiated:1.QDR-IV SRAM generates a single-ended input for system clock pins, such assys_clk_i. Connect the differential buffer output to the single-ended system clock inputs (sys_clk_i) of both the IP cores.2.System clock pins must be allocated within the same I/O column of the memoryinterface pins allocated. Add the pin LOC constraints for system clock pins and clock constraints in your top-level XDC.3.You must add a "BACKBONE" constraint on the net that is driving the MMCM or on theMMCM input if GCIO pin and MMCM are not allocated in the same bank. Apart from this, BUFG/BUFGCE/BUFGCTRL/BUFGCE_DIV must be instantiated between GCIO and MMCM to use the "BACKBONE" route.Note:°The UltraScale architecture includes an independent XIPHY power supply and TXPLL for each XIPHY. This results in clean, low jitter clocks for the memory system.°Skew spanning across multiple BUFGs is not a concern because single point of contact exists between BUFG → TXPLL and the same BUFG → System Clock Logic.°System input clock cannot span I/O columns because the longer the clock lines span, the more jitter is picked up.TXPLL UsageThere are two TXPLLs per bank. If a bank is shared by two memory interfaces, both TXPLLs in that bank are used. One PLL per bank is used if a bank is used by a single memory interface. You can use a second PLL for other usage. To use a second PLL, you can perform the following steps:1.Generate the design for the System Clock Configuration option as No Buffer.2.QDR-IV SRAM generates a single-ended input for system clock pins, such assys_clk_i. Connect the differential buffer output to the single-ended system clock inputs (sys_clk_i) and also to the input of PLL (PLL instance that you have in your design).3.You can use the PLL output clocks.Chapter 38:Debugging The following Tcl command can also be used when the Hardware Manager is open to get an output of the window values:report_hw_mig [get_hw_migs]Table 38-48:Signals of Interest for Read and Write Margin AnalysisSignal Usage Signal Description MARGIN_CONTROL Per Interface ReservedMARGIN_STATUS Per Interface ReservedRDLVL_MARGIN_PQTR_LEFT_RANK*_BYTE*_BIT*Per Bit Number of taps from center of window toleft edge.RDLVL_MARGIN_NQTR_LEFT_RANK*_BYTE*_BIT*Per Bit Number of taps from center of window toleft edge.RDLVL_MARGIN_PQTR_RIGHT_RANK*_BYTE*_BIT*Per Bit Number of taps from center of window toright edge.RDLVL_MARGIN_NQTR_RIGHT_RANK*_BYTE*_BIT*Per Bit Number of taps from center of window toright edge.WRITE_DQS_DQ_MARGIN_LEFT_RANK*_BYTE*_BIT*Per Bit Number of taps from center of window toleft edge.WRITE_DQS_DQ_MARGIN_RIGHT_RANK*_BYTE*_BIT*Per Bit Number of taps from center of window toright edge.。

Chapter1 ZC706 Evaluation Board FeaturesOverviewThe ZC706 evaluation board for the XC7Z045 SoC provides a hardware environment fordeveloping and evaluating designs targeting the Zynq®-7000 XC7Z045-2FFG900C SoC. The ZC706 evaluation board provides features common to many embedded processing systems, including DDR3 SODIMM and component memory, a four-lane PCI Express® interface, an Ethernet PHY, general purpose I/O, and two UART interfaces. Other features can besupported using VITA-57 FPGA mezzanine cards (FMC) attached to the low pin count (LPC) FMC and high pin count (HPC) FMC connectors.ZC706 Evaluation Board FeaturesThe ZC706 evaluation board features are listed in here. Detailed information for eachfeature is provided in Feature Descriptions starting on page15.•Zynq-7000 XC7Z045-2FFG900C SoC•1GB DDR3 memory SODIMM on the programmable logic (PL) side•1GB DDR3 component memory (four [256Mb x 8] devices) on the processing system (PS) side•Two 128Mb Quad-SPI (QSPI) flash memory (Dual Quad-SPI)•USB 2.0 ULPI (UTMI+ low pin interface) transceiver with micro-B USB connector•Secure Digital (SD) connector•USB JTAG interface via Digilent module with micro-B USB connector•Clock sources:°Fixed 200MHz LVDS oscillator (differential)°I2C programmable LVDS oscillator (differential)°Fixed 33.33MHz LVCMOS oscillator (single-ended)°Subminiature version A (SMA) connectors (differential)°SMA connectors for GTX transceiver clocking (differential)Feature DescriptionsDetailed information for each feature shown in Figure 1-3 and listed in Table 1-1 is provided in this section.Zynq-7000 XC7Z045 SoC[Figure 1-3, callout 1]The ZC706 evaluation board is populated with the Zynq-7000 XC7Z045-2FFG900C SoC.The XC7Z045 SoC consists of an integrated processing system (PS) and programmable logic (PL), on a single die. The high-level block diagram is shown in Figure 1-4.The PS integrates two ARM® Cortex™-A9 MPCore™ application processors, AMBA® interconnect, internal memories, external memory interfaces, and peripherals including USB, Ethernet, SPI, SD/SDIO, I 2C , CAN, UART, and GPIO. The PS runs independently of the PL and boots at power-up or reset.A system level block diagram is shown in Figure 1-5.Figure 1-4:High-Level Block DiagramM10PL_DDR3_TEMP_EVENT SSTL15198EVENT_B F7PL_DDR3_WE_B SSTL15113WE_B E7PL_DDR3_CAS_B SSTL15115CAS_B H11PL_DDR3_RAS_B SSTL15110RAS_B D10PL_DDR3_CKE0SSTL1573CKE0C7PL_DDR3_CKE1SSTL1574CKE1F10PL_DDR3_CLK0_N DIFF_SSTL15103CK0_N G10PL_DDR3_CLK0_P DIFF_SSTL15101CK0_P D8PL_DDR3_CLK1_N DIFF_SSTL15104CK1_N D9PL_DDR3_CLK1_PDIFF_SSTL15102CK1_PTable 1-4:DDR3 SODIMM Socket J1 Connections to the XC7Z045 SoC (Cont’d)XC7Z045 (U1)PinNet NameI/O StandardDDR3 SODIMM Memory J1Pin NumberPin NameThe connections between the USB Micro-B connector at J2 and the PHY at U12 are listed in Table1-8.Table 1-8:USB Connector Pin Assignments and Signal Definitions Between J2 and U12USB ConnectorJ1Net Name Description USB3320 (U12)Pin Pin Name1VBUS USB_VBUS_SEL+5V from host system222D_N USB_D_N Bidirectional differential serial data (N-side)193D_P USB_D_P Bidirectional differential serial data (P-side)185GND GND Signal ground33。

Chapter 3:Core ArchitectureMemory SettingsThis section captures the settings of memory components and DIMMs.DDR3 Register ModuleDDR3 register module settings are captured in Table 3-19. The register contents are programmed to default value of 0s, unless otherwise specified in the table. DDR4 Register ModuleDDR4 register module settings are captured in Table 3-20. The register contents are programmed to default value of 0s, unless otherwise specified in the table. Table 3-19:DDR3 Register Module Settings RegisterField Possible Values and Description RC3DBA[1:0], DA[4:3]Value based on DRAM loads on the card.RC4DBA[1:0], DA[4:3]Value based on DRAM loads on the card.RC5DBA[1:0], DA[4:3]Value based on DRAM loads on the card.RC10DBA[0], DA[4:3]Value based on the targeted speed.RC11DA[4:3]Value based on the targeted voltage.Table 3-20:DDR4 Register Module Settings RegisterField Possible Values and Description RC03DA[3:0]Value based on DRAM loads on the card.RC04DA[3:0]Value based on DRAM loads on the card.RC05DA[3:0]Value based on DRAM loads on the card.RC08DA[1:0]For non-3DS configurations:01 = Number of physical ranks per slot is 4 (LRDIMM Quad rank)11 = Number of physical ranks per slot is 2 or 1For 3DS configurations:11 = 1 height10 = 2 height01 = 4 heightDA[3]0 = If address pins are 181 = If address pins are 17RC0A DA[2:0]Value based on the targeted speed.RC0B DA[3]1 = Input receiver Vref source is External VrefCA input。

IntroductionArtix®-7 FPGAs are available in -3, -2, -1, -1LI, and -2L speed grades, with -3 having the highest performance. The Artix-7FPGAs predominantly operate at a 1.0V core voltage. The -1LI and -2L devices are screened for lower maximum static power and can operate at lower core voltages for lower dynamic power than the -1 and -2 devices, respectively. The -1LI devices operate only atV CCINT =V CCBRAM =0.95V and have the same speed specifications as the -1 speed grade. The -2L devices can operate at either of two V CCINT voltages, 0.9V and 1.0V and are screened for lower maximum static power. Whenoperated at V CCINT =1.0V, the speed specification of a -2L device is the same as the -2 speed grade. When operated at V CCINT =0.9V, the -2L static and dynamic power is reduced.Artix-7 FPGA DC and AC characteristics are specified in commercial, extended, industrial, expanded (-1Q), and military (-1M) temperature ranges. Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1Mspeed grade military device are the same as for a -1C speed grade commercial device). However, only selected speed grades and/or devices are available in each temperature range. For example, -1M is only available in thedefense-grade Artix-7Q family and -1Q is only available in XA Artix-7FPGAs.All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications.Available device and package combinations can be found in :•7Series FPGAs Overview (DS180)•Defense-Grade 7Series FPGAs Overview (DS185)•XA Artix-7 FPGAs Overview (DS197)DC CharacteristicsTable 1:Absolute Maximum Ratings (1)SymbolDescription Min Max UnitsFPGA Logic V CCINT Internal supply voltage –0.5 1.1V V CCAUX Auxiliary supply voltage–0.5 2.0V V CCBRAM Supply voltage for the block RAM memories –0.5 1.1V V CCO Output drivers supply voltage for HR I/O banks –0.5 3.6V V REF Input reference voltage –0.5 2.0V V IN (2)(3)(4)I/O input voltage–0.4V CCO +0.55V I/O input voltage (when V CCO =3.3V) for V REF and differential I/O standards except TMDS_33(5)–0.4 2.625V V CCBATTKey memory battery backup supply–0.52.0VGTP Transceiver V MGTAVCC Analog supply voltage for the GTP transmitter and receiver circuits–0.5 1.1V V MGTAVTT Analog supply voltage for the GTP transmitter and receiver termination circuits –0.5 1.32V V MGTREFCLK Reference clock absolute input voltage–0.5 1.32V V INReceiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage–0.51.26V找FPGA ，上赛灵思半导体（深圳）有限公司I DCIN-FLOAT DC input current for receiver input pins DC coupled RX termination =floating –14mA I DCIN-MGTAVTT DC input current for receiver input pins DC coupled RX termination =V MGTAVTT –12mA I DCIN-GND DC input current for receiver input pins DC coupled RX termination =GND – 6.5mA I DCOUT-FLOAT DC output current for transmitter pins DC coupled RX termination =floating –14mA I DCOUT-MGTAVTTDC output current for transmitter pins DC coupled RX termination =V MGTAVTT –12mA XADC V CCADC XADC supply relative to GNDADC –0.5 2.0V V REFPXADC reference input relative to GNDADC–0.52.0VTemperature T STG Storage temperature (ambient)–65150°C T SOL Maximum soldering temperature for Pb/Sn component bodies (6)–+220°C Maximum soldering temperature for Pb-free component bodies (6)–+260°C T j Maximum junction temperature (6)–+125°CNotes:1.Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.2.The lower absolute voltage specification always applies.3.For I/O operation, refer to 7Series FPGAs SelectIO Resources User Guide (UG471).4.The maximum limit applies to DC signals. For maximum undershoot and overshoot AC specifications, see Table 4.5.See Table 9 for TMDS_33 specifications.6.For soldering guidelines and thermal considerations, see 7Series FPGA Packaging and Pinout Specification (UG475).Table 2:Recommended Operating Conditions (1)(2)Symbol Description Min Typ Max UnitsFPGA LogicV CCINT (3)For -3, -2, -2LE (1.0V), -1, -1Q, -1M devices: internal supply voltage0.95 1.00 1.05V For -1LI (0.95V) devices: internal supply voltage 0.920.950.98V For -2LE (0.9V) devices: internal supply voltage 0.870.900.93V V CCAUX Auxiliary supply voltage1.71 1.80 1.89V V CCBRAM (3)For -3, -2, -2LE (1.0V), -2LE (0.9V), -1, -1Q, -1M devices: block RAM supply voltage0.95 1.00 1.05V For -1LI (0.95V) devices: block RAM supply voltage 0.920.950.98V V CCO (4)(5)Supply voltage for HR I/O banks 1.14– 3.465V V IN (6)I/O input voltage–0.20–V CCO +0.20V I/O input voltage (when V CCO =3.3V) for V REF and differential I/O standards except TMDS_33(7)–0.20– 2.625V I IN (8)Maximum current through any pin in a powered or unpowered bank when forward biasing the clamp diode.––10mA V CCBATT (9)Battery voltage1.0–1.89VGTP TransceiverV MGTAVCC (10)Analog supply voltage for the GTP transmitter and receiver circuits0.97 1.0 1.03V V MGTAVTT (10)Analog supply voltage for the GTP transmitter and receiver termination circuits1.171.21.23VXADC V CCADCXADC supply relative to GNDADC1.711.801.89VTable 1:Absolute Maximum Ratings (1) (Cont’d)Symbol DescriptionMin Max UnitsTable 3:DC Characteristics Over Recommended Operating ConditionsSymbolDescriptionMin Typ (1)Max Units V DRINT Data retention V CCINT voltage (below which configuration data might be lost)0.75––V V DRI Data retention V CCAUX voltage (below which configuration data might be lost) 1.5––V I REF V REF leakage current per pin––15µA I L Input or output leakage current per pin (sample-tested)––15µA C IN (2)Die input capacitance at the pad––8pF I RPU Pad pull-up (when selected) @ V IN =0V, V CCO =3.3V 90–330µA Pad pull-up (when selected) @ V IN =0V, V CCO =2.5V68–250µA Pad pull-up (when selected) @ V IN =0V, V CCO =1.8V 34–220µA Pad pull-up (when selected) @ V IN =0V, V CCO =1.5V 23–150µA Pad pull-up (when selected) @ V IN =0V, V CCO =1.2V12–120µA I RPD Pad pull-down (when selected) @ V IN =3.3V68–330µA I CCADC Analog supply current, analog circuits in powered up state ––25mA I BATT (3)Battery supply current––150nA R IN_TERM (4)Thevenin equivalent resistance of programmable input termination to V CCO /2 (UNTUNED_SPLIT_40)284055ΩThevenin equivalent resistance of programmable input termination to V CCO /2 (UNTUNED_SPLIT_50)355065ΩThevenin equivalent resistance of programmable input termination to V CCO /2 (UNTUNED_SPLIT_60)446083ΩDIFF_SSTL18_II0.3000.9001.4250.100–(V CCO /2)–0.600(V CCO /2)+0.60013.4–13.4Notes:1.V ICM is the input common mode voltage.2.V ID is the input differential voltage (Q –Q).3.V OL is the single-ended low-output voltage.4.V OH is the single-ended high-output voltage.Table 10:Complementary Differential SelectIO DC Input and Output Levels (Cont’d)I/O Standard V ICM (1)V ID (2)V OL (3)V OH (4)I OL I OH V, Min V,Typ V, Max V,Min V, MaxV, Max V, Min mA, Max mA, MinAC Switching CharacteristicsAll values represented in this data sheet are based on the speed specifications from the ISE® Design Suite and Vivado®Design Suite as outlined in Table12.Table 12:Artix-7 FPGA Speed Specification Version By DeviceVersion In:Typical V CCINTDeviceISE 14.7Vivado 2018.2(Table2)N/A 1.22 1.0V XC7A12T, XC7A15T, XC7A25T, XC7A35T, XC7A50T, XC7A75TN/A 1.220.95V XC7A12T, XC7A15T, XC7A25T, XC7A35T, XC7A50T, XC7A75T, XC7A100T,XC7A200TN/A 1.140.9V XC7A12T, XC7A15T, XC7A25T, XC7A35T, XC7A50T, XC7A75T1.10 1.22 1.0V XC7A100T, XC7A200T1.07 1.140.9V XC7A100T, XC7A200TN/A 1.15 1.0V XA7A12T, XA7A15T, XA725T, XA7A35T, XA7A50T, XA7A75T1.07 1.15 1.0V XA7A100T1.06 1.11 1.0V XQ7A100T, XQ7A200TN/A 1.11 1.0V XQ7A50T。