CS44800中文资料

5.2.1 接口指标 ....................................................................................................... 13 5.2.2 容量指标 ....................................................................................................... 14 5.2.3 可靠性指标.................................................................................................... 14 5.2.4 射频指标 ....................................................................................................... 14 5.2.5 BTS 时钟技术参数 ........................................................................................ 16
5 系统技术指标 ................................................................................................................... 12 5.1 设备运行环境指标要求 ........................................................................................... 12 5.1.1 外观图 ........................................................................................................... 12 5.1.2 尺寸............................................................................................................... 12 5.1.3 整机重量 ....................................................................................................... 12 5.1.4 电源系统范围 ................................................................................................ 12 5.1.5 功耗指标 ....................................................................................................... 12 5.1.6 设备散热量.................................................................................................... 13

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.©1999Document No. M14466EJ5V0DS00 (5th edition)Date Published July 2001 NS CP (K)Printed in JapanThe mark 5 shows major revised points.DescriptionThe µPD448012-X is a high speed, low power, 8,388,608 bits (524,288 words by 16 bits) CMOS static RAM.The µPD448012-X has two chip enable pins (/CE1, CE2) to extend the capacity.The µPD448012-X is packed in 48-pin PLASTIC TSOP (I) (Normal bent).Features• 524,288 words by 16 bits organization• Fast access time: 55, 70, 85, 100, 120 ns (MAX.)• Byte data control: /LB (I/O1 - I/O8), /UB (I/O9 - I/O16)• Low voltage operation(B version: V CC = 2.7 to 3.6 V, C version: V CC = 2.2 to 3.6 V)• Low V CC data retention : 1.0 V (MIN.)• Operating ambient temperature: T A = –25 to +85°C • Output Enable input for easy application • Two Chip Enable inputs: /CE1, CE2Part numberAccess time Operating supply Operating ambientSupply current ns (MAX.)voltage temperatureAt operating At standbyAt data retentionV°C mA (MAX.)µA (MAX.)µA (MAX.)µPD448012-BxxX 55, 70, 85, 100 2.7 to 3.6−25 to +8545Note156µPD448012-CxxX70, 85, 100, 1202.2 to3.645Note Cycle time ≥ 70 ns, µPD448012-B55X : 50 mAData Sheet M14466EJ5V0DS2Ordering InformationPart numberPackageAccess time Operating Operating Remarkns (MAX.)supply voltagetemperatureV°C µPD448012GY-B55X-MJH 48-pin PLASTIC TSOP (I)55 2.7 to 3.6−25 to +85B version µPD448012GY-B70X-MJH (12x18) (Normal bent)70µPD448012GY-B85X-MJH 85µPD448012GY-B10X-MJH 100µPD448012GY-C70X-MJH 70 2.2 to 3.6 C versionµPD448012GY-C85X-MJH 85µPD448012GY-C10X-MJH 100µPD448012GY-C12X-MJH120Data Sheet M14466EJ5V0DS3Pin Configuration (Marking Side)/xxx indicates active low signal.48-pin PLASTIC TSOP (I) (12x18) (Normal bent)[ µPD448012GY-BxxX-MJH ][ µPD448012GY-CxxX-MJH ]A15A14A13A12A11A10A9A8NC NC /WE CE2NC /UB /LB A18A17A7A6A5A4A3A2A1A16NC GND I/O16I/O8I/O15I/O7I/O14I/O6I/O13I/O5V CC I/O12I/O4I/O11I/O3I/O10I/O2I/O9I/O1/OE GND /CE1A0A0 - A18:Address inputs I/O1 - I/O16:Data inputs / outputs/CE1, CE2:Chip Enable 1, 2/WE :Write Enable /OE :Output Enable /LB, /UB :Byte data select V CC :Power supply GND :Ground NC:No ConnectionRemarkRefer to Package Drawing for the 1-pin index mark.Data Sheet M14466EJ5V0DS4Block DiagramI/O1 - I/O8V Truth Table/CE1CE2/OE/WE/LB/UBModeI/OSupply currentI/O1 - I/O8I/O9 - I/O16H ×××××Not selectedHigh impedanceHigh impedanceI SB×L ××××LHH H ××Output disable High impedanceHigh impedanceI CCALHL L Word read D OUT D OUTL H Lower byte read D OUTHigh impedanceHL Upper byte read High impedanceD OUT ×LL L Word write D IN D INL H Lower byte write D INHigh impedanceHL Upper byte write High impedance D IN××××HHNot selectedHigh impedanceHigh impedanceI SB Remark × : V IH or V ILData Sheet M14466EJ5V0DS5Electrical SpecificationsAbsolute Maximum RatingsParameterSymbol ConditionRatingUnit Supply voltage V CC –0.5Noteto +4.0V Input / Output voltageV T –0.5Noteto V CC + 0.4 (4.0 V MAX.)V Operating ambient temperature T A –25 to +85°C Storage temperatureT stg–55 to +125°CNote –3.0 V (MIN.) (Pulse width : 30 ns)Caution Exposing the device to stress above those listed in Absolute Maximum Rating could causepermanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.Recommended Operating ConditionsParameterSymbolConditionµPD448012-BxxXµPD448012-CxxXUnitMIN.MAX.MIN.MAX.Supply voltage V CC 2.7 3.6 2.2 3.6V High level input voltageV IH2.7 V ≤ V CC ≤3.6 V 2.4V CC + 0.42.4V CC + 0.4V2.2 V ≤ V CC < 2.7 V––2.0V CC + 0.3Low level input voltage V IL –0.3Note+0.5–0.3Note+0.3V Operating ambient temperatureT A–25+85–25+85°C Note –1.5 V (MIN.) (Pulse width: 30 ns)Capacitance (T A = 25°C, f = 1 MHz)ParameterSymbol Test conditionMIN.TYP.MAX.Unit Input capacitance C IN V IN = 0 V 8pF Input / Output capacitanceC I/OV I/O = 0 V10pFRemarks 1.V IN : Input voltage, V I/O : Input / Output voltage2.These parameters are not 100% tested.Data Sheet M14466EJ5V0DS6DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (1/2)ParameterSymbolTest conditionV CC ≥ 2.7 VUnitµPD448012-BxxXMIN.TYP.MAX.Input leakage current I LI V IN = 0 V to V CC–1.0+1.0µA I/O leakage currentI LOV I/O = 0 V to V CC , /CE1 = V IH or –1.0+1.0µACE2 = V IL or /WE = V IL or /OE = V IHOperating supply current I CCA1/CE1 = V IL , CE2 = V IH ,Cycle time = 55 ns –50mAMinimum cycle time,Cycle time ≥ 70 ns–45I I/O = 0 mAI CCA2/CE1 = V IL , CE2 = V IH , I I/O = 0 mA,–4Cycle time = ∞I CCA3/CE1 ≤ 0.2 V, CE2 ≥ V CC – 0.2 V,–6Cycle time = 1 µs, I I/O = 0 mA,V IL ≤ 0.2 V, V IH ≥ V CC – 0.2 VStandby supply current I SB /CE1 = V IH or CE2 = V IL or /LB = /UB = V IH –0.6mAI SB1/CE1 ≥ V CC − 0.2 V, CE2 ≥ V CC − 0.2 V 1.015µAI SB2CE2 ≤ 0.2 V1.015I SB3/LB = /UB ≥ V CC − 0.2 V, 1.015/CE1 ≤ 0.2 V, CE2 ≥ V CC − 0.2 VHigh level output voltage V OH I OH = –0.5 mA 2.4V Low level output voltageV OLI OL = 1.0 mA0.4VRemarks 1.V IN : Input voltage, V I/O : Input / Output voltage2.These DC characteristics are in common regardless of product classification.Data Sheet M14466EJ5V0DS7DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (2/2)ParameterSymbolTest conditionV CC ≥ 2.2 VUnitµPD448012-CxxXMIN.TYP.MAX.Input leakage current I LI V IN = 0 V to V CC–1.0+1.0µA I/O leakage currentI LOV I/O = 0 V to V CC , /CE1 = V IH or –1.0+1.0µACE2 = V IL or /WE = V IL or /OE = V IHOperating supply currentI CCA1/CE1 = V IL , CE2 = V IH , Minimum cycle time,–45mAI I/O = 0 mAV CC ≤ 2.7 V–30I CCA2/CE1 = V IL , CE2 = V IH , I I/O = 0 mA,–4Cycle time = ∞V CC ≤ 2.7 V–2I CCA3/CE1 ≤ 0.2 V, CE2 ≥ V CC – 0.2 V,–6Cycle time = 1 µs, I I/O = 0 mA, V IL ≤ 0.2 V,V IH ≥ V CC – 0.2 VV CC ≤ 2.7 V–5Standby supply current I SB /CE1 = V IH or CE2 = V IL or –0.6mA/LB = /UB = V IHV CC ≤ 2.7 V–0.6I SB1/CE1 ≥ V CC − 0.2 V, 1.015µACE2 ≥ V CC − 0.2 VV CC ≤ 2.7 V0.913I SB2CE2 ≤ 0.2 V1.015V CC ≤ 2.7 V0.913I SB3/LB = /UB ≥ V CC − 0.2 V, /CE1 ≤ 0.2 V, 1.015CE2 ≥ V CC − 0.2 VV CC ≤ 2.7 V0.913High level output voltage V OH I OH = –0.5 mA2.4V V CC ≤ 2.7 V1.8Low level output voltage V OL I OL = 1.0 mA0.4VRemarks 1.V IN : Input voltage, V I/O : Input / Output voltage2.These DC characteristics are in common regardless of product classification.Data Sheet M14466EJ5V0DS8AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)AC Test Conditions[ µPD448012-B55X, µPD448012-B70X, µPD448012-B85X, µPD448012-B10X ]Input Waveform (Rise and Fall Time ≤ 5 ns)0.1V CC0.9V CCOutput WaveformOutput Load1TTL + 50 pF[ µPD448012-C70X, µPD448012-C85X, µPD448012-C10X, µPD448012-C12X ]Input Waveform (Rise and Fall Time ≤ 5 ns)0.1V CC0.9V CCOutput WaveformOutput Load1TTL + 30 pFParameter Symbol V CC≥ 2.7 V Unit ConditionµPD448012µPD448012µPD448012µPD448012-B55X-B70X-B85X-B10XMIN.MAX.MIN.MAX.MIN.MAX.MIN.MAX.Read cycle time t RC557085100nsAddress access time t AA557085100ns Note 1 /CE1 access time t CO1557085100nsCE2 access time t CO2557085100ns/OE to output valid t OE30354050ns/LB, /UB to output valid t BA557085100nsOutput hold from address change t OH10101010ns/CE1 to output in low impedance t LZ110101010ns Note 2 CE2 to output in low impedance t LZ210101010ns/OE to output in low impedance t OLZ0000ns/LB, /UB to output in low impedance t BLZ10101010ns/CE1 to output in high impedance t HZ120253035nsCE2 to output in high impedance t HZ220253035ns/OE to output in high impedance t OHZ20253035ns/LB, /UB to output in high impedance t BHZ20253035nsNotes 1.The output load is 1TTL + 50 pF.2.The output load is 1TTL + 5 pF.Read Cycle (2/2) (C version)Parameter Symbol V CC≥ 2.2 V Unit ConditionµPD448012µPD448012µPD448012µPD448012-C70X-C85X-C10X-C12XMIN.MAX.MIN.MAX.MIN.MAX.MIN.MAX.Read cycle time t RC7085100120nsAddress access time t AA7085100120ns Note 1 /CE1 access time t CO17085100120nsCE2 access time t CO27085100120ns/OE to output valid t OE35405060ns/LB, /UB to output valid t BA7085100120nsOutput hold from address change t OH10101010ns/CE1 to output in low impedance t LZ110101010ns Note 2 CE2 to output in low impedance t LZ210101010ns/OE to output in low impedance t OLZ0000ns/LB, /UB to output in low impedance t BLZ10101010ns/CE1 to output in high impedance t HZ125303540nsCE2 to output in high impedance t HZ225303540ns/OE to output in high impedance t OHZ25303540ns/LB, /UB to output in high impedance t BHZ25303540nsNotes 1.The output load is 1TTL + 30 pF.2.The output load is 1TTL + 5 pF.Data Sheet M14466EJ5V0DS9Data Sheet M14466EJ5V0DS10/LB, /UB (Input)CE2 (Input)/CE1 (Input)Address (Input)I/O (Output)/OE (Input)Remark In read cycle, /WE should be fixed to high level.Write Cycle (1/2) (B version)Parameter Symbol V CC≥ 2.7 V Unit ConditionµPD448012µPD448012µPD448012µPD448012-B55X-B70X-B85X-B10XMIN.MAX.MIN.MAX.MIN.MAX.MIN.MAX.Write cycle time t WC557085100ns/CE1 to end of write t CW150557080nsCE2 to end of write t CW250557080ns/LB, /UB to end of write t BW50557080nsAddress valid to end of write t AW50557080nsAddress setup time t AS0000nsWrite pulse width t WP45505560nsWrite recovery time t WR0000nsData valid to end of write t DW25303540nsData hold time t DH0000ns/WE to output in high impedance t WHZ20253035ns Note Output active from end of write t OW5555nsNote The output load is 1TTL + 5 pF.Write Cycle (2/2) (C version)Parameter Symbol V CC≥ 2.2V Unit ConditionµPD448012µPD448012µPD448012µPD448012-C70X-C85X-C10X-C12XMIN.MAX.MIN.MAX.MIN.MAX.MIN.MAX.Write cycle time t WC7085100120ns/CE1 to end of write t CW1557080100nsCE2 to end of write t CW2557080100ns/LB, /UB to end of write t BW557080100nsAddress valid to end of write t AW557080100nsAddress setup time t AS0000nsWrite pulse width t WP50556085nsWrite recovery time t WR0000nsData valid to end of write t DW30354060nsData hold time t DH0000ns/WE to output in high impedance t WHZ25303540ns Note Output active from end of write t OW5555nsNote The output load is 1TTL + 5 pF.Address (Input)/CE1 (Input)/LB, /UB (Input)I/O (Input / Output)CE2 (Input)/WE (Input)Cautions 1.During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.2.Do not input data to the I/O pins while they are in the output state.Remarks 1.Write operation is done during the overlap time of a low level /CE1, /WE, /LB and/or /UB, and ahigh level CE2.2.If /CE1 changes to low level at the same time or after the change of /WE to low level, or if CE2changes to high level at the same time or after the change of /WE to low level, the I/O pins will remain high impedance state.3.When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level,read operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance.Address (Input)/CE1 (Input)/LB, /UB (Input)I/O (Input)CE2 (Input)/WE (Input)Cautions 1.During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.2.Do not input data to the I/O pins while they are in the output state.RemarkWrite operation is done during the overlap time of a low level /CE1, /WE, /LB and/or /UB, and a high level CE2.Address (Input)CE2 (Input)/LB, /UB (Input)I/O (Input)/CE1 (Input)/WE (Input)Cautions 1.During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.2.Do not input data to the I/O pins while they are in the output state.RemarkWrite operation is done during the overlap time of a low level /CE1, /WE, /LB and/or /UB, and a high level CE2.Write Cycle Timing Chart 4 (/LB, /UB Controlled)Address (Input)/LB, /UB (Input)I/O (Input)CE2 (Input)/WE (Input)/CE1 (Input)Cautions 1.During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.2.Do not input data to the I/O pins while they are in the output state.RemarkWrite operation is done during the overlap time of a low level /CE1, /WE, /LB and/or /UB, and a high level CE2.Low V CC Data Retention Characteristics (T A = –25 to +85°C)Parameter Symbol Test Condition V CC≥ 2.7 V V CC≥ 2.2 V UnitµPD448012µPD448012-B××X-C××XMIN.TYP.MAX.MIN.TYP.MAX.Data retention V CCDR1/CE1 ≥ V CC− 0.2 V, CE2 ≥ V CC− 0.2 V 1.0 3.6 1.0 3.6V supply voltage V CCDR2CE2 ≤ 0.2 V 1.0 3.6 1.0 3.6V CCDR3/LB = /UB ≥ V CC− 0.2 V, 1.0 3.6 1.0 3.6/CE1 ≤ 0.2 V, CE2 ≥ V CC− 0.2 VData retention I CCDR1V CC = 1.5 V, /CE1 ≥ V CC− 0.2 V,0.5 6.00.5 6.0µA supply current CE2 ≥ V CC− 0.2 VI CCDR2V CC = 1.5 V, CE2 ≤ 0.2 V0.5 6.00.5 6.0I CCDR3V CC = 1.5 V, /LB = /UB ≥ V CC− 0.2 V,0.5 6.00.5 6.0/CE1 ≤ 0.2 V, CE2 ≥ V CC− 0.2 VChip deselection t CDR00ns to data retentionmodeOperation t R t RC Note t RC Note ns recovery timeNote t RC : Read cycle timeData Retention Timing Chart(1) /CE1 ControlledV IH (MIN.)V CCDR (MIN.)V IL (MAX.)V CCGNDV CC (MIN.)NoteNote B version : 2.7 V, C version : 2.2 V RemarkOn the data retention mode by controlling /CE1, the input level of CE2 must be ≥ V CC − 0.2 V or ≤ 0.2 V.The other pins (Address, I/O, /WE, /OE, /LB, /UB) can be in high impedance state.(2) CE2 ControlledV IH (MIN.)V CCDR (MIN.)V IL (MAX.)VCCGNDV CC (MIN.)NoteNote B version : 2.7 V, C version : 2.2 V RemarkOn the data retention mode by controlling CE2, the other pins (/CE1, Address, I/O, /WE, /OE, /LB, /UB) can be in high impedance state.(3) /LB, /UB ControlledV CCV CC (MIN.)NoteV IH (MIN.)V CCDR (MIN.)V IL (MAX.)GNDNote B version : 2.7 V, C version : 2.2 VRemark On the data retention mode by controlling /LB and /UB, the input level of /CE1 and CE2 must be ≥ V CC− 0.2 V or ≤ 0.2 V. The other pins (Address, I/O, /WE, /OE) can be in high impedance state.Package DrawingNOTES48-PIN PLASTIC TSOP(I ) (12x18)ITEM MILLIMETERS A B C E I 12.0±0.10.5 (T.P.)0.1±0.050.45 MAX.K 1.2 MAX.16.4±0.10.145±0.05F 0.10M D 0.22±0.051. Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition.2. "A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.)1.0±0.05G L 0.50.10N P 18.0±0.2Q 3°+5°−3°0.25R S48GY-50-MJH1-1S0.60±0.15J 0.8±0.2Recommended Soldering ConditionsPlease consult with our sales offices for soldering conditions of the µPD448012-X.Types of Surface Mount DeviceµPD448012GY-BxxX-MJH : 48-pin PLASTIC TSOP (I) (12x18) (Normal bent)µPD448012GY-CxxX-MJH : 48-pin PLASTIC TSOP (I) (12x18) (Normal bent)[ MEMO ]Data Sheet M14466EJ5V0DS21Data Sheet M14466EJ5V0DS22[ MEMO ]Data Sheet M14466EJ5V0DS23M8E 00. 4The information in this document is current as of July, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information.written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. 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To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features.NEC semiconductor products are classified into the following three quality grades:"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application."Standard":Computers, office equipment, communications equipment, test and measurement equipment, audioand visual equipment, home electronic appliances, machine tools, personal electronic equipmentand industrial robots"Special":Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disastersystems, anti-crime systems, safety equipment and medical equipment (not specifically designedfor life support)"Specific":Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, lifesupport systems and medical equipment for life support, etc.The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application.(Note)(1)"NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.(2)"NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).••••••。

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图 1 CS1242 原理框图.......................................................................................................................... 5 图 2 CS1242 管脚图.............................................................................................................................. 7 图 3 CS1242 时序图............................................................................................................................ 11 图 4 多路输入选择原理框图 ............................................................................................................. 13 图 5 外部晶振连接图 ......................................................................................................................... 15
3 CS1242 功能模块描述 ................................................................................................................. 13

8-BIT MICROCONTROLLERPublication Release Date: July 1998GENERAL DESCRIPTIONThe W78C438C is a high-performance single-chip CMOS 8-bit microcontroller that is a derivative of the W78C58 microcontroller family. The W78C438C is functionally compatible with the W78C32,except that it provides either a 64 KB program/1 MB data memory address or memory-mapped chip select logic, five general I/O ports, and four external interrupts.In the W78C32, two I/O ports, Port 1 and Port 3, are available for general-purpose use (Port 3 also supports alternative functions), and Port 2 and Port 0 are used as the address bus and data bus,respectively. To enable Port 0 and Port 2 to also be used as general purpose I/O ports, the W78C438C provides two dedicated address ports (AP5 and AP6) that serve as address output for 64KB of memory and one address/data port (DP4) that serves as ROM code input and external RAM data input/output. Unlike the W78C32, this product does not require an external latch device for multiplexing low byte addresses. The W78C438C also provides four pins (AP7.0−AP7.3) to support either 64 KB program/1 MB data memory space or memory-mapped chip select logic, one parallel I/O port (Port 8) without bit addressing mode, and two additional external interrupts (INT2, INT3) .The W78C438C is programmed in a manner fully compatible with that used to program the W78C32,except that the external data RAM is accessed by the "MOVX @Ri" instruction. Address paging is performed by loading page addresses into the HB (high byte) register, which is not a standard register in the W78C32, before execution of the "MOVX @Ri" instruction.FEATURES•8-bit CMOS microcontroller •Fully static design •DC to 40 MHz operation •ROM-less operation•256-byte on-chip scratchpad RAM•Either 64 KB program/1 MB data memory address space or 4 memory-mapped chip select pins •One 8-bit data/address port•Two 8-bit and one 4-bit (optional) address ports •Five 8-bit bidirectional I/O ports −Four 8-bit bit-addressable I/O ports and one 8-bit parallel I/O port •Eight-source, two-level interrupt capability •Three 16-bit timer/counters •Four external interrupts•One full-duplex serial channel •Built-in power management −Idle mode−Power-down mode •Packages:− 84-pin PLCC: W78C438CP-24/40− 100-pin PQFP: W78C438CF-24/40PIN CONFIGURATIONSPublication Release Date: July 1998Pin Configurations, continuedPIN DESCRIPTIONP0.0−P0.7 I/O Port 0These pins function the same as those in the W78C32, except that a multiplexed address/data bus is not provided during accesses to external memory.P1.0−P1.7 I/O Port 1Functions are the same as in the W78C32.P2.0−P2.7 I/O Port 2Functions are the same as in the W78C32, except that an upper address bus is not provided during accesses to external memory.P3.0−P3.7 I/O Port 3Functions are the same as in the W78C32.DP4.0−DP4.7 Data/Address BusDP4 provides multiplexed low-byte address/data during access to external memory.AP5.0−AP5.7 Address BusAP5 outputs the <7:0> address of the external ROM multiplexed with the <7:0> address of the external data RAM.AP6.0−AP6.7 Address BusAP6 outputs the <15:8> address of the external ROM multiplexed with the <15:8> address of the external data RAM. During the execution of "MOVX @Ri," the output of AP6 comes from the HB register, which is the page register for the high byte address, and its address is 0A1H.AP7.0−AP7.3 Address Bus/Chip Select PinsSet bit 7 of the EPMA (Extended Program Memory Address) register to determine the functions of port 7. When this bit is "0" (default value), AP7 allows the external memory data to be accessed by outputting the <19:16> address of the external memory from bits<3:0> of the EPMA register during the execution of "MOVC A, @A+DPTR" or "MOVX dest, src." At all other times, AP7<3:0> will output 0H.When this bit is "1," AP7<3:0> (CS3−0) are the chip select pins, which support memory-mapped peripheral device select, and only one pin is active low at any one time. These pins are decoded by AP6<7:6>. For details, see the table below.AP6.7AP6.6DESCRIPTION00AP70: low; others: high01AP71: low; others: high10AP72: low; others: high11AP73: low; others: highPublication Release Date: July 1998P8.0−P8.7 I/O PortFunctions are the same as those of Port 1 in the W78C31, except that they are mapped by the P8register and not bit-addressable. The P8 register is not a standard register in the W78C32. Its address is at 0A6H.INT2, INT3 External Interrupt, InputFunctions are similar to those of external INT0, INT1 in the W78C32, except that the functions/status of these interrupts are determined/shown by the bits in the XICON (External Interrupt Control)register. The XICON register is bit-addressable but is not a standard register in the W78C32. Its address is at 0C0H. For details, see the Functional Description below.EA External Address, InputFunctions same as W78C32.RST, XTAL1, XTAL2, PSEN , ALEFunctions same as W78C32.BLOCK DIAGRAMFUNCTIONAL DESCRIPTIONThe W78C438C is a functional extension of the W78C58 microcontroller. It contains a 256 × 8 RAM, 64 KB program/1 MB data memory address or memory-mapped chip select logic, two 8-bit address ports, one 8-bit data port, five general I/O ports, four external interrupts, three timers/counters, and one serial port.Dedicated Data and Address PortThe W78C438C provides four general-purpose I/O ports for W78C32 applications; the address and data bus are separated from Port 0 and Port 2 so that these ports can be used as general-purpose I/O ports. In this product, DP4 is the data bus for external ROM and RAM, AP5<7:0> are the low byte address, AP6<7:0> are the high byte address, PSEN enables the external ROM to DP4, and P3.6 (WR) and P3.7 (RD) are the write/read control signals for the external RAM. The external latch for multiplexing the low byte address is no longer needed in this product. The W78C438C uses AP5 and AP6 to support 64 KB external program memory and 64 KB external data memory, just as a standard W78C32 does.The W78C438C provides four pins, AP7.3−AP7.0 (CS3−CS0), to support either 64 KB program/1 MB data memory space or memory-mapped chip select logic. Bit 7 of the EPMA (Extended Program Memory Address) register, which is described in Table 1 below, determines the functions of these pins.When this bit is "0" (the default value), AP7<3:0> support external program/data memory addresses up to 64 KB/1 MB for applications which need additional external memory to store large amounts of data.Although there is 1M bytes memory space, instructions stored here can not be run at full range of this area except the first 64 Kbytes. It is owing to the fact that during the instruction fetch cycle, AP7<3:0> always output 0s to address lines A19−A16. This limits the program code to store at address 0−0FFFFH (64K). The rest of the area (10000H−FFFFFH) can be treated as ROM data storage which can be read by "MOVC A, @A+DPTR" instruction.When "MOVC A, @A+DPTR" is executed to read the external ROM data or "MOVX dest, src" is executed to access the external RAM data, AP7<3:0> output address <19:16> from bits <3:0> of the EPMA (Extended Program Memory Address) register. At other times, AP7<3:0> always output 0H to ensure the instruction fetch is within the 64K program memory address. Different banks can be selected by modifying the content of the EPMA register before the execution of "MOVC A, @A+DPTR" or "MOVX dest, src."[Example]. Access the external ROM/RAM data from external memory space.CLR A; Clear Accumulator.MOV DPTR, #0H; Clear DPTR.MOV0A2H, #02; Initialize EPMA(0A2H). EPMA.7 = 0: extended memory space; EPMA.<3:0> = 0010B, the address range: 20000−2FFFFH.MOVC A, @A+DPTR; Read the external ROM data from location 20000H.MOVX A, @DPTR; Read the external RAM data from location 20000H.CLR AMOV0A2H, #03H; EPMA.<3:0> = 0011B, the address range: 30000H−3FFFFH.MOVC A, @A+DPTR ; Read the external ROM data from location 30000H.MOVX@DPTR, A; Write the contents of Accumulator to external RAM data.; location 30000H.Publication Release Date: July 1998(A) EPMA.7 = 0chip select logic, which eliminates the need for glue logic. These pins are decoded by AP6<7:6>.Only one pin is active low at any time. That is, they are active individually with 16K address resolution. For example, CS0 is active low in the address range from 0000H to 3FFFH, CS1 is active low in the address range from 4000H to 7FFFH, and so forth.(B) EPMA.7 = 1The EPMA register is a nonstandard 8-bit SFR at address 0A2H in the standard W78C32. To read/write the EPMA register, one can use the "MOV direct" instruction or "read-modify-write" instructions. Bits <6:4> of the EPMA register are reserved bits, and their output values are 111B if they are read. The content of EPMA is 70H after a reset. The EPMA register does not support bit-addressable instructions.BIT NAME FUNCTION7EPMA7EPMA7 = 0: 64 KB program/1 MB data memory space modeEPMA7 = 1: memory-mapped chip select mode6EPMA6Reserved5EPMA5Reserved4EPMA4Reserved3EPMA3Value of AP7.32EPMA2Value of AP7.21EPMA1Value of AP7.10EPMA0Value of AP7.0Table 1. Functional Description of EPMA RegisterAdditional I/O PortThe W78C438C provides one parallel I/O port, Port 8. Its function is the same as that of Port 1 in the W78C31, except that it is mapped by the P8 register and is not bit-addressable. The P8 register is not a standard register in the standard W78C32. Its address is at 0A6H. To read/write the P8 register, one can use the "MOV direct" instruction or "read-modify-write" instructions.[Example]: MOV 0A6H, A; Output data via Port 8.MOV A, 0A6H; Input data via Port 8.Additional External InterruptThe W78C438C provides two additional external interrupts, INT2 and INT3, whose functions are similar to those of external interrupts 0 and 1 in the W78C32. The functions (or the status) of these interrupts are determined by (or shown by) the bits in the XICON (External Interrupt Control) register. For details, see Table 2. The XICON register is bit-addressable but is not a standard register in the standard 80C32. Its address is at 0C0H. To set/clear the bit of the XICON register, one can use the vector addresses and the priority polling sequence within the same level are shown in Table 3. [Example].SETB0C0H; INT2 is falling-edge triggered.SETB0C3H; INT2 is high-priority.SETB0C2H; Enable INT2.CLR0C4H; INT3 is low-level triggered.Publication Release Date: July 1998Table 2. Functions of XICON RegisterINTERRUPT SOURCE VECTOR ADDRESSPRIORITY SEQUENCEExternal Interrupt 003H 0 (Highest)Timer/Counter 00BH 1External Interrupt 113H 2Timer/Counter 11BH 3Serial Port 23H 4Timer/Counter 22BH 5External Interrupt 233H 6External Interrupt 33BH7 (Lowest)Table 3. Priority of InterruptsNewly Added Special Function RegistersThe W78C438C uses four newly defined special function registers, which are described in Table 4. Toread/write these registers, use the "MOV direct" or "read-modify-write" instructions.Table 4. Newly Added Special Function Registers of the W78C438CNotes:1. The instructions used to access these nonstandard registers may cause assembling errors with respect to the 2500 A. D.assembler, but these errors can be ignored by adding directive ".RAMCHK OFF" ahead these instructions.2. In the newly added SFR of W78C438C, only XICON register is bit-addressable.Power Reduction FunctionThe W78C438C supports power reduction just as the W78C32 does. The following table shows the status of the external pins during the idle and power-down modes.Note: AP7 is either 0 or a value decoded by AP6<7:6>, depending on the value of EPMA.7.Programming DifferenceThe W78C438C is programmed in the same way as the W78C32, except that the external data RAM is accessed by a "MOVX @Ri" instruction. To support address paging, there is an additional 8-bit SFR "HB" (high byte), which is a nonstandard register, at address 0A1H. During execution of the "MOVX @Ri" instruction, the contents of HB are output to AP6. The page address is modified by loading the HB register with a new value before execution of the "MOVX @Ri" instruction. To read/write the HB register, one can use the "MOV direct" instruction or "read-modify-write" instructions. The HB register does not support bit-addressable instructions.[Example].MOV R1, #0H; R1 = 0.MOV0A1H, #0FFH; HB contents FFH.MOVX A, @R1; Read the contents of external RAM location FF00H into; Accumulator.MOV0A1H, #12H; HB contents 12H.MOVX@R1, A; Copies the contents of Accumulator into external RAM; location 1200H.ABSOLUTE MAXIMUM RATINGSPARAMETER SYMBOL MIN.MAX.UNIT DC Power Supply V DD−V SS-0.3+7.0V Input Voltage V IN V SS -0.3V DD +0.3V Operating Temperature T OPR070°C Storage Temperature T STG-55+150°C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.Publication Release Date: July 1998DC CHARACTERISTICSDD −SS A OSC Notes:1. 0 < V IN < V DD , for INT2, INT3, RESET, EA , Port 0, DP4, P1, P2, P3 and P8 inputs in leakage.2. Using an internal pull low/high resistor (approx. 30K).3. ALE, PSEN , P0 and DP4 in external program or data access mode.4. The maximum input voltage is V DD +0.2V.5. XTAL1 is a CMOS input and RESET is a Schmitt trigger input.AC CHARACTERISTICSAC specifications are a function of the particular process used to manufacture the product, the ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications can be expressed in terms of multiple input clock periods (T CP), and actual parts will usually experience less than a ±20 nS variation.Clock Input WaveformPARAMETER SYMBOL MIN.TYP.MAX.UNIT NOTES Operating Speed F OP0-40MHz1 Clock Period T CP25--nS2 Clock High T CH10--nS3 Clock Low T CL10--nS3Notes:1. The clock may be stopped indefinitely in either state.2. The T CP specification is used as a reference in other specifications.3. There are no duty cycle requirements on the XTAL1 input.Program Fetch CycleData Memory Read/Write CycleNote: "∆" (due to buffer driving delay and wire loading) is 20 nS.Publication Release Date: July 1998TIMING WAVEFORMSProgram Fetch CycleData Memory Read/Write CycleTYPICAL APPLICATION CIRCUITSUsing 128K × 8 bit External EPROM (W27E010)Figure APublication Release Date: July 1998CRYSTAL C1C2R 16 MHz 30P 30P −24 MHz 15P 15P −33 MHz 10P 10P 6.8K 40 MHz5P5P6.8KAbove table shows the reference values for crystal applications.Notes:1. For C1, C2, R components refer to Figure A.2. It is recommended that the crystals be replaced with oscillators for applications above 35 MHz.PACKAGE DIMENSIONS84-pin PLCCPackage Dimensions, continued100-pin QFPHeadquarters No. 4, Creation Rd. III,Science-Based Industrial Park,Hsinchu, Taiwan TEL: 886-3-5770066FAX: 886-3-5792766/Voice & Fax-on-demand: 886-2-27197006Taipei Office11F, No. 115, Sec. 3, Min-Sheng East Rd.,Taipei, TaiwanTEL: 886-2-27190505FAX: 886-2-27197502Winbond Electronics (H.K.) Ltd.Rm. 803, World Trade Square, Tower II,123 Hoi Bun Rd., Kwun Tong,Kowloon, Hong Kong TEL: 852-********FAX: 852-********Winbond Electronics North America Corp.Winbond Memory Lab.Winbond Microelectronics Corp.Winbond Systems Lab.2727 N. First Street, San Jose,CA 95134, U.S.A.TEL: 408-9436666FAX: 408-5441798Note: All data and specifications are subject to change without notice.。