test pattern generation介绍

1 HDL描述 版图(layout) 裸片（die）

芯片（chip） 产品（product） 综合(synthesis) 制造

封装(package) 测试（test） 测试 验证(verification) 第四章 DFT基础

4．1 测试在半导体产品实现过程中的意义

一 半导体产品的实现过程

集成电路从设计到产品一般要经历以下几个步骤才能成为产品（如下图所示）：

1． 设计过程：集成电路设计一般从编写HDL代码开始，HDL代码可能用verilog，也可能用VHDL语言写成，可能是RTL级，也可能是门级。如果是RTL级，首先进行逻辑综合、验证将设计转变成门级网表，然后进行布局布线变成最终的版图。

2． 制造过程：代工厂接受来自设计者的版图数据（GDSII）将其制成掩膜版（mask），然后通过复杂的制造过程将期望的电路做在晶园片上，这时晶园片上已经包含了若干个芯片的原型－－裸片（die）。

3． 晶园片测试：制造好的晶园片需要进行严格的测试然后划片、封装，实际上只有那些通过测试的裸片才会进行封装，而未通过测试的裸片被淘汰。经过封装的裸片就变成芯片。

4． 芯片测试：通过晶园片测试和封装的芯片还不能算真正的产品，它仍然要进一步进行测试确认没有故障才能成为真正的半导体产品。

从这个过程可以看出，测试是半导体产品实现过程中一个必不可少的环节。

二 测试定义

测试实际上是指将一定的激励信号加载到需要检测的半导体产品的输入引脚，然后在它的输出引脚检测电路的响应，并将它与期望的响应相比较以判断电路是否有故障的过程（如图所示）。

由图可以看出，要实现测试，首先要有激励信号，这个激励信号就是所谓的测试向量（test vector）。激励信号由测试设备产生；然后要判断电路是否有故障，就必须检测响应，并将实际检测的响应与期望的响应相比较，如果两者不一致，我们就认为电路中有故障。当然在这个过程中，测试设备要发出适当的控制信号，以使得整个测试过程得以顺利进行。

Silicon Test and Yield AnalysisTessent MemoryBIST Embedded Memory Self-Test and Repair

Industry Leading Solution for Memory Built-In Self-TestMentor Graphics Tessent

™

MemoryBIST provides a complete solution for at-speed testing, diagnosis, and repair of embedded memories. The solution’s architecture is hierarchical, allowing BIST and self-repair capabilities to be added to individual cores as well as at the top level.On-chip generated algorithmic test patterns are delivered to the memories at appli-cation clock frequencies. The Tessent MemoryBIST controllers are configurable to support a variety of memory types, as well as a range of memory timing inter-faces and memory port configurations. The controllers are accessed and controlled through the test access port (TAP) interface using IEEE 1149.1 and IEEE 1500 protocols or through a specified CPU interface. The controllers can be accessed throughout the life of the integrated circuit, including manufacturing test, silicon debug, and system verification.Tessent MemoryBIST includes a unique comprehensive automation flow that provides design rule checking, test planning, integration, and verification all at the RTL or gate level. All test capabilities created by Tessent MemoryBIST are fully supported by the Tessent SiliconInsight® interactive diagnostic tools.Hard Algorithm ProgrammabilityAt design time, one or more Mentor-provided or user-programmed memory test algorithms can be hard-coded into a Tessent MemoryBIST controller. Any of Key BenefitsFast self-test and self-repair IP •󰀃integration, as well as reuse of embedded memory test inserted cores, shorten time-to-market.Design-time algorithm program-•󰀃ming allows for quality improve-ment and test time optimization.Field algorithm programming •󰀃provides full control of quality and test time trade-offs.Built-in row- and column-based •󰀃repair analysis reduces test time for repairable memories.Single insertion memory repair on •󰀃any tester reduces manufacturing costs.Mentor Graphics award-winning •󰀃customer support ensures success.Key FeaturesDesign-time algorithm program-•󰀃ming supports hardcoding of custom test algorithms. Innovative architecture supports the program-ming of any test algorithm.Field algorithm programming •󰀃supports run-time programming of custom test algorithms. Full automation provided for down-loading program code through the TAP or CPU interface.On-chip global eFuse manage-•󰀃ment includes fuse data compres-sion and programming.On-chip test and repair supports •󰀃third-party repairable SRAMs.Supports any number of power •󰀃domains distributed across any number of physical blocks.Supports any level of parallelism •󰀃for both test and repair activities.Hierarchical Tessent MemoryBIST infrastructure.

一种低功耗系统芯片的可测试性设计方案

徐太龙;鲁世斌;代广珍;孟坚;陈军宁

【摘 要】低功耗技术，如多电源多电压和电源关断等的应用，给现代超大规模系统芯片可测试性设计带来诸多问题。为此，采用工业界认可的电子设计自动化工具和常用的测试方法，构建实现可测试性设计的高效平台。基于该平台，提出一种包括扫描链设计、嵌入式存储器内建自测试和边界扫描设计的可测性设计实现方案。实验结果表明，该方案能高效、方便和准确地完成低功耗系统芯片的可测性设计，并成功地在自动测试仪上完成各种测试，组合逻辑和时序逻辑的扫描链测试覆盖率为98.2%。%The low power design technologies such as Multi-supply

Multi-voltage(MSMV) and Power Shut-off(PSO), present many challenges

for the testability design of modern very large scale integration System-on-chip(SoC). Based on the efficient implementation platform constructed

by using the industrial electronic design automation tools and the widely

used testability methods, a testability design scheme that includes the scan

chain, memory built-in-self-test and boundary scan is proposed.

Experimental results show that the scheme can efficiently, conveniently

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