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ISL6262Printer Friendly Version Two-Phase Core Regulator for IMVP-6 Mobile CPUsDatasheets, Related Docs & Simulations ApplicationDiagramsRelatedDevicesOrdering InformationAvailable in RoHS/Pb-FreeBuy direct from IntersilCheck distributorinventoryRequest samplesPart No.Design-InStatus Temp.Package MSLPriceUS $ISL6262CRZ Active Comm48 Ld QFN2 3.80ISL6262CRZ-T Active Comm48 Ld QFN T+R2 3.80ISL6262CRZ-TK Active Comm48 Ld QFN T+R2 3.80ISL6262IRZ Active Ind48 Ld QFN2 6.16ISL6262IRZ-T Active Ind48 Ld QFN T+R2 6.16The price listed is the manufacturer's suggested retail price for quantitiesbetween 100 and 999 units. However, prices in today's market are fluid and maychange without notice.MSL = Moisture Sensitivity Level - per IPC/JEDEC J-STD-020SMD = Standard Microcircuit DrawingRelated DocumentationDatasheet(s):?The ISL6262 datasheet is restricted to IMVP licensees only. To request a datasheet please email Majid Kafi at mkafi@Application Block Diagrams?Notebook ComputersRelated Devices Parametric Table ISL6210Dual Synchronous Rectified MOSFET DriversISL6228High-Performance Dual-Output Buck Controller for Notebook ApplicationsISL6236High-Efficiency, Quad-Output, Main Power Supply Controllers for Notebook ComputersISL6237High-Efficiency, Quad-Output, Main Power Supply Controllers for Notebook ComputersISL6261One-Phase INT DC/DC Buck ControllerISL6261A1-Phase Core Controller (Santa Rosa, IMVP-6+)ISL6262A2-Phase Core Controller (Santa Rosa, IMVP-6+)ISL62635-Bit VID Single-Phase Graphics Core Voltage RegulatorISL6263A 5-Bit VID Single-Phase Voltage Regulator with Power Monitor for IMVP-6+ Santa Rosa GPU CoreISL6263B 5-Bit VID Single-Phase Voltage Regulator with Current Monitor for IMVP-6+ Santa Rosa GPU CoreISL6268High-Performance Notebook PWM ControllerISL6269High-Performance Notebook PWM Controller with Bias Regulator and Audio-Frequency ClampISL6269A High-Performance Notebook PWM ControllerISL6269B High-Performance Notebook PWM Controller with Audio-Frequency ClampISL63064-Phase PWM Controller with 8-Bit DAC Code Capable of Precision RDS(ON)or DCR Differential Current SensingISL63076-Phase PWM Controller with 8 Bit VID Code Capable of Precision RDS(ON)or DCR Differential CurrentISL6312Four-Phase Buck PWM Controller with Integrated MOSFET Drivers for Intel VR10, VR11, and AMD ApplicationsISL6312A Four-Phase Buck PWM Controller with Integrated MOSFET Drivers for Intel VR10, VR11, and AMD ApplicationsISL6313Two-Phase Buck PWM Controller with Integrated MOSFET Drivers for Intel VR11 and AMD ApplicationsISL6314Single-Phase Buck PWM Controller with Integrated MOSFET Drivers for Intel VR11 and AMD ApplicationsISL6315Two-Phase Multiphase Buck PWM Controller with MOSFET Drivers Integrated (No Droop)ISL6322Four-Phase Buck PWM Controller with Integrated MOSFET Drivers and I 2CInterface for Intel VR10, VR11, and AMD ApplicationsISL63264-Phase PWM Controller with 8-Bit DAC Code Capable of Precision DCR Differential Current SensingISL6326B 4-Phase PWM Controller with 8-Bit DAC Code Capable of Precision DCR Differential Current SensingISL6327Enhanced 6-Phase PWM Controller with 8-Bit VID Code and Differential Inductor DCR or Resistor Current SensingISL63415V or 12V Single Synchronous Buck Pulse-Width Modulation (PWM) Controller ISL6341A5V or 12V Single Synchronous Buck Pulse-Width Modulation (PWM) Controller ISL6341B5V or 12V Single Synchronous Buck Pulse-Width Modulation (PWM) Controller ISL6410Single Synchronous Buck Regulator with Integrated FET for WLAN Chipsets ISL6441 1.4MHz Dual, 180° Out-of-Phase, Step-Down PWM and Single Linear Controller ISL6445 1.4MHz Dual, 180° Out-of-Phase, Step-Down PWM ControllerISL654266A Dual Synchronous Buck Regulator with Integrated MOSFETsISL6549Single 12V Input Supply Dual Regulator -Synchronous Rectified Buck PWM and Linear Power ControllerISL6563Two-Phase Multiphase Buck PWM Controller with Integrated MOSFET Drivers ISL8502 2.5A Synchronous Buck Regulator with Integrated MOSFETsISL8843Single-Ended Current Mode PWM Controller with 3% Current Limit and Military Temp Grade OptionISL91061.2A 1.6MHz Low Quiescent Current High Efficiency Synchronous Buck RegulatorISL9440Triple, 180° Out-of-Phase, Step-Down PWM and Single Linear ControllerISL97656640kHz/1.2MHz PWM Step-Up RegulatorAbout Us |Careers |Contact Us |Investors |Legal |Privacy |Site Map |Subscribe |Intranet©2007. All rights reserved.元器件交易网。
VR11.1, VR12 Compatible Synchronous Rectified Buck MOSFET DriverISL6627The ISL6627 is a high frequency MOSFET driver designed to drive upper and lower power N-Channel MOSFETs in a synchronous rectified buck converter topology. The advanced PWM protocol of ISL6627 is specifically designed to work with Intersil VR11.1, VR12 controllers and combined with N-Channel MOSFETs to form a complete core-voltage regulator solution for advanced microprocessors. When ISL6627 detects a PSI protocol sent by an Intersil VR11.1, VR12 controller, it activates Diode Emulation (DE) operation; otherwise, it operates in normal Continuous Conduction Mode (CCM) PWM mode.To further enhance light load efficiency, the ISL6627 enables diode emulation operation during PSI mode. This allows Discontinuous Conduction Mode (DCM) by detecting when the inductor current reaches zero and subsequently turning off the low side MOSFET to prevent it from sinking current.When ISL6627 detects Diode Braking command from the PWM, it turns off both gates and reduces overshoot in load transient situations.An advanced adaptive shoot-through protection is integrated to prevent both the upper and lower MOSFETs from conducting simultaneously and to minimize dead time. The user also has the option to program the driver working in fixed propagation delay mode to optimize the regulator efficiency. The ISL6627 has a 20kΩ integrated high-side gate-to-source resistor to prevent self turn-on due to high input bus dV/dt.Related Literature•Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)”•Technical Brief TB417 “Designing Stable Compensation Networks for Single Phase Voltage Mode Buck Regulators”Features•Intersil VR11.1 and VR12 Compatible•Dual MOSFET Driver for Synchronous Rectified Bridge •Advanced Adaptive Zero Shoot-through Protection •Programmable Fixed Deadtime for Efficiency Optimization •Low Standby Bias Current•36V Internal Bootstrap Diode•Bootstrap Capacitor Overcharge Prevention•Supports High Switching Frequency-4A Sinking Current Capability-Fast Rise/Fall Times and Low Propagation Delays •Integrated High-Side Gate-to-Source Resistor to Prevent Self Turn-on Due to High Input Bus dV/dt•Power Rails Undervoltage Protection•Expandable Bottom Copper Pad for Enhanced Heat Sinking •Dual Flat 10 Ld (3x3 DFN) Package-Near Chip-Scale Package Footprint; Improves PCB Efficiency and Thinner in Profile•Pb-Free (RoHS Compliant)Applications•High Light Load Efficiency Voltage Regulators•Core Regulators for Advanced Microprocessors•High Current DC/DC Converters•High Frequency and High Efficiency VRM and VRDEN VCCPWM +5V33.6k28.8kBOOTUGATEPHASELGATEGNDSHOOT-THROUGHPROTECTION/20kΩCONTROLLOGICPOR/TDDELAYPROGRAMMINGFIGURE 1.ISL6627 BLOCK DIAGRAMTypical Application CircuitPin ConfigurationISL6627(10 LD 3x3 DFN)TOP VIEW2 3 4 1 59 8 7 10 6UGATE BOOTTD PWMGNDPHASEENNCVCCLGATE PAD(GND)Functional Pin DescriptionsPIN #SYMBOL DESCRIPTION1UGATE Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.2BOOT Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and thePHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Internal BootstrapDevice” on page7 for guidance in choosing the capacitor value.3TD Deadtime programming pin. Connect to ground or VCC via resistor to program fixed time delay from LGATE fall toUGATE rise or UGATE fall to LGATE rise. Open pin sets the adaptive mode. See Table 1 for more details.4PWM Control input for the driver. The PWM signal can enter three distinct states during operation;see “Advanced PWMProtocol (Patent Pending)” on page6 for further details. Connect this pin to the PWM output of the controller.5GND Bias and reference ground. All signals are referenced to this node. It is also the power ground return of thedriver.6LGATE Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.7VCC Connect to 5V bias supply. This pin supplies power to the gate drives and small-signal circuitry. Place a highquality low ESR ceramic capacitor from this pin to GND.8NC No connection.9EN Enable input pin. Connect this pin high to enable the driver and low to disable the driver.-PAD EPAD at ground potential. Soldering it directly to GND plane is required for thermal considerations. Ordering InformationPART NUMBER (Notes 1, 2, 3)PARTMARKINGTEMP. RANGE(°C)PACKAGE(Pb-Free)PKG.DWG. #ISL6627CRZ66270 to +7010 Ld 3x3 DFN L10.3X3ISL6627IRZ627I-40 to +8510 Ld 3x3 DFN L10.3X3NOTES:1.Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.2.These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% mattetin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.3.For Moisture Sensitivity Level (MSL), please see device information page for ISL6627. For more information on MSL please see techbrief TB363.Absolute Maximum Ratings Thermal InformationSupply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V Input Voltage (V EN, V PWM). . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V BOOT Voltage (V BOOT-GND) . . . . . . . . . .-0.3V to 25V (DC) or 36V (<200ns) BOOT to PHASE Voltage (V BOOT-PHASE). . . . . . . . . . . . . . . .-0.3V to 7V (DC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to 9V (<10ns) PHASE Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 25V (DC) . . . . . . . . . . . . . . . GND -8V (<20ns Pulse Width, 10μJ) to 30V (<100ns) UGATE Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . V PHASE - 0.3V (DC) to V BOOT . . . . . . . . . . . . . . . . . . .V PHASE - 5V (<20ns Pulse Width, 10μJ) to V BOOT LGATE Voltage. . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V (DC) to VCC + 0.3V . . . . . . . . . . . . . . . . GND - 2.5V (<20ns Pulse Width, 5μJ) to VCC + 0.3V Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C ESD RatingHuman Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.5kV Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1kV Latch Up (Tested per JESD78C; Class II, Level A). . . . . . . . . . . . . . . 100mA Thermal ResistanceθJA (°C/W)θJC (°C/W) 10 Ld 3x3 DFN Package (Notes 4, 5). . . . . 5110 Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below /pbfree/Pb-FreeReflow.asp Recommended Operating ConditionsAmbient Temperature Range(ISL6627IRZ) . . . . . . . . . . . .-40°C to +85°C Ambient Temperature Range (ISL6627CRZ) . . . . . . . . . . . ..0°C to +70°C Maximum Operating Junction Temperature. . . . . . . . . . . . . . . . . . +125°C Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.NOTES:4.θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See TechBrief TB379.5.For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Boldface limits apply over the operating temperature range.PARAMETER SYMBOL TEST CONDITIONSMIN(Note 7)TYPMAX(Note 7)UNITSVCC SUPPLY CURRENTNo Load Switching Supply Current IVCC f_PWM = 300kHz, VCC = 5V, EN = High 1.27mA Standby Supply Current IVCC VCC = 5V, PWM 0V to 2.5V transition, EN = High 1.85mAVCC = 5V, PWM 0V to 2.5V transition, EN = Low 1.15mA POWER-ON RESET AND ENABLEVCC Rising POR Threshold 3.20 3.85 4.40V VCC Falling POR Threshold 3.00 3.52 4.00V VCC POR Hysteresis130300530mV EN High Threshold 1.40 1.65 1.90V EN Low Threshold 1.20 1.35 1.55V PWM INPUT (See “TIMING DIAGRAM” on page6)Input Current IPWM VPWM = 5V155µAVPWM = 0V-133µA Three-State Lower Gate Falling Threshold VCC = 5V 1.6V Three-State Lower Gate Rising Threshold VCC = 5V 1.1V Three-State Upper Gate Rising Threshold VCC = 5V 3.2V Three-state Upper Gate Falling Threshold VCC = 5V 2.8V UGATE Rise Time (Note 6)t_RU VCC = 5V, 3nF load, 10% to 90%8ns LGATE Rise Time (Note 6)t_RL VCC = 5V, 3nF load, 10% to 90%8ns UGATE Fall Time (Note 6)t_FU VCC = 5V, 3nF load, 10% to 90%8ns LGATE Fall Time (Note 6)t FL VCC = 5V, 3nF load, 10% to 90%4ns UGATE Turn-On Propagation Delay (Note 6)t PDHU VCC = 5V, 3nF load, adaptive28ns LGATE Turn-On Propagation Delay (Note 6)t PDHL VCC = 5V, 3nF load, adaptive16ns UGATE Turn-Off Propagation Delay (Note 6)t PDLU VCC = 5V, 3nF load15nsLGATE Turn-Off Propagation Delay (Note 6)t PDLL VCC = 5V, 3nF load14ns Minimum LGATE on Time at Diode Emulationt LG_ON_DM VCC = 5V230330450nsPROPAGATION DELAY PROGRAMMINGUGATE Fall to LGATE Rise Timet PDUFLRVCC = 5V, 3nF Load, 90% to 10%, short resistor from TD to VCC23ns VCC = 5V, 3nF Load, 90% to 10%, 100k Ω resistor from TD to VCC18ns VCC = 5V, 3nF Load, 90% to 10%, 330k Ω resistor from TD to VCC15ns VCC = 5V, 3nF Load, 90% to 10%, 910k Ω resistor from TD to VCC7ns VCC = 5V, 3nF Load, 90% to 10%, short resistor from TD to GND18ns LGATE Fall to UGATE Rise Timet PDLFURVCC = 5V, 3nF Load, 90% to 10%, short resistor from TD to GND40ns VCC = 5V, 3nF Load, 90% to 10%, 100k Ω resistor from TD to GND25ns VCC = 5V, 3nF Load, 90% to 10%, 360k Ω resistor from TD to GND17ns VCC = 5V, 3nF Load, 90% to 10%, short resistor from TD to VCC27nsOUTPUT (Note 6)Upper Drive Source Current I_U_SOURCE VCC = 5V, 3nF load 2A Upper Drive Source Impedance R_U_SOURCE 20mA source current 1ΩUpper Drive Sink Current I_U_SINK VCC = 5V, 3nF load 2A Upper Drive Sink Impedance R_U_SINK 20mA sink current 1ΩLower Drive Source Current I_L_SOURCE VCC = 5V, 3nF load 2A Lower Drive Source Impedance R_L_SOURCE 20mA source current1ΩLower Drive Sink Current I_L_SINK VCC = 5V, 3nF load 4A Lower Drive Sink Impedance R_L_SINK20mA sink current0.4ΩNOTES:6.Limits established by characterization and are not production tested.7.Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested.Electrical SpecificationsRecommended Operating Conditions, Unless Otherwise Noted. Boldface limits apply over the operatingtemperature range. (Continued)PARAMETERSYMBOL TEST CONDITIONSMIN (Note 7)TYP MAX(Note 7)UNITSOperation and Adaptive Shoot-Through ProtectionDesigned for high speed switching, the ISL6627 MOSFET driver controls both high-side and low-side N-Channel FETs from one externally-provided PWM signal.A rising transition on PWM initiates the turn-off of the lowerMOSFET (see “Timing Diagram”). After a short propagation delay [t PDLL ], the lower gate begins to fall. Typical fall times [t FL ] are provided in the “Electrical Specifications” on page 4. Adaptive shoot-through circuitry monitors the LGATE voltage and turns on the upper gate following a short delay time [t PDHU ] after the LGATE voltage drops below ~1V. The user also has the option to program the propagation delay as described in “Deadtime Programming” on page 6. The upper gate drive then begins to rise [t RU ] and the upper MOSFET turns on.A falling transition on PWM indicates the turn-off of the upper MOSFET and the turn-on of the lower MOSFET. A short propagation delay [t PDLU ] is encountered before the upper gate begins to fall [t FU ]. The adaptive shoot-through circuitry monitors the UGATE-PHASE voltage and turns on the lower MOSFET a short delay time [t PDHL ], after the upper MOSFET’s gate voltage drops below 1V. The lower gate then rises [t RL ], turning on the lower MOSFET. These methods prevent both the lower and upper MOSFETs from conducting simultaneously (shoot-through), while adapting the dead time to the gate charge characteristics of the MOSFETs being used. The user also has the option to program the propagation delay as described in “Deadtime Programming” on page 6. This driver is optimized for voltage regulators with a large step down ratio. The lower MOSFET is usually sized larger compared to the upper MOSFET because the lower MOSFET conducts for a longer time during a switching period. The lower gate driver is therefore sized much larger to meet this application requirement. The 0.4Ω ON-resistance and 4A sink current capability enable the lower gate driver to absorb the charge injected into the lower gate through the drain-to-gate capacitor of the lower MOSFET and help prevent shoot through caused by the self turn-on of the lower MOSFET due to high dV/dt of the switching node.Advanced PWM Protocol (Patent Pending)The advanced PWM protocol of ISL6627 is specifically designed to work with Intersil VR11.1 and VR12 controllers. When ISL6627 detects a PSI# protocol sent by an IntersilVR11.1/VR12 controller, it turns on diode emulation operation; otherwise, it remains in normal CCM PWM mode.Note that for a PWM low to tri-level (2.5V) transition, the LGATE will not turn off until the its diode emulation minimum ON-time of 330ns (typically) passes.Diode EmulationDiode emulation allows for higher converter efficiency under light-load situations. With diode emulation active, the ISL6627 detects the zero current crossing of the output inductor and turns off LGATE, preventing the low side MOSFET from sinking current and ensuring discontinuous conduction mode (DCM) is achieved. In DCM mode, LGATE has a minimum ON-time of 330ns (typically).Deadtime ProgrammingThe part provides the user with the option to program either of the two gate propagation delays (as defined in Figure 3) in order to optimize the deadtime and maximize the efficiency of the circuit. Tying the TD pin to either GND or VCC through a specified-value resistor leads the driver to operate in fixed gate propagation delay mode. Leaving the TD pin floating results in the driver operating in adaptive deadtime mode. Refer to Table 1 for typicalprogramming resistor value options. Propagation delay has a typical tolerance of 30%. As actual deadtime depends on FET switching transition characteristics, while operating in fixed propagation delay mode, the user needs to monitor the gate transitions under worst-case operating conditions and useappropriate design margin to prevent eventual shoot-through due to insufficient dead time.FIGURE 2.TIMING DIAGRAMPWMUGATELGATEt FLt PDHU t PDLLt RLt TSSHDt PDTSt PDTS1.6V<PWM<3.2V1.1V<PWM<2.8Vt FUt RUt PDLUt PDHLt UG_OFF_DBt PDLFURt PDUFLRPower-On Reset (POR) FunctionVCC voltage level is monitored at all times. Once the VCC voltageexceeds 3.85V (typically), operation of the driver is enabled and the PWM input signal takes control of the gate drivers. If VCC drops below the falling threshold of 3.52V (typically), operation of the driver is disabled.Internal Bootstrap DeviceISL6627 features an internal bootstrap schottky diode. Simply adding an external capacitor across the BOOT and PHASE pins completes the bootstrap circuit. The bootstrap function is also designed to prevent the bootstrap capacitor from overcharging due to the large negative swing at the trailing-edge of the PHASE node excursion. This reduces the potential for overstressing the upper driver.The bootstrap capacitor must have a voltage rating above the maximum VCC voltage. Its capacitance value can be estimated from Equation 1:where Q G1 is the amount of gate charge per upper MOSFET at V GS1 gate-source voltage and N Q1 is the number of control (upper) MOSFETs. The ΔV BOOT_CAP term is defined as theallowable droop in the rail of the upper gate drive. Select results are exemplified in Figure 4.Power DissipationPackage power dissipation is mainly a function of the switching frequency (F SW ), the output drive impedance, the layoutresistance, the selected MOSFET’s internal gate resistance and its total gate charge (Q G ). Calculating the power dissipation in the driver for a desired application is critical to ensure safe operation. Exceeding the maximum allowable power dissipation level may push the IC beyond the maximum recommended operatingjunction temperature. The DFN package is more suitable for high frequency applications. See “Layout Considerations” on page 8 for thermal impedance improvement suggestions. The total driver power loss, essentially MOSFETs’ gate charge and driver internal circuitry losses, can be estimated using Equations 2 and 3, respectively.where the gate charge (Q G1 and Q G2) is defined at a particular gate to source voltage (V GS1 and V GS2) in the corresponding MOSFET datasheet; I Q is the driver’s total quiescent current with no load at both drive outputs; N Q1 and N Q2 are number of upper and lower MOSFETs, respectively; UVCC and LVCC are the drive voltages for both upper and lower FETs, respectively. The I Q*VCC product is the bias power of the driver without a load.TABLE 1.TYPICAL DELAY PROGRAMMING RESISTOR VALUE RESISTOR FROM TD TO VCC(k Ω)RESISTOR FROMTD TO GND (k Ω)LG FALL TO UG RISE DELAY (ns)UG FALL TO LG RISE DELAY (ns)short -2723100-2718330-2715910-277-Short 4018-1002518-3601718FloatingFloatingAdaptiveAdaptiveFIGURE 3.PROGRAMMABLE PROPAGATION DELAYILLUSTRATION C BOOT_CAP Q GATEΔV BOOT_CAP ---------------------------------≥Q GATE Q G1VCC•V GS1---------------------------N Q1•=(EQ. 1)50nC20nCFIGURE 4.BOOTSTRAP CAPACITANCE vs BOOT RIPPLEVOLTAGEΔV BOOT_CAP (V)C B O O T _C A P (µF )1.61.41.21.0.80.60.40.20.00.30.00.10.20.40.50.60.90.70.81.0Q GATE = 100nCP Qg_TOT P Qg_Q1P Qg_Q2I Q VCC •++=(EQ. 2)P Qg_Q1Q G1UVCC 2•V GS1----------------------------------F SW •N Q1•=P Qg_Q2Q G2LVCC 2•V GS2----------------------------------F SW •N Q2•=I DR Q G1UVCC N Q1••V GS1------------------------------------------------Q G2LVCC N Q2••V GS2-----------------------------------------------+⎝⎠⎜⎟⎛⎞F SW I Q +•=(EQ. 3)The total gate drive power losses are dissipated among the resistive components along the transition path, as outlined in Equation 4. The drive resistance dissipates a portion of the total gate drive power losses, the rest will be dissipated by the external gate resistors (R G1 and R G2) and the internal gate resistors (R GI1 and R GI2) of MOSFETs. Figures 5 and 6 show the typical upper and lower gate drives turn-on current paths.Application InformationMOSFET and Driver SelectionThe parasitic inductances of the PCB and of the power devices’packaging (both upper and lower MOSFETs) can cause serious ringing, exceeding absolute maximum rating of the devices. The negative ringing at the edges of the PHASE node could increase the bootstrap capacitor voltage through the internal bootstrap diode, and in some cases, it may overstress the upper MOSFET driver. Careful layout, proper selection of MOSFETs andpackaging, as well as the driver can minimize such unwanted stress.Layout ConsiderationsA good layout helps reduce the ringing on the switching (PHASE) node and significantly lower the stress applied to the MOSFETs as well as the driver. The following advice is meant to lead to an optimized layout:•Keep decoupling circuit loops (VCC-GND and BOOT-PHASE) as short as possible.•Minimize trace inductance, especially on low-impedance lines. All power traces (UGATE, PHASE, LGATE, GND, VCC) should be short and wide, as much as possible. •Minimize the inductance of the PHASE node. Ideally, thesource of the upper and the drain of the lower MOSFET should be as close as thermally allowable.•Minimize the current loop of the output and input power trains. Short the source connection of the lower MOSFET to ground as close to the transistor pin as feasible. Input capacitors(especially ceramic decoupling) should be placed as close to the drain of upper and source of lower MOSFETs as possible.In addition, connecting the thermal pad of the DFN package to the power ground through one or several vias is recommended for high switching frequency, high current applications. This is to improve heat dissipation and allow the part to achieve its full thermal potential.Upper MOSFET Self Turn-On Effects at StartupShould the driver have insufficient bias voltage applied, itsoutputs are floating. If the input bus is energized at a high dV/dt rate while the driver outputs are floating, due to self-coupling via the internal C GD of the MOSFET, the gate of the upper MOSFET could momentarily rise up to a level greater than the threshold voltage of the device, potentially turning on the upper switch. Therefore, if such a situation could conceivably be encountered, it is a common practice to place a resistor (R UGPH ) across the gate and source of the upper MOSFET to suppress the Miller coupling effect. The value of the resistor depends mainly on the input voltage’s rate of rise, the C GD /C GS ratio, as well as the gate-source threshold of the upper MOSFET. A higher dV/dt, a lower C GD /C GS ratio, and a lower gate-source threshold upper FET will require a smaller resistor to diminish the effect of the internal capacitive coupling. For most applications, theintegrated 20k Ω resistor is sufficient, not measurably affecting normal performance and efficiency.The coupling effect can be roughly estimated with Equation 5, which assumes a fixed linear input ramp and neglects the clamping effect of the body diode of the upper drive and the bootstrap capacitor. Other parasitic components, such as lead inductances and PCB capacitances are also not taken into account. Figure 7 provides a visual reference for this phenomenon and its potential solution.FIGURE 5.TYPICAL UPPER-GATE DRIVE TURN-ON PATHFIGURE 6.TYPICAL LOWER-GATE DRIVE TURN-ON PATHP DR P DR_UP P DR_LOW I Q VCC•++=(EQ. 4)P DR_UP R HI1R HI1R EXT1+-----------------------------------R LO1R LO1R EXT1+------------------------------------+⎝⎠⎜⎟⎛⎞P Qg_Q12-------------------•=P DR_LOW R HI2R HI2R EXT2+-----------------------------------R LO2R LO2R EXT2+------------------------------------+⎝⎠⎜⎟⎛⎞P Qg_Q22-------------------•=R EXT1R G1R GI1NQ1------------+=R EXT2R G2R GI2NQ2------------+=Q1DSG R GI1R G1BOOTR HI1C DSC GSC GDR LO1PHASEVCCVCCQ2DSG R GI2R G2R HI2C DSC GSC GDR LO2V GS_MILLER dV dt------R C rss 1e V–DS dV dt------R C ⋅iss ⋅-------------------------------–⎝⎠⎜⎟⎜⎟⎜⎟⎜⎟⎛⎞⋅⋅=R R UGPH R GI+=C rss C GD=C iss C GD C GS+=(EQ. 5)General PowerPAD Design ConsiderationsFigure 8 shows the recommended use of vias on the thermal pad to remove heat from the IC. This typical array populates the thermal pad footprint with vias spaced three times the radius distance from the center of each via. Small via size is advisable, but not to the extent that solder reflow becomes difficult. All vias should be connected to the pad potential, with low thermal resistance for efficient heat transfer. Completeconnection of the plated-through hole to each plane is important. It is not recommended to use “thermal relief” patterns to connect the vias.FIGURE 7.GATE TO SOURCE RESISTOR TO REDUCE UPPERMOSFET MILLER COUPLINGVIN QUPPERDSG R GIR U G P HBOOTDUC DSC GSC GDDLPHASEVCCI S L 6627C BOOTUGATEFIGURE 8.PCB VIA PATTERNRevision HistoryThe revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev.DATE REVISION CHANGE9/22/11FN6992.0Initial release.ProductsIntersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to /products for a complete list of Intersil product families.For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on : ISL6627To report errors or suggestions for this datasheet, please go to: /askourstaffFITs are available from our website at: /reports/searFor additional products, see /product_treeIntersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as notedin the quality certifications found at /design/qualityIntersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.For information regarding Intersil Corporation and its products, see ISL662711FN6992.0September 22, 2011Package Outline DrawingL10.3x310 LEAD DUAL FLAT PACKAGE (DFN) Rev 6, 09/09located within the zone indicated. The pin #1 identifier may be Unless otherwise specified, tolerance : Decimal ± 0.05Tiebar shown (if present) is a non-functional feature.The configuration of the pin #1 identifier is optional, but must be between 0.18mm and 0.30mm from the terminal tip.Lead width applies to the metallized terminal and is measured Dimensions in ( ) for Reference Only.Dimensioning and tolerancing conform to AMSE Y14.5m-1994.6.either a mold or mark feature.3.5.4.2.Dimensions are in millimeters.1.NOTES:DETAIL "X"TYPICAL RECOMMENDED LAND PATTERNTOP VIEW芯天下--/。
®ISL6505Multiple Linear Power Controller with ACPI Control InterfaceThe ISL6505 complements other power building blocks (voltage regulators) in ACPI-compliant designs for microprocessor and computer applications. The IC integrates three linear controllers/regulators, switching, monitoring and control functions into a 20-pin wide-body SOIC or 20-pin QFN (also known as MLF) 5x5 package. The ISL6505’s operating mode (active or sleep outputs) is selectable through two digital control pins, S3 and S5.One linear controller generates the 3.3V DUAL/3.3V SB voltage plane from the A TX supply’s 5V SB output, powering the south bridge and the PCI slots through an external NPN pass transistor during sleep states (S3, S4/S5). In active state (during S0 and S1/S2), the 3.3V DUAL/3.3V SB linear regulator uses an external N-channel pass MOSFET to connect the outputs directly to the 3.3V input supplied by an A TX power supply, for minimal losses. The 3.3V DUAL/3.3V SB output is active for as long as the A TX 5V SB voltage is applied to the chip.A controller powers up the 5V DUAL plane by switching in the A TX 5V output through an NMOS transistor in active states, or by switching in the A TX 5V SB through a PMOS (or PNP) transistor in S3 sleep state. In S4/S5 sleep states, theISL6505 5V DUAL output is either shut down or stays on, based on the state of the EN5 pin.An internal linear regulator supplies the 1.2V for the voltage identification circuitry (VID) only during active states (S0 and S1/S2), and uses the 3V3 pin as input source for its internal pass element.A linear controller generates V OUT1 from the3.3V DUAL/3.3V SB voltage plane, using an external NFET. The voltage is user-programmable to values between 1.2V and 1.5V, using an external resistor divider. The mode is user-selectable with the LAN pin; a logic high (or open) selects the 10/100 LAN mode, where V OUT1 is always on (S0-S5); a logic low selects the Gigabit Ethernet mode, where V OUT1 is only on during active modes (S0-S2). Features•Provides four ACPI-Controlled Voltages-5V DUAL USB/Keyboard/Mouse- 3.3V DUAL/3.3V SB PCI/Auxiliary/LAN- 1.2V VID Processor VID Circuitry-V OUT1 (1.2V - 1.5V programmable) LAN/Ethernet•Excellent Output Voltage Regulation-All Outputs: ±2.0% over temperature (as applicable)•Small Size; Very Low External Component Count •Undervoltage Monitoring of All Outputs with Centralized FAULT Reporting and T emperature Shutdown•QFN Package:-Compliant to JEDEC PUB95 MO-220QFN - Quad Flat No Leads - Package Outline-Near Chip Scale Package footprint, which improvesPCB efficiency and has a thinner profile•Pb-Free Plus Anneal Available (RoHS Compliant) Applications•ACPI-Compliant Power Regulation for Motherboards Pinouts - See page6.Ordering InformationPART NUMBERTEMP.RANGE (°C)PACKAGEPKG.DWG. # ISL6505CB*0 to 7020 Ld Wide SOIC M20.3 ISL6505CR*0 to 7020 Ld 5x5 QFN L20.5x5 ISL6505CRZ*(Note 1)0 to 7020 Ld 5x5 QFN(Pb-free)L20.5x5 ISL6505EVAL1Evaluation Board (SOIC)ISL6505EVAL2Evaluation Board (QFN)Add “-T” suffix for tape and reel.NOTE:1.Intersil Pb-free plus anneal products employ special Pb-freematerial sets; molding compounds/die attach materials and100% matte tin plate termination finish, which are RoHScompliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified atPb-free peak reflow temperatures that meet or exceed thePb-free requirements of IPC/JEDEC J STD-020.Simplified Power System DiagramTypical ApplicationFIGURE 2.+5V SB+3.3V IN+12V IN SX, EN5, LAN+5V IN 3.3V DUAL FAULTSHUTDOWN V GND5VSB+3.3V IN+5V SB VID_PGVID_CTDR1C CT_VIDISL6505+12V IN VID PGOODSLP_S3S3V OUT33.3V DUAL /3.3V SBC OUT3+5V IN C OUT4V OUT45V DUAL3V3DL 3V3DLSBQ2Q3Q4Q5DLA5VDLSBFAULT5VDLSS 1V2VID SHUTDOWNFAULT V OUT11.2V - 1.5VV OUT21.2V VIDC OUT1C OUT2SLP_S5S5C SS3V3R DLAQ6FB1LANEN5EN5LAN5V FIGURE 3.R20R21Absolute Maximum Ratings Thermal InformationSupply Voltage, V5VSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V DLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14.5V All Other Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+ 7.0V ESD Classification (Human Body Model) . . . . . . . . . . . . . . . . . .2kV Recommended Operating ConditionsSupply Voltage, V5VSB . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5% Lowest 5VSB Supply Voltage Guaranteeing Parameters . . . . +4.5V Digital Inputs, V Sx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to +5.5V Ambient T emperature Range. . . . . . . . . . . . . . . . . . . . .0o C to 70o C Junction Temperature Range. . . . . . . . . . . . . . . . . . . .0o C to 125o C Thermal Resistance (T ypical)θJA (o C/W)θJC (o C/W) SOIC Package (Note 2). . . . . . . . . . . .65N/AQFN Package (Notes 3, 4) . . . . . . . . .355 Maximum Junction T emperature (Plastic Package) . . . . . . . .150o C Maximum Storage T emperature Range. . . . . . . . . . -65o C to 150o C Maximum Lead T emperature (Soldering 10s) . . . . . . . . . . . . .300o C (SOIC - Lead Tips Only)CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.NOTES:2.θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.3.θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. SeeTech Brief TB379.4.For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3 PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS VCC SUPPLY CURRENTNominal Supply Current I5VSB-6-mA Shutdown Supply Current I5VSB(OFF)V SS = 0.8V-4-mA POWER-ON RESET, SOFT-START, AND VOLTAGE MONITORS5VSB Rising POR Threshold 4.0 4.3 4.5V5VSB Falling POR Threshold 3.15 3.4 3.55V5VSB POR Hysteresis-0.9-V3V3 Rising Threshold 2.8 2.93 3.0V3V3 Falling Threshold 2.65 2.78 2.9V3V3 Hysteresis-150-mV5V Rising Threshold 4.25 4.4 4.5V5V Falling Threshold 4.0 4.15 4.3V5V Hysteresis-250-mV VID_PG Rising Threshold- 1.04-VVID_PG Hysteresis-50-mV VID_CT Charging Current I VID_CT V VID_CT = 0V-10-µA Soft-Start Current I SS-10-µA Soft-Start Shutdown Voltage Threshold V SD--0.8V LINEAR REGULATOR (V OUT1; DR1 and FB1 pins)V OUT1 Regulation V OUT1 = 1.2V to 1.5V-- 2.0%V OUT1 Nominal Voltage Level V OUT1Based on external resistors- 1.5-VV OUT1 Undervoltage Rising Threshold FB1 pin- 1.2-VV OUT1 Undervoltage Hysteresis FB1 pin-50-mV DR1 Output Drive Current I DR1V3V3DL = 3.3V-10-mA1.2V VID LINEAR REGULATOR (V OUT2)1V2VID Regulation-- 2.0%1V2VID Nominal Voltage Level V 1V2VID- 1.2-V 1V2VID Undervoltage Rising Threshold -0.92-V 1V2VID Undervoltage Hysteresis -100-mV 1V2VID Output CurrentI 1V2VIDV 3V3 = 3.3V--180mA3.3V DUAL /3.3V SB LINEAR REGULATOR (V OUT3)3V3DL Sleep State Regulation -- 2.0%3V3DL Nominal Voltage Level V 3V3DL- 3.3-V 3V3DL Undervoltage Rising Threshold - 2.62-V 3V3DL Undervoltage Hysteresis -150-mV 3V3DLSB Output Drive CurrentI 3V3DLSBV 5VSB = 5V3050-mA5V DUAL SWITCH CONTROLLER (V OUT4)5VDL Undervoltage Rising Threshold - 4.10-V 5VDL Undervoltage Hysteresis -120-mV 5VDLSB Output Drive Current I 5VDLSBV 5VDLSB = 4V , V 5VSB = 5V-20--40mATIMING INTERVALSActive State Assessment Past Input UV Thresholds (Note 5)425364ms Active-to-Sleep Control Input Delay -200-µs Falling UV Threshold Timeout (All Monitors)-10-µsCONTROL I/O (S3, S5, EN5, LAN, FAULT)High Level Input Threshold S3, S5, EN5, LAN -- 2.2V Low Level Input Threshold S3, S5, EN5, LAN 0.8--V Internal Pull-up Current to 5VSB S3, S5 to GND -50-µA Internal Pull-up Current to 5VSB EN5, LAN to GND -10-µA Input Leakage Current to 5VSB EN5, LAN to 5VSB --10mA FAULT Current IOH (to 5VSB)FAULT = 4.6V, 5VSB = 5V --7.5-mA FAULT Current IOL (to GND)FAULT = 0.4V, 5VSB = 5V-0.75-mATEMPERATURE MONITOR Fault-Level Threshold (Note 6)125--o C Shutdown-Level Threshold (Note 6)-155-o CNOTES:5.Guaranteed by Correlation.6.Guaranteed by Design.Electrical SpecificationsRecommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3 (Continued)PARAMETERSYMBOLTEST CONDITIONSMINTYPMAXUNITSFunctional Pin Description (Pin numbers for SOIC and QFN)3V3 (Pin 6 SOIC; Pin 3 QFN)Connect this pin to the A TX 3.3V output. This pin provides the output current for the 1V2VID pin, and is monitored for power quality.5V (Pin 7 SOIC; Pin 4 QFN)Connect this pin to the A TX 5V output. This pin is only monitored for power quality.5VSB (Pin 20 SOIC; Pin 17 QFN)Provide a very well de-coupled 5V bias supply for the IC to this pin by connecting it to the A TX 5V SB output. This pin provides all the chip’s bias as well as the base current for Q2 (see typical application diagram). The voltage at this pin is monitored for power-on reset (POR) purposes.GND (Pin 11 SOIC; Pin 8 QFN)Signal ground for the IC. All voltage levels are measured with respect to this pin.S3 and S5 (Pins 9, 10 SOIC; Pins 6, 7 QFN)These pins switch the IC’s operating state from active (S0, S1/S2) to S3 and S4/S5 sleep states. These are digital inputs featuring internal 50µA (typical) current source pull-ups to 5VSB. Internal circuitry de-glitches these pins for disturbances lasting as long as 2µs (typically). Additional circuitry blocks illegal state transitions (such as S4/S5 to S3), but does allow S3 to S4/S5. Connect S3 and S5respectively to the computer system’s SLP_S3 and SLP_S5 signals.EN5 (Pin 8 SOIC; Pin 5 QFN)This digital input selects whether the 5VDL output stays up or shuts down during the S5 Sleep Mode. It has a 10µA typical pull-up current source. A logic high (5V) or open will keep the 5VDL on during S5; a logic low (GND) will shut it off during S5. NOTE: This pin should be tied low or high (or open) on the board; it was not designed to be changed during normal operation.LAN (Pin 16 SOIC; Pin 13 QFN)This digital input selects between two modes for the V OUT1 regulator. It has a 10µA pull-up current source. A logic high (5V) or open selects the 10/100 LAN mode, where V OUT1 stays on all of the time (active and sleep modes). A logic low (GND) selects the Gigabit Ethernet mode, where V OUT1 is only on during active (S0, S1) modes. Note that thisselection is independent of the voltage selection of V OUT1 (which is determined by the external resistor divider). NOTE: This pin should be tied low or high (or open) on the board; it was not designed to be changed during normal operation.FAULT (Pin 12 SOIC; Pin 9 QFN)This digital output pin is used to report the fault condition by being pulled to 5VSB (pulled to GND if no fault). It is aCMOS digital output; an external pull-down resistor is NOT required. In case of an undervoltage on any of the controlled outputs, on any of the monitored A TX voltages (3V3 or 5V; not 12V), or in case of an overtemperature event, this pin is used to report the fault condition.PinoutsISL6505 (20 LEAD WIDE SOIC)TOP VIEWISL6505 (5X 5 QFN)TOP VIEWNOTE:The QFN bottom pad is electrically connected to the IC substrate, at GND potential. It can be left unconnected, or connected to GND; do NOT connect to another potential.1112131415161718201910987654321FB1DR13V3DLSB 3V3DL 1V2VID3V3EN55V S3S55VSB VID_PG SS LAN VID_CT 5VDL 5VDLSB DLA FAULT GND3V 3D L S B3V3DL 5V 1V2VID3V3D R 1F B 1F A U L T5VDL 5VDLSB5V S BS 3D L AEN5S 5G N DSSV I D _C T LAN VID_PG 1234567891015141312112019181716SS (Pin 17 SOIC; Pin 14 QFN)Connect this pin to a small ceramic capacitor (no less than 5nF; 0.1µF recommended). The internal soft-start (SS) current source along with the external capacitor creates a voltage ramp used to control the ramp-up of the output voltages. Pulling this pin low (to GND) with an open-drain device shuts down all the outputs as well as forces the FAULT pin low. The C SS capacitor is also used to provide a controlled voltage slew rate during active-to-sleep transitions on the 3.3V DUAL/3.3V SB output.3V3DL (Pin 4 SOIC; Pin 1 QFN)Connect this pin to the 3.3V dual/stand-by output (V OUT3). In sleep states, the voltage at this pin is regulated to 3.3V; in active states, A TX 3.3V output is delivered to this node through a fully-on NFET transistor. During all operating states, this pin is monitored for undervoltage events. This pin provides all the output current delivered by V OUT1.3V3DLSB (Pin 3 SOIC; Pin 20 QFN)Connect this pin to the base of a suitable NPN transistor. In sleep state, this transistor is used to regulate the voltage at the 3V3DL pin to 3.3V.DLA (Pin 13 SOIC; Pin 10 QFN)This pin is an open-collector output. Connect a 1kΩ resistor from this pin to the A TX 12V output. This resistor is used to pull the gates of suitable NFETs to 12V, which in active state, switch in the A TX 3.3V and 5V outputs into the3.3V DUAL/3.3V SB and 5V DUAL outputs, respectively.5VDL (Pin 15 SOIC; Pin 12 QFN)Connect this pin to the 5V DUAL output (V OUT4). In either operating state (when on), the voltage at this pin is provided through a fully-on MOSFET transistor. This pin is also monitored for undervoltage events.5VDLSB (Pin 14 SOIC; Pin 11 QFN)Connect this pin to the gate of a suitable PFET or bipolar PNP. This transistor is switched on, connecting the A TX5V SB output to the 5V DUAL regulator output during S3, and if EN5 is open or high, during S5. If EN5 is low (GND), the transistor is switched off in S5.DR1 (Pin 2 SOIC; Pin 19 QFN)This output pin drives the gate of an external NFET transistor to create V OUT1, which draws its output current from the 3V3DL pin.FB1 (Pin 1 SOIC; Pin 18 QFN)This analog input pin looks at the V OUT1 external resistor divider, and compares it to the internal reference (0.8V nominal), in order to regulate the voltage on V OUT1. This pin is also monitored for undervoltage events.1V2VID (Pin 5 SOIC; Pin 2 QFN)This pin is the output of the internal 1.2V voltage identification (VID) regulator (V OUT2). This internal regulator operates only in active states (S0, S1/S2) and is shut off during any sleep state. This regulator draws its output current from the 3V3 pin. This pin is monitored for undervoltage events.VID_PG (Pin 18 SOIC; Pin 15 QFN)This pin is the open collector output of the 1V2VID power good comparator. Connect a 10kΩ pull-up resistor from this pin to the 1V2VID output. As long as the 1V2VID output is below its PG threshold (typically 90% of final value), this pin is pulled low. Once the PG threshold is reached, the VID_CT pin starts charging its capacitor (setting the delay); when it reaches its trip point, then the VID-PG pin releases, and goes high (through the external pull-up resistor).VID_CT (Pin 19 SOIC; Pin 16 QFN)Connect a small capacitor from this pin to ground. The capacitor is used to delay the VID_PG reporting the 1V2VID has reached power good limits.DescriptionOperationThe ISL6505 controls 4 output voltages (Refer to Figures 1, 2, and 3). It is designed for microprocessor computer applications with 3.3V, 5V, 5V SB, and 12V bias input from an A TX power supply. The IC is composed of three linear controllers/regulators supplying the computer system’sV OUT1 (1.2V - 1.5V programmable), 3.3V SB and PCI slots’ 3.3V AUX power (V OUT3), the 1.2V VID circuitry power(V OUT2), a dual switch controller supplying the 5V DUAL voltage (V OUT4), as well as all the control and monitoring functions necessary for complete ACPI implementation.Initialization and PORThe ISL6505 automatically initializes upon receipt of input power. The Power-On Reset (POR) function continually monitors the 5V SB input supply voltage, initiating3.3V DUAL/3.3V SB and 1.5V SB soft-start operation shortly after exceeding POR threshold.Note that while the 5VSB pin has the main POR, both the3V3 and 5V pins (12V is not monitored) must rise above their own POR levels (typically 90%) in order to transition into the S0/S1 active state. If during normal operation either one drops below their falling trip points, the IC will go to the S5 sleep mode. When both are back above their rising thresholds, the IC will again soft-start into active state.Output Operational Truth TablesTable 1 describes the truth combinations pertaining to the 3.3V DUAL/SB and 5V DUAL dual outputs. The last two lines highlight the difference between EN5 connected high or low.Table 2 describes the truth combinations pertaining to the V OUT1 (typically between 1.2V and 1.5V) and 1V2VID outputs. The last two sets of lines highlight the difference between the two LAN pin modes (5V/open is the 10/100 LAN mode; GND is the Gigabit Ethernet mode).The internal circuitry does not allow the transition from an S4/S5 (suspend to disk/soft off) state to an S3 (suspend to RAM) state; however, it does allow the transition from S3 to S4/S5. The only ‘legal’ transitions are from an active state (S0, S1) to a sleep state (S3, S5) and vice versa.Functional Timing DiagramsFigures 4 (EN5 = low), 5 (EN5 = high), and 6 are timing diagrams, detailing the power up/down sequences of all the outputs in response to the status of the sleep-state pins (S3, S5), as well as the status of the input A TX supply . Not shown in these diagrams is the deglitching feature used to protect against false sleep state tripping. Both S3 and S5 pins are protected against noise by a 2µs filter (typically 1–4µs). This feature is useful in noisy computer environments if the control signals have to travel over significant distances. Additionally , the S3 pin features a 200µs delay in transitioning to sleep states. Once the S3 pin goes low, an internal timer is activated. At the end of the 200µs interval, if the S5 pin is low, the ISL6505 switches into S5 sleep state; if the S5 pin is high, the ISL6505 goes into S3 sleep state.The shaded column in Figures 4 and 5 highlights thedifference on the 5VDLSB and 5VDL pins for the two EN5 states.TABLE 1.5V DUAL OUTPUT (V OUT4) AND 3.3VDL/SB (V OUT3)TRUTH TABLE S5S3 3.3VDL/SB5VDL COMMENTS 11 3.3V 5V S0/S1/S2 States (Active)10 3.3V5VS301NoteMaintains Previous State00 3.3V 0V S4/S5 (EN5 = GND)03.3V 5V S4/S5 (EN5 = open/5V)NOTE:Combination Not Allowed.TABLE 2.V OUT1 AND 1V2VID (V OUT2) TRUTH TABLE S5S3V OUT11V2VID COMMENTS 11 1.5V 1.2V S0/S1/S2 States (Active)100V 0V S3 (LAN = GND)10 1.5V0VS3 (LAN = open/5V)01NoteMaintains Previous State 000V 0V S4/S5 (LAN = GND)01.5V 0V S4/S5 (LAN = open/5V)NOTE:Combination Not Allowed.FIGURE 4.5V DUAL AND 3.3V DUAL /3.3V SB TIMINGDIAGRAM; EN5 = GND5VSB 3.3V, 5V S3S55VDLSBDLA 3V3DLSB3V3DL5VDLFIGURE 5.5V DUAL AND 3.3V DUAL /3.3V SB TIMINGDIAGRAM; EN5 = 5V/OPEN5VSB 3.3V, 5V S3S55VDLSB DLA 3V3DLSB3V3DL5VDLFIGURE 6.V OUT1 AND 1.2V VID TIMING DIAGRAM (NOTETHE DEPENDENCE OF V OUT1 ON THE LOGIC STATE OF LAN PIN)5VSB 3.3V,S3S51V2VIDDLA V OUT15V, 12V (LAN=5V)V OUT1 (LAN=GND)Soft-Start into Sleep States (S3, S4/S5)The 5V SB POR function initiates the soft-start sequence. An internal 10µA current source charges an external capacitor. The error amplifiers’ reference inputs are clamped to a level proportional to the SS (soft-start) pin voltage. As the SS pin voltage slews from about 1.4V to 3.0V , the input clamp allows a rapid and controlled output voltage rise.Figures 7 (EN5 = low) and 8 (EN5 = high) show the soft-start sequence for the typical application start-up into a sleep state. At time T0 5V SB (bias) is applied to the circuit. At time T1, the 5V SB surpasses POR level. An internal fast charge circuit quickly raises the SS capacitor voltage toapproximately 1V , then the 10µA current source continues the charging.The soft-start capacitor voltage reaches approximately 1.4V at time T2, at which point the 3.3V DUAL /3.3V SB and V OUT1 error amplifiers’ reference inputs start their transition, resulting in the output voltages ramping up proportionally. The ramp-up continues until time T3 when the two voltages reach the set value. As the soft-start capacitor voltage reaches approximately 3.0V , the undervoltage monitoring circuit of this output is activated and the soft-start capacitor is quickly discharged to approximately 1.4V . Following the 3ms (typical) time-out between T3 and T4, the soft-start capacitor commences a second ramp-up designed tosmoothly bring up the remainder of the voltages required by the system. At time T5, voltages are within regulation limits, and as the SS voltage reaches 3.0V , all the remaining UV monitors are activated and the SS capacitor is quicklydischarged to 1.4V , where it remains until the next transition. As the 1.2V VID output is only on while in an active state, it does not come up, but rather waits until the main A TX outputs come up within regulation limits.Note that in Figures 7 and 8, LAN = 5V/open. If the LAN pin is connected to GND instead, then the V OUT1 output does not turn on at all in either sleep mode (S3 or S4/S5).Soft-Start into Active States (S0, S1)If both S3 and S5 are logic high at the time the 5V SB is applied, the ISL6505 will assume active state wake-up and keep off the required outputs until some time (typically 50ms) after the monitored main A TX outputs (3.3V and 5V; 12V is not monitored here) exceed the set thresholds. This time-out feature is necessary in order to ensure the main A TX outputs are stabilized. The time-out also assures smooth transitions from sleep into active when sleep states are being0V0VTIMESOFT-START (1V/DIV)OUTPUT (1V/DIV)VOLTAGES V OUT1V OUT4 (5V DUAL ) if S3T1T2T3T05V SB (1V/DIV)T5T4V OUT3 (3.3V DUAL /3.3V SB )V OUT2(1.2V VID )V OUT4 (5V DUAL ) if S5FIGURE 7.SOFT -START INTERVAL IN A SLEEP STATE; EN5= GND; LAN = 5V/OPEN0V0VSOFT-START (1V/DIV)OUTPUT (1V/DIV)VOLTAGES V OUT1V OUT4 (5V DUAL )T1T2T3T05V SB (1V/DIV)T5T4V OUT3 (3.3V DUAL /3.3V SB )V OUT2(1.2V VID )FIGURE 8.SOFT -START INTERVAL IN A SLEEP STATE;EN5 = 5V/OPEN; LAN = 5V/OPENTIMEsupported. 3.3V DUAL /3.3V SB and V OUT1 outputs will come up right after bias voltage surpasses POR level (but if LAN = GND, then V OUT1 output will not come up until the soft-start ramp, along with V OUT2; see Figure 9).During sleep-to-active state transitions from conditionswhere the 5V DUAL output is initially GND (such as S5 to S0 transition, or simple power-up sequence directly into active state), the circuit goes through a quasi soft-start, the5V DUAL output being pulled high through the body diode of the NMOS FET connected between it and the 5V A TX. Figure 9 exemplifies this start-up case. 5V SB is already present when the main A TX outputs are turned on, at time T0. As a result of +5V IN ramping up, the 5V DUAL output capacitors charge up through the body diode of Q5 (see T ypical Application). At time T1, all main A TX outputs exceed the ISL6505’s undervoltage thresholds, and the internal 50ms (typical) timer is initiated. At T2, the time-out initiates a soft-start, and the 1.2V voltage ID output is ramped-up, reaching regulation limits at time T3. Simultaneous with the beginning of this ramp-up, at time T2, the DLA pin isreleased, allowing the pull-up resistor to turn on Q3 and Q5, and bring the 5V DUAL output in regulation. Shortly after time T3, as the SS voltage reaches 3.0V , the soft-start capacitor is quickly discharged down to approximately 2.7V , where it remains until a valid sleep state request is received from the system.Fault ProtectionAll of the outputs are monitored against undervoltage events. A severe overcurrent caused by a failed load on any of the outputs, would, in turn, cause that specific output tosuddenly drop. If any of the output voltages drops below 80% (typical) of their set value, such event is reported by having the FAULT pin pulled to 5V . Additionally, exceeding the maximum current rating of an integrated regulator (output with pass transistor on-chip) can lead to output voltage drooping; if excessive, this droop can ultimately trip the undervoltage detector and send a FAULT signal to the computer system.A FAULT condition occurring on an output when controlled through an external pass transistor will only set off theFAULT flag, and it will not shut off or latch off any part of the circuit. A FAULT condition occurring on an output controlled through an internal pass transistor (1V2VID only), will set off the FAULT flag, and it will shut off the respective faulting regulator (1V2VID only). If shutdown or latch off of the entire circuit is desired in case of a fault, regardless of the cause, this can be achieved by externally pulling or latching the SS pin low. Pulling the SS pin low will also force the FAULT pin to go low and reset any internally latched-off output.Special consideration is given to the initial start-upsequence. If, following a 5V SB POR event, any of the V OUT1 or 3.3V DUAL /3.3V SB outputs is ramped up and is subject to an undervoltage event before the end of the second soft-start ramp, then the FAULT output goes high and the entire IC latches off. Latch-off condition can be reset by cycling the bias power (5V SB ). Undervoltage events on the V OUT1 and the 3.3V DUAL /3.3V SB outputs at any other times are handled according to the description found in the second paragraph under the current heading.Another condition that could set off the FAULT flag is chip overtemperature. If the ISL6505 reaches an internaltemperature of 140o C (typical), the FAULT flag is set, but the chip continues to operate until the temperature reaches 155o C (typical), when unconditional shutdown of all outputs takes place. Operation resumes only after powering down the IC (to create a 5V SB POR event) and a start-up(assuming the cause of the fault has been removed; if not, as it heats up again, it will repeat the FAULT cycle).In ISL6505 applications, loss of the active A TX output (3V3 or 5V , as detected by the on-board voltage monitor) during active state operation causes the chip to switch to S5 sleep state, in addition to reporting the input UV condition on the FAULT pin. Exiting from this forced S5 state can only be achieved by returning the faulting input voltage above its UV threshold, by resetting the chip through removal of 5V SB bias voltage, or by bringing the SS pin at a potential lower than 0.8V .FIGURE 9.SOFT -START INTERVAL IN ACTIVE STATETIMET1T2T3T0分销商库存信息:INTERSILISL6505CRZ-T ISL6505CRZ ISL6505CB ISL6505CB-T ISL6505CR ISL6505CR-T。
