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Product BriefMay 1998Ambassador TM T8105H.100/H.110 Interface and Time-Slot InterchangerFeaturess Fully backwards compatible to the T8100, T8100A, and T8102 by hardware strapping and program-ming the DEV_ID registers Complete solution for interfacing board-level circuitry to the H.100/H.110 telephony buss Includes 2 CT_NETREF pinss H.100/H.110 compliant interface; all mandatory signalss Programmable connections to any of the 4096 time slots on the H.100/H.110 buss Up to 16 local serial inputs and 16 local serial outputs, programmable for 2.048 Mbits/s,4.096 Mbits/s, and 8.192 Mbits/s operation per CHI specificationss Programmable switching between local time slots, up to 1024 connectionss Programmable switching between local time slots and H.100/H.110 bus, up to 512 connectionss Choice of frame integrity or minimum latency switching on a per-time-slot basis:— Frame integrity to ensure proper switching of wideband data— Minimum latency switching to reduce delay in voice channelss On-chip phase-locked loop (PLL) for H.100/H.110, MVIP*, or Dialogic’s† SC-bus clock operation in master or slave clock modess Serial TDM bus rate and format conversion between most standard busess Optional 8-bit parallel input and/or 8-bit parallel output for local TDM interfacess High-performance microprocessor interface:— Provides access to device configuration regis-ters and to time-slot data— Supports both Motorola‡ nonmultiplexed and Intel§ multiplexed/nonmultiplexed modess Subrate switching of nibbles, dibits, or bitss Programmable GPIO s T wo independently programmable groups of up to 12 framing signals eachs 3.3 V local I/O with 5 V tolerant inputs and TTL-compatible outputss Boundary-scan testing supports208-pin, plastic SQFPs217-pin BGA packageApplicationss Computer-telephony systemss Enhanced service platformss WAN access devicess PBXsDescriptionThe Ambassador T8105 is an H.100/H.110-compli-ant device that provides a complete interface between the H.100/H.110 bus and a wide variety of telephony interface components, processors, and other circuits. The bus interface provides all signals needed for the H.100/H.110 bus, the H-MVIP and MVIP-90 buses, or the SC-bus. Local interfaces include sixteen serial inputs and sixteen serial out-puts based on the Lucent concentration highway interface (CHI). T wo built-in time-slot interchangers are included. The first provides a local switching domain with up to 1024 programmable connections between time slots on the local CHI inputs and out-puts. The second supports up to 512 programmable connections between any time slot on the H.100/ H.110 bus and any time slot in the local switching domain. The Ambassador T8105 is configured via a microprocessor interface. This interface can also read and write time-slot and device data.*MVIP is a trademark of Natural MicroSystems Corporation.†Dialogic is a registered trademark of Dialogic Corporation.‡Motorola is a registered trademark of Motorola, Inc.§Intel is a registered trademark of Intel Corporation.2Lucent Technologies Inc.Product BriefMay 1998H.100/H.110 Interface and Time-Slot InterchangerAmbassador T8105Description (continued)Onboard clock circuitry , including a digital phase-locked loop, supports all H.100/H.110 clock modes including MVIP and SC-bus compatibility clocks. The local CHI interfaces support PCM rates of 2.048 Mbits/s,4.096 Mbits/s, and 8.192 Mbits/s. The Ambassador T8105 has internal circuitry to support either minimum latency or multi-time-slot frame integrity. Frame integrity is a requisite feature for applications that switch wideband data (ISDN H-channels). Minimum latency is advantageous in voice applications.5-6101(F)cFigure 1. Block Diagram of the Ambassador………H.100, H.110, H-MVIPINTERNAL CLOCKS ANDSTATE COUNTERS/P AND P/S CONVERTERS512LOCATION DATA SRAMTHREE 512LOCATION CONNECTIONCAMs1024LOCATION DATA MEMORY OUTPUT LOGIC AND P/S CONVERTINPUT LOGIC AND S/P CONVERT 1024LOCATION CONNECTION MEMORYTIMING AND CONTROLMICROPROCESSORINTERFACEFRAME GROUP INTERFACE LOGICFRAME GROUPSADDR[1:0]DATA[7:0]µP CONTROLSMISC. I/OCLOCKS AND REFSINTERNAL DATAINTERNAL ADDRESS AND CONTROLLOCAL OUTLOCAL INProduct BriefMay 1998H.100/H.110 Interface and Time-Slot InterchangerAmbassador T8105Application OverviewThe integration of computers and telecommunications has enabled a wide range of new communications applications and has fueled an enormous growth in communications markets. A key element in the devel-opment of computer-based communications equipment has been the addition of an auxiliary telecom bus to existing computer systems. Most manufacturers of high-capacity, computer-based telecommunications equipment have incorporated some such telecom bus in their systems. T ypically, these buses and bus inter-faces are designed to transport and switch Nx64 kbits/s low-latency telecom traffic between boards within the computer, independent of the computer’s I/O and mem-ory buses. At least a half dozen of these PC-based telecom buses emerged in the early 1990s for use within equipment based on ISA/EISA and MCA com-puters.With the advent of the H.100/H.110 bus specification by the Enterprise Computer T elephony Forum, the com-puter-telephony industry has agreed on a single tele-com bus for use with PCI and compact PCI computers.H.100/H.110 facilitates interoperation of components, thus providing maximum flexibility to equipment manu-facturers, value-added resellers, system integrators, and others building computer-based telecommunica-tions applications.Subrate switching is the ability to switch part(s) of one byte from one stream/time slot to another stream/time slot. The parts are the following:s Nibbles (4 bits)—representing a 32 kbits/s subrates Dibits (2 bits)—representing a 16 kbits/s subrates Bits—representing an 8 kbits/s subrateH.100/H.110 data transfers are always bytes. If subrate switching is used, the T8100A constructs a byte con-sisting of the subrate samples. The constructed byte may contain any combination of nibbles, dibits, or bits. In addition, individual data bits can be placed within a byte along with don’t care bits.5-6099FFigure 2. CTI Call Center Application DATABASEETHERNETCTI SERVERUSER EXTENSIONSASRFAXT1/E1ISDNPCIBUSH.100/H.110 BUSTO PSTNT1E1ISDNLucent Technologies Inc.3Lucent T echnologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. Ambassador is a trademark of Lucent T echnologies Inc.Copyright © 1998 Lucent T echnologies Inc.All Rights Reserved Printed in U.S.A.May 1998PN98-141NTNBPrinted On Recycled PaperFor additional information, contact your Microelectronics Group Account Manager or the following:INTERNET:/micro E-MAIL:docmaster@ N. AMERICA:Microelectronics Group, Lucent T echnologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, P A 181031-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)ASIA P ACIFIC:Microelectronics Group, Lucent T echnologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256Tel. (65) 778 8833, FAX (65) 777 7495CHINA:Microelectronics Group, Lucent T echnologies (China) Co., Ltd., A-F2, 23/F , Zao Fong Universe Building, 1800 Zhong Shan Xi Road,Shanghai 200233 P . R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652JAP AN:Microelectronics Group, Lucent T echnologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, T okyo 141, JapanTel. (81) 3 5421 1600, FAX (81) 3 5421 1700EUROPE:Data Requests: MICROELECTRONICS GROUP DA T ALINE: Tel. (44) 1189 324 299, FAX (44) 1189 328 148T echnical Inquiries:GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Bracknell),FRANCE: (33) 1 48 83 68 00 (Paris), SWEDEN: (46) 8 600 7070 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki), IT AL Y: (39) 2 6608131 (Milan), SP AIN: (34) 1 807 1441 (Madrid)Product BriefMay 1998H.100/H.110 Interface and Time-Slot InterchangerAmbassador T8105T8105 Selection GuideFeaturesT8100T8100A T8102T8105Subrate switching —√√√Local-to-local connections 1,0241,024—1,024Local-to-H.100 connections256256512512CT_NETREFs1222。

GENRAL DESCRIPTIONThe MSM80C85AH is a complete 8-bit parallel; central processor implemented in silicon gate C-MOS technology and compatible with MSM80C85A.It is designed with higher processing speed (max.5 MHz) and lower power consumption compared with MSM80C85A and power down mode is provided, thereby offering a high level of system integration.The MSM80C85AH uses a multiplexed address/data bus. The address is split between the 8-bit address bus and the 8-bit data bus. The on-chip address latch : of a MSM81C55-5 memory product allows a direct interface with the MSM80C85AH.FEATURES•Power down mode (HALT-HOLD)•Low Power Dissipation: 50mW(Typ)•Single + 3 to + 6 V Power Supply•–40 to + 85°C, Operating Temperature •Compatible with MSM80C85A •0.8 m s instruction Cycle (V CC = 5V)•On-Chip Clock Generator (with External Crystal)•On-Chip System Controller; Advanced Cycle Status Information Available for Large System Control•Bug operation in MSM80C85AH is fixed•Four Vectored interrupt (One is non-maskable) Plus the 8080A-compatible interrupt.•Serial, In/Serial Out Port•Decimal, Binary and Double Precision Arithmetic •Addressing Capability to 64K Bytes of Memory •TTL Compatible•40-pin Plastic DIP(DIP40-P-600-2.54): (Product name: MSM80C85AHRS)•44-pin Plastic QFJ(QFJ44-P-S650-1.27): (Product name: MSM80C85AHJS)•44-pin Plastic QFP(QFP44-P-910-0.80-2K): (Product name: MSM80C85AHGS-2K)MSM80C85AHRS/GS/JS8-Bit CMOS MICROPROCESSORE2O0009-27-X2元器件交易网FUNCTIONAL BLOCK DIAGRAMINTR INTA 5.5 6.57.5TRAP SID SODRSTX1X2CLK OUT READY RD WR ALE S0S1IO / M HOLD HLDA RESET IN RESET OUT A15 - A8Address BusAD7- ADAddress/Data BusPIN CONFIGURATION (TOP VIEW)40 pin Plastic DIPA 8HOLD HLDA CLK(OUT)RESET IN READY IO/M S 1RD WR ALE S 0A 15A 14A 13A 12A 11A 10A 9V CC 39383736353433READY IO/M S 1RD WR NC ALE TRAP RST7.5RST6.5RST5.5INTR NC INTA 18192021222324A D 4N C A D 5A D 6A D 7G N D A 865432144S I DS O DR E S E T X 2X 1N C7891011121332313029S 0A 15A 14AD 0AD 1AD 2AD 314151617A 13V C C25262728A 9A 10A 11A 1243424140H O L D H L D AC L K (O R E S E T I NTRAP RST7.5RST6.5RST5.5INTR INTA AD 0A D 4A D 5A D 6A D 7G N D V C C A 8AD 1AD 2AD 3NC A 9A 10A 11N CMSM80C85AH FUNCTIONAL PIN DEFINITIONThe following describes the function of each pin:A 0 - A 7(Input/Output)3-state A 8 - A 15(Output, 3-state)Multiplexed Address/Data Bus: Lower 8-bits of the memory address (or I/O address) appear on the bus during the first clock cycle (T state) of a machine cycle. It then becomes the data bus during the second and third clock cycles.Address Bus: The most significant 8-bits of the memory address or the 8-bits of the I/O address, 3-stated during Hold and Halt modes and during RESET.Symbol FunctionALE (Output)Address Latch Enable: It occurs during the first clock state of a machine cycle and enables address to get latched into the on-chip latch peripherals. The falling edge of ALE is set to guarantee setup and hold times for the address information. The falling edge ALE can also be used to strobe the status information ALE is never 3-state.S 0 , S 1 , IO/M (Output)Machine cycle status:IO/M S 1 S 0 States S 1 can be used as an advanced R/W status. IO/M , S 0 and S 1 become valid at the beginning ofa machine cycle and remain stable throughout the cycle. The falling edge of ALE may be used to latch the state of these lines.RD(Output, 3-state)READ control: A low level on RD indicates the selected memory or I/O device is to be read thatthe Data Bus is available for the data transfer, 3-stated during Hold and Halt modes and during RESET.WR(Output, 3-state)WRITE control: A low level on WR indicates the data on the Data Bus is to be written into the selected memory or I/O location. Data is set up at the trailing edge of WR , 3-stated during Hold and Halt modes and during RESET.READY (Input)If READY is high during a read or write cycle, it indicates that the memory or peripheral is ready to send or receive data. If READY is low, the cpu will wait an integral number of clock cycles for READY to go high before completing the read or write cycle READY must conform to specified setup and hold times.HOLD (Input)HLDA (Output)HOLD ACKNOWLEDGE: Indicates that the cpu has received the HOLD request and that it will relinquish the bus in the next clock cycle. HLDA goes low after the Hold request is removed. The cpu takes the bus one half clock cycle after HLDA goes low.HOLD indicates that another master is requesting the use of the address and data buses.The cpu, upon receiving the hold request, will relinquish the use of the bus as soon as the completion of the current bus transfer. Internal processing can continue. The processor can regain the bus only after the HOLD is removed. When the HOLD is acknowledged, the Address, Data, RD , WR , and IO/M lines are 3-stated. And status of power down is controlled by HOLD.INTR (Output)INTERRUPT REQUEST: Is used as a general purpose interrupt. It is sampled on during the next to the last clock cycle of an instruction and during Hold and Halt states. If it is active, the Program Counter (PC) will be inhibited from incrementing and an INTA will be issued. During this cycle a RESTART or CALL instruction can be inserted to jump to the interrupt service routine. The INTR is enabled and disabled by software. It is disabled by Reset and immediately after an interrupt is accepted. Power down mode is reset by INTR.INTA (Output)INTERRUPT ACKNOWLEDGE: Is used instead of (and has the same timing as) RD during the instruction cycle after an INTR is accepted.RST 5.5RST 6.5RST 7.5(Input)RESTART INTERRUPTS: These three inputs have the same timing as INTR except they cause an internal RESTART to be automatically inserted.The priority of these interrupts is ordered as shown in Table 1. These interrupts have a higher priority than INTR. In addition, they may be individually masked out using the SIM instruction. Power down mode is reset by these interrupts.TRAP (Input)Trap interrupt is a nonmaskable RESTART interrupt. It is recognized at the same timing as INTR or RST 5.5 - 7.5. It is unaffected by any mask or Interrupt Disable. It has the highest priority of any interrupt. (See Table 1.) Power down mode is reset by input of TRAP.001100101110101Memory write Memory read I/O write I/O readOpcode fetchIO/M S 1 S 0 States 1...10¥¥10¥¥Interrupt Acknowledge Halt = 3-stateHold (high impedance)Reset ¥ = unspecifiedName Address Branched To (1)When Interrupt OccursType TriggerRST 7.53CH 34H Rising edge (latched).High level unitl sampled.RST 6.5RST 5.52CH (2)High level until sampled.High level until sampled.INTRTRAP Priority 2345124H Rising edge and high level unit sampled.Table 1 Interrupt Priority, Restart Address, and SensitivityNotes:(1)The processor pushes the PC on the stack before branching to the indicatedaddress.(2)The address branched to depends on the instruction provided to the cpuwhen the interrupt is acknowledged.RESET IN (Input)Sets the Program Counter to zero and resets the Interrupt Enable and HLDA flip-flops and release power down mode. The data and address buses and the control lines are 3-stated during RESET and because of the asynchronous nature of RESET IN, the processor's internal registers and flags may be altered by RESET with unpredictable results. RESET IN is a Schmitt-triggered input, allowing connection to an R-C network for power-on RESET delay. The cpu is held in the reset condition as long as RESET IN is applied.Symbol FunctionRESET OUT (Output)Indicated cpu is being reset. Can be used as a system reset. The signal is synchronized to the processor clock and lasts an integral number of clock periods.X 1, X 2(Input)X 1 and X 2 are connected to a crystal to drive the internal clock generator. X 1 can also be an external clock input from a logic gate. The input frequency is divided by 2 to give the processor's internal operating frequency.SID (Input)Serial input data line. The data on this line is loaded into accumulator bit 7 whenever a RIM instruction is executed.SOD (Output)Serial output data line. The output SOD is set or reset as specified by the SIM instruction.V CC + 5 Volt supply GNDGround Reference.CLK (Output)Clock Output for use as a system clock. The period of CLK is twice the X 1, X 2 input period.FUNCTIONAL DESCRIPTIONThe MSM80C85AH is a complete 8-bit parallel central processor. It is designed with silicon gate C-MOS technology and requires a single +5 volt supply. Its basic clock speed is 5 MHz, thus improving on the present MSM80C85A's performance with higher system speed and power down mode. Also it is designed to fit into a minimum system of two IC's: The CPU (MSM80C85AH), and a RAM/IO (MSM81C55-5)The MSM80C85AH has twelve addressable 8-bit register pairs. Six others can be used interchangeably as 8-bit registers or 16-bit register pairs. The MSM80C85AH register set is as follows:PC 16-bit address 8-bit ¥ 6 or 16-bits ¥ 3BC, DE, HL SP 16-bit address 5 flags (8-bit space)Flags or FProgram CounterACC or A 8-bits Accumulator Mnemonic ContentsRegisterGeneral-Purpose Registers; data pointer (HL)Stack Pointer Flag RegisterThe MSM80C85AH uses a multiplexed Data Bus. The address is spilt between the higher 8-bit Address Bus and the lower 8-bit Address/Data Bus. During the first T state (clock cycle) of a machine cycle the low order address is sent out on the Address/Data Bus. These lower 8-bits may be latched externally by the Address Latch Enable signal (ALE). During the rest of the machine cycle the data bus is used for mamory or I/O data.The MSM80C85AH provides RD , WR , S 0, S 1, and IO/M signals for bus control. An Interrupt Acknowledge signal (INTA ) is also provided. Hold and all Interrupts are synchronized with the processor's internal clock. The MSM80C85AH also provides Serial Input Data (SID) and Serial Output Data (SOD) lines for a simple serial interface.In addition to these features, the MSM80C85AH has three maskable, vector interrupt pins, one nonmaskable TRAP interrupt and power down mode with HALT and HOLD.INTERRUPT AND SERIAL I/OThe MSM80C85AH has 5 interrupt inputs: INTR, RST 5.5 RST 6.5, RST 7.5, and TRAP. INTR is identical in function to the 8080A INT. Each of the three RESTART inputs, 5.5, 6.5, and 7.5, has a programmable mask. TRAP is also a RESTART interrupt but it is nonmaskable.The three maskable interrupts cause the internal execution of RESTART ( saving the program counter in the stack branching to the RESTART address) it the interrupts are enable and if the interrupt mask is not set. The nonmaskable TRAP causes the internal execution of a RESTART vector independent of the state of the interrupt enable or masks. (See Table 1.)There are two different types of inputs in the restart interrupt. RST 5.5 and RST 6.5 are high level-sensitive like INTR (and INT on the 8080A) and are recognized with the same timing as INTR. RST 7.5 is rising edge-sensitive.For RST 7.5, only a pulse is required to set an internal flip-flop which generates the internal interrupt request. The RST 7.5 request flip-flop remains set until the request is serviced. Then it is reset automatically, This flip-flop may also be reset by using the SIM instruction or by issuing a RESET␣IN to the MSM80C85AH. The RST 7.5 internal flip-flop will be set by a pulse on the RST 7.5 pin even when the RST 7.5 interrupt is masked out.The interrupts are arranged in a flixed priority that determines which interrupt is to be recognized if more than one is pending, as follows: TRAP-highest priority, RST 7.5, RST 6.5, RST 5.5, INTR-lowest priority. This priority scheme does not take into account the priority of a routine that was started by a higher priority interrupt. RST 5.5 can interrupt an RST 7.5 routine if the interrupt are re-enabled before the end of the RST 7.5 routine.The TRAP interrupt is useful for catastrophic evens such as power failure or bus error. The TRAP input is recognized just as any other interrupt but has the highest priority. It is not affected by any flag or mask. The TRAP input is both edge and level sensitive. The TRAP input must go high and remain high until it is acknowledged. It will not be recognized again until it goes low, then high again. This avoids any false triggering due to noise or logic glitches. Figure 3 illustrates the TRAP interrupt request circuitry within the MSM80C85AH. Note that the servicing of any interrupt (TRAP, RST 7.5, RST 6.5, RST 5.5,INTR) disables all future interrupts (except TRAPs) until an El instruction is executed.The TRAP interrupt is special in that it disables interrupts, but preserves the previous interrupt enable status. Performing the first RIM instruction following a TRAP interrupt allows you to determine whether interrupts were enabled or disabled prior to the TRAP. All subsequent RIM instructions provide current interrupt enable status. Performing a RIM instruction following INTR or RST 5.5-7.5 will provide current interrupt Enable status, revealing that Interrupts are disabled.The serial I/O system is also controlled by the RIM and SIM instructions. SID is read by RIM, and SIM sets the SOD data.AcknowledgeFigure 3 Trap and RESET IN CircuitDRIVING THE X 1 AND X 2 INPUTSYou may drive the clock inputs of the MSM80C85AH with a crystal, or an external clock source.The driving frequency must be at least 1 MHz, and must be twice the desired internal clock frequency; hence, the MSM80C85AH is operated with a 6 MHz crystal (for 3 MHz clock). If a crystal is used, it must have the following characteristics:Parallel resonance at twice the clock frequency desired C L (load capacitance) £ 30 pF C S (shunt capacitance) £ 7 pFR S (equivalent shunt resistance) £ 75 ohms Drive level: 10 mWFrequency tolerance: ±0.05% (suggested)Note the use of the capacitors between X 1, X 2 and ground. These capacitors are required to assure oscillator startup at the correct frequency.Figure 4 shows the recommended clock driver circuits. Note in B that a pull-up resistor is required to assure that the high level voltage of the input is at least 4 V.For driving frequencies up to and including 6 MHz you may supply the driving signal to X, and leave X 2 open-circuited (Figure 4B). To prevent self-oscillation of the MSM80C85AH, be sure that X 2 is not coupled back to X 1 through the driving circuit.Note:Since the constant values may vary depending on oscillator, consult the manufacturer of the oscillator used when designing a circuit.Figure 4 Clock Driver Circuits* X 2 Left Floating33 pF Capacitor required for crystal frequency 10 to 6.25 MHz 50 pF Capacitor required for crystal frequency 6.25 to 4 MHz 100 pF Capacitor required for crystal frequency <4 MHzA. Quartz Crystal Clock DriverB. 1 - 10 MHz Input Frequency External Clock Drive CircuitBASIC SYSTEM TIMINGThe MSM80C85AH has a multiplexed Data Bus. ALE is used as a strobe to sample the lower 8-bits of address on the Data Bus. Figure 5 shows an instruction fetch, memory read and I/O write cycle (as would occur during processing of the OUT instruction). Note that during the I/ O write and read cycle that the I/O port address is copied on both the upper and lower half of the address.There are seven possible types of machine cycles. Which of these seven takes place is defined by the status of the three status lines (IO/M, S1, S0) and the three control signals (RD, WR,and INTA). (See Table 2.) The status line can be used as advanced controls (for device selection, for example), since they become active at the T1 state, at the outset of each machine cycle. Control lines RD and WR become active later, at the time when the transfer of data is to take place, so are used as command lines.A machine cycle normally consists of three T states, with the exception of OPCODE FETCH, which normally has either four or six T states (unless WAIT or HOLD states are forced by the receipt of READY or HOLD inputs). Any T state must be one of ten possible states, shown in Table 3.Table 2 MSM80C85AH Machine Cycle ChartTable 3 MSM80C85AH Machine State Chart0= Logic "0"1= Logic "1"TS = High Impedance ¥= UnspecifiedNotes:(1) ALE not generated during 2nd and 3rd machine cycles of DAD instruction.(2) IO/M = 1 during T 4 - T 6 of INA machine cycle.A AD IO/Figure 5 MSM80C85AH Basic System TimingPOWER DOWN ModeThe MSM80C85AH is compatible with the MSM80C85A in function and POWER DOWN mode. This reduces power consumption further.There are two methods available for starting this POWER DOWN mode. One is through software control by using the HALT command and the other is under hardware control by using the pin HOLD. This mode is released by the HOLD, RESET, and interrupt pins (TRAP, RST7.5, RST6.5 RST5.5, or INTR). (See Table 4.)Since the sequence of HALT, HOLD, RESET, and INTERRUPT is compatible with MSM80C85A, every the POWER DOWN mode can be used with no special attention.Start by means of Halt command Start by means of HOLD pin Released by using pins RESET and INTERRUPT (not by pin HOLD) Released by using RESET and HOLD pins (not by interrupt pins)Table 4 POWER DOWN Mode Releasing Method(1) Start by means of HALT command (See Figures 6 and 7.)The POWER DOWN mode can be started by executing the HALT command.At this time, the system is put into the HOLD status and therefore the POWER DOWN mode cannot be released even when the HOLD is released later.In this case, the POWER DOWN mode can be released by means of the RESET or interrupt.(2) Start by means of HOLD pin (See Figure 8.)During the execution of commands other than the HALT, the POWER DOWN mode is started when the system is put into HOLD status by means of the HOLD pin.Since no interrupt works during the execution of the HOLD, the POWER DOWN mode cannot be released by means of interrupt pins. In this case, the POWER DOWN mode can be released either by means of the RESET pin or by releasing the HOLD status by means of HOLD pin.CLK (OUT)ALEAD 0-7CPU MODE RESET INFigure 6 Started by HALT and Released by RESET INCLK (OUT)ALEHOLD CPU MODEHLDAFigure 8 Started and Released by HOLDCLK (OUT)ALECPU MODERST5.5Figure 7 Started by HALT and Released by RST5.5ABSOLUTE MAXIMUM RATINGS–55 - +150MSM80C85AHRS Power Supply Voltage V CC –0.5 - 7V Input Voltage V IN –0.5 - V CC +0.5V Output Voltage V OUT –0.5 - V CC +0.5V Storage Temperature T STG °CPower DissipationP D0.7WParameter Units Symbol With respect to GND—Ta = 25°CCondition LimitsMSM80C85AHGS MSM80C85AHJS1.01.0OPERATING RANGELimits Power Supply Voltage V CC 3 - 6V Operating TemperatureT OP–40 - +85°CParameterUnit Symbol RECOMMENDED OPERATING CONDITIONSDC CHARACTERISTICS"L"V ILR —–0.3+0.8Typ.Power Supply Voltage V CC 5V T OP +25"L" Input Voltage V IL —"H" Output Voltage V IH —Min.4.5–40–0.32.2Max.5.5+85+0.8V CC +0.3ParameterUnit Symbol °C V V Operating Temperature V V IHR—3.0V CC +0.3VRESET IN Input Voltage "H"RESET IN Input VoltageTyp.Max."L" Output Voltage V OL —0.4V "H" Output Voltage V OH ——V ——V Parameter Unit Symbol Min.—3.0V CC - 0.4I OL = 2.5 mA I OH = –2.5 mA I OH = –100 m A ConditionsV CC = 4.5 V - 5.5 V Ta = –40°C - +85°C Input Leak Current I LI —10m A Output Leak CurrentI LO—10m A –10–100 £ V IN £ V CC 0 £ V OUT £ V CC T cyc = 200 ns C L = 0 pF at reset Operating SupplyCurrentI CC1020mA 510mA——T cyc = 200 nsC L = 0 pF at power down modeAC CHARACTERISTICSParameter Symbol Condition Min.Max.UnitCLY Cycle Period t CYCt CYC=200 nsCL=150 pF 2002000nsCLY Low Time t140—ns CLY High Time t270—ns CLY Rise and Fall Time t r, t f—30nsX1 Rising to CLK Rising t XKR25120nsX1 Rising to CKK Falling t XKF30150nsA8~15 Valid to Leading Edge of Control (1)t AC115—ns AD0~7 Valid to Leading Edge of Control t ACL115—ns AD0~15 Valid Data in t AD—350ns Address Float After Leading Edge of RD INTA t AFR—0nsA8~15 Valid Before Trailing Edge of ALE (1)t AL50—ns AD0~7 Valid Before Trailing Edge of ALE t ALL50—ns READY Valid from Address Valid t ARY—100ns Address (A8~15) Valid After Control t CA60—ns Width of Control Law (RD, WR, INTA)t CC230—ns Trailing Edge of Control to Leading Edges of ALE t CL25—ns Data Valid to Trailing Edge of WR t DW230—ns HLDA to Bus Enable t HABE—150ns Bus Float After HLDA t HABF—150ns HLDA Valid to Trailing Edge of CLK t HACK40—ns HOLD Hold Time t HDH0—ns HOLD Step Up Time to Trailing Edge of CLK t HDS120—ns INTR Hold Time t INH0—ns INTR, RST and TRAP Setup Time to Falling Edge of CLK t INS150—ns Address Hold Time After ALE t LA50—ns Trailing Edge of ALE to Leading Edge of Control t LC60—ns ALE Low During CLK High t LCK50—ns ALE to Valid Data During Read t LDR—270ns ALE to Valid Data During Write t LDW—140ns ALE Width t LL80—ns ALE to READY Stable t LRY—30ns Trailing Edge of RD to Re-enabling of Address t RAE90—ns RD (or INTA) to Valid Data t RD—150ns Control Trailing Edge to Leading Edge of Next Control t RV220—ns Data Hold Time After RD INTA (7)t RDH0—ns READY Hold Time t RYH0—ns READY Setup Time to Leading Edge of CLK t RYS100—ns Data Valid After Trailing Edge of WR t WD60—ns LEADING Edge of WR to Data Vaild t WDL—20ns(Ta = –40°C ~ 85°C, V CC = 4.5 V ~ 5.5 V)Notes:(1)A 8 - A 15 address Specs apply to IO/M , S 0 and S 1.(2)Test condition: t CYC =200 ns C L =150 pF(3)For all output timing where C L =150 pF use the following correction factors:25 pF £ C L < 150 pF : –0.10ns/pF 150 pF < C L £ 200 pF : +0.30ns/pF(4)Output timings are measured with purely capacitive load.(5)All timings are measured to output voltage V L =0.8 V, V H =2.2 V, and 1.5 Vwith 10 ns rise and fall time on inputs.(6)To calculate timing specifications at other values of t CYC use Table 7.(7)Data hold time is guaranteed under all loading conditions.2.40.45Input Waveform for A.C. Tests:(1/2)T - 50t AL Min (Ta = -40°C - +85°C, V CC = 4.5 V - 5.5 V, C L = 150 pF)(1/2)T - 50t LA Min (1/2)T - 20t LL Min (1/2)T - 50t LCK Min (1/2)T - 40t LC Min (5/2+N)T - 150t AD Max (3/2+N)T - 150t RD Max (1/2)T - 10t RAE Min (1/2)T - 40t CA Min (3/2+N)T -70t DW Min (1/2)T - 40t WD Min (3/2+N)T - 70t CC Min (1/2)T - 75t CL Min (3/2)T - 200t ARY Max (1/2)T - 60t HACK Min (1/2)T + 50t HABF Max (1/2)T + 50(2/2)T - 85t HABE Max t AC Min (1/2)T - 60t 1Min (1/2)T - 30t 2Min (3/2)T - 80t RV Min t LDRMax——————————————————————MSM80C85AH Table 7 Bus Timing Specification as a T CYC DependentNote:N is equal to the total WAIT states.T = t CYC(2+N)T -130X1 INPUTCLKOUTPUTFigure 6 Clock Timing Waveform READ OPERATIONCLKA8-A15 AD0-AD7ALE RD / INTA T1T2T3T1WRITE OPERATIONCLK T1A8-A15AD0-AD7ALEWRT2T3T1CLKA 8~A 15AD 0~AD 7ALERD / INTAREADYT 1T 2T WAIT T 3T 1Note: READY must remain stable during setup and hold times.Figure 7 MSM80C85AH Bus Timing, With and Without WaitRead operation with Wait Cycle (Typical)–same READY timing applies to WRITE operationCLK HOLDHLDA BUSFigure 8 MSM80C85AH Hold TimingHOLD OPERATIONNOTE: (1) IO/M is also floating during this time.Figure 9 MSM80C85AH Interrupt and Hold TimingMOVE, LOAD, AND STORE MOVr1 r2MOV M r MOV r M MVI r MVI M LXI B LXI D LXI H LXI SP STAX B STAX D LDAX B LDAX D STA LDA SHLD LHLD XCHG MnemonicDescriptionInstruction Code (1)Clock (2)Cycles000000000000000001111000000000000001D 1D D 10011000011111D 1D D 10101010111000D 0D D 00000001101011S S 1110000000000000S S 1110000111111111S S 0001111000000001D 7D 6D 5D 4D 3D 2D 1D 0477710101010107777131316164Move register to register Move register to memory Move memory to register Move immediate register Move immediate memory Load immediate register Pair B & C Load immediate register Pair D & E Load immediate register Pair H & L Load immediate stack pointer Store A indirect Store A indirect Load A indirect Load A indirect Store A direct Load A direct Store H & L direct Load H & L direct Exchange D & E H & L registers STACK OPS PUSH B PUSH D PUSH H PUSH PSW POP B POP D POP H POP PSW XTHL SPHL 111111111111111111110011001111010101010100000000011111000000000000001011111111111212121210101010166Push register Pair B & C on stack Push register Pair D & E on stack Push register Pair H & L on stack Push A and Flags on stackPop register Pair B & C off stack Pop register Pair D & E off stack Pop register Pair H & L off stack Pop A and Flags off stack Exchange top of stack H & L H & L to stack pointer JUMP JMP JC JNC JZ JNZ JP JM JPE JPO PCHL 11111111111111111111000001111101100110000101001101000000000011111111101000000001107/107/107/107/107/107/107/107/106Jump unconditional Jump on carry Jump on no carry Jump on zero Jump on no zero Jump on positive Jump on minus Jump on parity even Jump on parity oddH & L to program counter CALL CALL CC CNC CZ CNZ CP CM CPE CPO111111111111111111000001111011001100110100110111111111000000000100000000189/189/189/189/189/189/189/189/18Call unconditional Call on carry Call on no carry Call on zero Call on no zero Call on positive Call on minus Call on parity even Call on parity oddTable 8 Instruction Set SummaryRETURN RET RC RNC RZ RNZ RP RM RPE RPO Mnemonic DescriptionInstruction Code (1)Clock (2)Cycles 111111111111111111000001111011001100110100110000000000000000000100000000D 7D 6D 5D 4D 3D 2D 1D 0106/126/126/126/126/126/126/126/12ReturnReturn on carry Return on no carry Return on zero Return on no zero Return on positive Return on minus Return on parity even Return on parity odd RESTART RST11A A A 11112Restart INPUT/OUTPUT IN OUT11110011100011111010Input OutputINCREMENT AND DECREMENT INR r DCR r INR M DCR M INX B INX D INX H INX SP DCX B DCX D DCX H DCX SP 000000000000000000000000D D 1100110011D D 1101010101D D 000000111111110000000000001111111101011111111144101066666666Increment register Decrement register Increment memory Decrement memory Increment B & C registers Increment D & E registers Increment H & L registers Increment stack pointer Decrement B & C Decrement D & E Decrement H & L Decrement stack pointer ADD ADD r ADC r ADD M ADC M ADI ACI DAD B DAD D DAD H DAD SP 11111100000000110000000000001100000001010101011111S S 11110000S S 11110000S S 0000111144777710101010Add register to AAdd register to A with carry Add memory to AAdd memory to A with carry Add immediate to AAdd immediate to A with carry Add B & C to H & L Add D & E to H & L Add H & L to H & LAdd stack pointer to H & LSUBTRACT SUB r SBB r SUB M SBB M SUI SBI111111000011000000111111010101S S 1111S S 1111S S 0000447777Subtract register from ASubtract register from A with borrow Subtract memory from ASubtract memory from A with borrow Subtract immediate from ASubtract immediate from A with borrowTable 8 Instruction Set Summary cont'd。

1.Features Array•80C52 Compatible–8051 pin and instruction compatible–Four 8-bit I/O ports–Three 16-bit timer/counters–256 bytes scratchpad RAM•High-Speed Architecture–40 MHz @ 5V, 30MHz @ 3V–X2 Speed Improvement capability (6 clocks/machine cycle)–30 MHz @ 5V, 20 MHz @ 3V (Equivalent to–60 MHz @ 5V, 40 MHz @ 3V)•Dual Data Pointer•On-chip ROM/EPROM (16K-bytes, 32K-bytes, 64K-bytes)•On-chip eXpanded RAM (XRAM) (256 or 768 bytes)•Programmable Clock Out and Up/Down Timer/Counter 2•Programmable Counter Array with–High Speed Output,–Compare / Capture,–Pulse Width Modulator,–Watchdog Timer Capabilities•Hardware Watchdog Timer (One-time enabled with Reset-Out)• 2 extra 8-bit I/O ports available on RD2 with high pin count packages •Asynchronous port reset•Interrupt Structure with–7 Interrupt sources,–4 level priority interrupt system•Full duplex Enhanced UART–Framing error detection–Automatic address recognition•Low EMI (inhibit ALE)•Power Control modes–Idle mode–Power-down mode–Power-off Flag•Once mode (On-chip Emulation)•Power supply: 4.5-5V, 2.7-5.5V•Temperature ranges: Commercial (0 to 70o C) and Industrial (-40 to 85o C)•Packages: PDIL40, PLCC44, VQFP44 1.4, PLCC68, VQFP64 1.42.DescriptionAtmel TS8xC51Rx2 is a high performance CMOS ROM, OTP, EPROM and ROMless versions of the 80C51 CMOS single chip 8-bit microcontroller.The TS8xC51Rx2 retains all features of the 80C51 with extended ROM/EPROM capacity (16/32/64 Kbytes), 256 bytes of internal RAM, a 7-source , 4-level interrupt system, an on-chip oscilator and three timer/counters.In addition, the TS80C51Rx2 has a Programmable Counter Array, an XRAM of 256 or768 bytes, a Hardware Watchdog Timer, a more versatile serial channel that facili-24188E–8051–08/06AT/TS8xC51Rx2tates multiprocessor communication (EUART) and an X2 speed improvement mechanism.The fully static design of the TS80C51Rx2 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data.The TS80C51Rx2 has 2 software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode the CPU is frozen while the timers, the serial port and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative.PDIL40PLCC44VQFP44 1.4ROM (bytes)EPROM (bytes)XRAM (bytes)TOTAL RAM (bytes)I/O TS80C51RA2TS80C51RD2000025676851210243232TS83C51RB2TS83C51RC2TS83C51RD216k 32k 64k 0002562567685125121024323232TS87C51RB2TS87C51RC2TS87C51RD200016k 32k 64k2562567685125121024323232PLCC68VQFP64 1.4ROM (bytes)EPROM (bytes)XRAM (bytes)TOTAL RAM (bytes)I/O TS80C51RD200768102448TS83C51RD264k 0768102448TS87C51RD264k76810244834188E–8051–08/06AT/TS8xC51Rx23.Block DiagramT 0T 1R x DT x DI N T 1I N T 0P P P P R E S E TP C A E C IV s sV c c(1): Alternate function of Port 1(3): Alternate function of Port 32E X 2P P (2): Only available on high pin count packages44188E–8051–08/06AT/TS8xC51Rx24.SFR MappingThe Special Function Registers (SFRs) of the TS80C51Rx2 fall into the following categories:•C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1•I/O port registers: P0, P1, P2, P3, P4, P5•Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H•Serial I/O port registers: SADDR, SADEN, SBUF, SCON •Power and clock control registers: PCON•HDW Watchdog Timer Reset: WDTRST, WDTPRG•PCA registers: CL, CH, CCAPiL, CCAPiH, CCON, CMOD, CCAPMi •Interrupt system registers: IE, IP, IPH •Others: AUXR, CKCON54188E–8051–08/06AT/TS8xC51Rx2Table 4-1.All SFRs with their address and their reset valueBitaddressable Non Bit addressable 0/81/9 2/A 3/B 4/C 5/D 6/E 7/FF8hCH 0000 0000CCAP0H XXXX XXXXCCAP1H XXXX XXXXCCAPL2H XXXX XXXXCCAPL3H XXXX XXXXCCAPL4H XXXX XXXXFFhF0h B0000 0000F7hE8h P5 bitaddressable 1111 1111CL 0000 0000CCAP0L XXXX XXXXCCAP1L XXXX XXXXCCAPL2L XXXX XXXXCCAPL3L XXXX XXXXCCAPL4L XXXX XXXXEFhE0hACC0000 0000E7hD8h CCON 00X0 0000CMOD 00XX X000CCAPM0X000 0000CCAPM1X000 0000CCAPM2X000 0000CCAPM3X000 0000CCAPM4X000 0000DFhD0h PSW0000 0000D7hC8h T2CON 0000 0000T2MOD XXXX XX00RCAP2L 0000 0000RCAP2H 0000 0000TL20000 0000TH20000 0000CFhC0h P4 bitaddressable 1111 1111P5 byte addressable 1111 1111C7hB8hIP X000 000SADEN 0000 0000BFhB0h P31111 1111IPHX000 0000B7hA8h IE 0000 0000SADDR 0000 0000AFhA0h P21111 1111AUXR1XXXX0XX0WDTRST XXXX XXXXWDTPRG XXXX X000A7h98h SCON 0000 0000SBUF XXXX XXXX 9Fh90h P11111 111197h88h TCON 0000 0000TMOD 0000 0000TL00000 0000TL10000 0000TH00000 0000TH10000 0000AUXRXXXXXX00CKCON XXXX XXX08Fh80h P01111 1111SP0000 0111DPL0000 0000DPH0000 0000PCON 00X1 000087h0/81/92/A3/B4/C5/D6/E7/Freserved64188E–8051–08/06AT/TS8xC51Rx25.Pin ConfigurationP1.7RST P3.0/RxD P3.1/TxD P1.5P1.6P3.2/INT0P3.3/INT1P3.4/T0P3.5/T1P3.6/WR P3.7/RD XTAL2XTAL1VSS P1.0 / T2P1.2P1.1 / T2EX P 3.P 3X P P P 2.P 2.P 2.*NIC: No Internal Connection74188E–8051–08/06AT/TS8xC51Rx2P5.5P0.3/AD3P0.2/AD2P5.6P0.1/AD1P0.0/AD0P5.7VCC NIC P1.0/T2P4.0P1.1/T2EXP1.2P1.3P4.1P1.4P4.2N I P 1.R S N IN I NI P3.0/R x N I N I N I P 3.1/T x D P 3.3/I N T P5.0P2.4/A12P2.3/A11P4.7P2.2/A10P2.1/A9P2.0/A8VSS P4.6P4.5XTAL1XTAL2NIC P 1.P 1.P 3.4/T P3.5/T P4.4P3.6/WR P4.3P3.7/RD P 3.2/I N T 0VSS P2.3/A11P4.7P2.2/A10P2.1/A9P2.0/A8P4.6P4.5NIC XTAL1XTAL2P3.7/RD P4.4P4.3P2.4/A12P3.6/WR P1.0/T2P0.3/AD3P0.2/AD2P5.6P0.1/AD1P0.0/AD0P5.7VCC VSS P4.0P1.1/T2EXP1.2P1.3P4.1P1.4P5.5N I C P 3.4/T 0P 3.2/I N T 0P 3.1/T x D N I C N I C P 3.0/R x D N I C N I C R S T P 1.7P 1.6P 1.5P 4.2P3.5/T 1P3.3/I N T 1NIC: No InternalConnection84188E–8051–08/06AT/TS8xC51Rx2Mnemonic Pin NumberType Name And Function DIL LCC VQFP 1.4V SS 202216I Ground: 0V referenceVss1139I Optional Ground: Contact the Sales Office for ground connection.V CC404438I Power Supply: This is the power supply voltage for normal, idle and power-down operationP0.0-P0.739-3243-3637-30I/OPort 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. Port 0 pins must be polarized to Vcc or Vss in order to prevent any parasitic current consumption. Port 0 is also the multiplexed low-order address and data bus during access to external program and data memory. In this application, it uses strong internal pull-up when emitting 1s. Port 0 also inputs the code bytes during EPROM programming. External pull-ups are required during program verification during which P0 outputs the code bytes.P1.0-P1.7 1-82-940-441-3I/OPort 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current because of the internal pull-ups. Port 1 also receives the low-order address byte during memory programming and verification.Alternate functions for Port 1 include:1240I/O T2 (P1.0): Timer/Counter 2 external count input/Clockout 2341I T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control 3442I ECI (P1.2): External Clock for the PCA4543I/O CEX0 (P1.3): Capture/Compare External I/O for PCA module 05644I/O CEX1 (P1.4): Capture/Compare External I/O for PCA module 16745I/O CEX0 (P1.5): Capture/Compare External I/O for PCA module 27846I/O CEX0 (P1.6): Capture/Compare External I/O for PCA module 38947I/O CEX0 (P1.7): Capture/Compare External I/O for PCA module 4P2.0-P2.721-2824-3118-25I/OPort 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR).In this application, it uses strong internal pull-upsemitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR. Some Port 2 pins (P2.0 to P2.5) receive the high order address bits during EPROM programming and verification:P3.0-P3.7 10-1711,13-195,7-13I/OPort 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current because of the internal pull-ups. Some Port 3 pins (P3.4 to P3.5) receive the high order address bits during EPROM programming and verification.Port 3 also serves the special features of the 80C51 family, as listed below.10115I RXD (P3.0): Serial input port 11137OTXD (P3.1): Serial output port94188E–8051–08/06AT/TS8xC51Rx25.1Pin Description for 64/68 pin PackagesPort 4 and Port 5 are 8-bit bidirectional I/O ports with internal pull-ups. Pins that have 1s written to them are pulled high by the internal pull ups and can be used as inputs.As inputs, pins that are externally pulled low will source current because of the internal pull-ups.Refer to the previous pin description for other pins.Table 5-1.64/68 Pin Packages Configuration12148I INT0 (P3.2): External interrupt 013159I INT1 (P3.3): External interrupt 1141610I T0 (P3.4): Timer 0 external input 151711I T1 (P3.5): Timer 1 external input161812O WR (P3.6): External data memory write strobe 171913O RD (P3.7): External data memory read strobeReset9104IReset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to V SS permits a power-on reset using only an external capacitor to V CC. If the hardware watchdog reaches its time-out, the reset pin becomes an output during the time the internal reset is activated.ALE/PROG 303327O (I)Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG) during EPROM programming. ALE can be disabled by setting SFR’s AUXR.0 bit. With this bit set, ALE will be inactive during internal fetches.PSEN 293226OProgram Store ENable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory.EA/V PP313529IExternal Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H and 3FFFH (RB) or 7FFFH (RC), or FFFFH (RD). If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than 3FFFH (RB) or 7FFFH (RC) EA must be held low for ROMless devices. This pin also receives the 12.75V programming supply voltage (V PP ) during EPROM programming. If security level 1 is programmed, EA will be internally latched on Reset.XTAL1192115ICrystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits.XTAL2182014OCrystal 2: Output from the inverting oscillator amplifierMnemonicPin NumberType Name And FunctionDIL LCC VQFP 1.4PinPLCC68SQUARE VQFP64 1.4VSS 519/40VCC178104188E–8051–08/06AT/TS8xC51Rx2P0.0156P0.1145P0.2123P0.3112P0.4964P0.5661P0.6560P0.7359P1.01910P1.12112P1.22213P1.32314P1.42516P1.52718P1.62819P1.72920P2.05443P2.15544P2.25645P2.35847P2.45948P2.56150P2.66453P2.76554P3.03425P3.13928PinPLCC68SQUARE VQFP64 1.4P3.24029P3.34130P3.44231P3.54332P3.64534P3.74736RESET 3021ALE/PROG6856AT/TS8xC51Rx2PSEN6755EA/VPP258XTAL14938XTAL24837P4.02011P4.12415P4.22617P4.34433P4.44635P4.55039P4.65342P4.75746P5.06049P5.16251P5.26352P5.3762P5.4863P5.5101P5.6134P5.71675.2TS80C51Rx2 Enhanced FeaturesIn comparison to the original 80C52, the TS8xC51Rx2 implements some new features, whichare:•The X2 option.•The Dual Data Pointer.•The extended RAM.•The Programmable Counter Array (PCA).•The Watchdog.•The 4 level interrupt priority system.•The power-off flag.•The ONCE mode.•The ALE disabling.•Some enhanced features are also located in the UART and the timer 2.5.3X2 FeatureThe TS80C51Rx2 core needs only 6 clock periods per machine cycle. This feature called ”X2”provides the following advantages:•Divides frequency crystals by 2 (cheaper crystals) while keeping same CPU power.•Saves power consumption while keeping same CPU power (oscillator power saving).•Saves power consumption by dividing dynamically operating frequency by 2 in operating andidle modes.•Increases CPU power by 2 while keeping same crystal frequency.In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 sig-nal and the main clock input of the core (phase generator). This divider may be disabled bysoftware.5.3.1DescriptionThe clock for the whole circuit and peripheral is first divided by two before being used by theCPU core and peripherals. This allows any cyclic ratio to be accepted on XTAL1 input. In X2mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to60%. Figure 5-1 shows the clock generation block diagram. X2 bit is validated on XTAL1÷2 ris-ing edge to avoid glitches when switching from X2 to STD mode. Figure 5-2 shows the modeswitching waveforms.AT/TS8xC51Rx2AT/TS8xC51Rx2Figure 5-1.Clock Generation DiagramFigure 5-2.Mode Switching WaveformsThe X2 bit in the CKCON register (Table 5-2) allows to switch from 12 clock cycles per instruc-tion to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the X2 feature (X2 mode).Note:In order to prevent any incorrect operation while operating in X2 mode, user must be aware that all peripherals using clock frequency as time reference (UART, timers, PCA...) will have their time ref-erence divided by two. For example a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. UART with 4800 baud rate will have 9600 baud rate.Table 5-2.CKCON RegisterCKCON - Clock Control Register (8Fh)XTAL12CKCON regX2state machine: 6 clock cycles.CPU controlF OSCF XTAL01XTAL1:2XTAL1:2XTAL1CPU clockX2 bitX2 ModeSTD ModeSTD Mode76543210Bit NumberBit MnemonicDescription7-ReservedThe value read from this bit is indeterminate. Do not set this bit.6-ReservedThe value read from this bit is indeterminate. Do not set this bit.5-ReservedThe value read from this bit is indeterminate. Do not set this bit.AT/TS8xC51Rx2Not bit addressableFor further details on the X2 feature, please refer to ANM072 available on the web ()4-ReservedThe value read from this bit is indeterminate. Do not set this bit.3-ReservedThe value read from this bit is indeterminate. Do not set this bit.2-ReservedThe value read from this bit is indeterminate. Do not set this bit.1-ReservedThe value read from this bit is indeterminate. Do not set this bit.0X2CPU and peripheral clock bitClear to select 12 clock periods per machine cycle (STD mode, F OSC =F XTAL /2). Set to select 6 clock periods per machine cycle (X2 mode, F OSC =F XTAL ).Bit NumberBit MnemonicDescriptionAT/TS8xC51Rx25.4Dual Data Pointer RegisterThe additional data pointer can be used to speed up code execution and reduce code size in a number of ways.The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1/bit0 (Table 5-3) that allows the program code to switch between them (Refer to Figure 5-3).Figure 5-3.Use of Dual PointerTable 5-3.AUXR1: Auxiliary Register 1External Data MemoryAUXR1(A2H)DPSDPH(83H)DPL(82H)07DPTR0DPTR1AUXR1Address 0A2H----GF3--DPS ResetvalueXXXXXXSymbolFunction-Not implemented, reserved for future use (1)1.User software should not write 1s to reserved bits. These bits may be used in future 8051 familyproducts to invoke new feature. In that case, the reset value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.GF3 will not be available on first version of the RC devices.DPSData Pointer Selection.DPS Operating Mode 0DPTR0 Selected 1DPTR1 SelectedGF3This bit is a general purpose user flag (2).6.ApplicationSoftware can take advantage of the additional data pointers to both increase speed and reducecode size, for example, block operations (copy, compare, search ...) are well served by usingone data pointer as a ’source’ pointer and the other one as a "destination" pointer.ASSEMBLY LANGUAGE; Block move using dual data pointers; Destroys DPTR0, DPTR1, A and PSW; note: DPS exits opposite of entry state; unless an extra INC AUXR1 is added;00A2 AUXR1 EQU 0A2H;0000 909000MOV DPTR,#SOURCE ; address of SOURCE0003 05A2 INC AUXR1 ; switch data pointers0005 90A000 MOV DPTR,#DEST ; address of DEST0008 LOOP:0008 05A2 INC AUXR1 ; switch data pointers000A E0 MOVX A,@DPTR ; get a byte from SOURCE000B A3 INC DPTR ; increment SOURCE address000C 05A2 INC AUXR1 ; switch data pointers000E F0 MOVX @DPTR,A ; write the byte to DEST000F A3 INC DPTR ; increment DEST address0010 70F6JNZ LOOP ; check for 0 terminator0012 05A2 INC AUXR1 ; (optional) restore DPSINC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR.However, note that the INC instruction does not directly force the DPS bit to a particular state,but simply toggles it. In simple routines, such as the block move example, only the fact that DPSis toggled in the proper sequence matters, not its actual value. In other words, the block moveroutine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruc-tion (INC AUXR1), the routine will exit with DPS in the opposite state.AT/TS8xC51Rx2AT/TS8xC51Rx26.1Expanded RAM (XRAM)The TS80C51Rx2 provide additional Bytes of ramdom access memory (RAM) space forincreased data parameter handling and high level language usage.RA2, RB2 and RC2 devices have 256 bytes of expanded RAM, from 00H to FFH in externaldata space; RD2 devices have 768 bytes of expanded RAM, from 00H to 2FFH in external dataspace.The TS80C51Rx2 has internal data memory that is mapped into four separate segments.The four segments are:•1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are directly and indirectlyaddressable.•2. The Upper 128 bytes of RAM (addresses 80H to FFH) are indirectly addressable only.•3. The Special Function Registers, SFRs, (addresses 80H to FFH) are directly addressableonly.•4. The expanded RAM bytes are indirectly accessed by MOVX instructions, and with theEXTRAM bit cleared in the AUXR register. (See Table 6-1.)The Lower 128 bytes can be accessed by either direct or indirect addressing. The Upper 128bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy the sameaddress space as the SFR. That means they have the same address, but are physically sepa-rate from SFR space.When an instruction accesses an internal location above address 7FH, the CPU knows whetherthe access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode usedin the instruction.•Instructions that use direct addressing access SFR space. For example: MOV 0A0H, #data, accesses the SFR at location 0A0H (which is P2).•Instructions that use indirect addressing access the Upper 128 bytes of data RAM. Forexample: MOV @R0, # data where R0 contains 0A0H, accesses the data byte at address0A0H, rather than P2 (whose address is 0A0H).•The 256 or 768 XRAM bytes can be accessed by indirect addressing, with EXTRAM bitcleared and MOVX instructions. This part of memory which is physically located on-chip,logically occupies the first 256 or 768 bytes of external data memory.•With EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX instruction incombination with any of the registers R0, R1 of the selected bank or DPTR. An access toXRAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD). For example, with EXTRAM= 0, MOVX @R0, # data where R0 contains 0A0H, accesses the XRAM at address 0A0Hrather than external memory. An access to external data memory locations higher than FFH(i.e. 0100H to FFFFH) (higher than 2FFH (i.e. 0300H to FFFFH for RD devices) will beperformed with the MOVX DPTR instructions in the same way as in the standard 80C51, sowith P0 and P2 as data/address busses, and P3.6 and P3.7 as write and read timing signals.Refer to Figure 6-1. For RD devices, accesses to expanded RAM from 100H to 2FFH canonly be done thanks to the use of DPTR.•With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard 80C51.MOVX @ Ri will provide an eight-bit address multiplexed with data on Port0 and any outputport pins can be used to output higher order address bits. This is to provide the externalpaging capability. MOVX @DPTR will generate a sixteen-bit address. Port2 outputs the high-order eight address bits (the contents of DPH) while Port0 multiplexes the low-order eightAT/TS8xC51Rx2address bits (DPL) with data. MOVX @ Ri and MOVX @DPTR will generate either read or write signals on P3.6 (WR) and P3.7 (RD).The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM) internal data memory. The stack may not be located in the XRAM.Figure 6-1.Internal and External Data Memory AddressTable 6-1.Auxiliary Register AUXRXRAM 256 bytesUpper 128 bytes InternalRamLower 128 bytes Internal RamSpecial Function Register 808000FF(RA, RB, RC)/2FF (RD)FF00FFExternal Data Memory00000100 (RA, RB, RC) or 0300 (RD)FFFFindirect accessesdirect accessesdirect or indirect accessesAUXR Address 08EH------EXTRAMAOSymbolFunction-Not implemented, reserved for future use. (1)1.User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.AODisable/Enable ALEAO Operating Mode0ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2 mode is used)1ALE is active only during a MOVX or MOVC instructionEXTRAM Internal/External RAM (00H-FFH) access using MOVX @ Ri/ @ DPTR EXTRAMOperating Mode0Internal XRAM access using MOVX @ Ri/ @ DPTR 1External data memory accessAT/TS8xC51Rx26.2Timer 2The timer 2 in the TS80C51RX2 is compatible with the timer 2 in the 80C52.It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2,connected in cascade. It is controlled by T2CON register (See Table 6-2) and T2MOD register(See Table 6-3). Timer 2 operation is similar to Timer 0 and Timer 1. C/T2 selects F OSC/12 (timeroperation) or external pin T2 (counter operation) as the timer clock input. Setting TR2 allows TL2to be incremented by the selected input.Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These modesare selected by the combination of RCLK, TCLK and CP/RL2 (T2CON), as described in theAtmel 8-bit Microcontroller Hardware description.Refer to the Atmel 8-bit Microcontroller Hardware description for the description of Capture andBaud Rate Generator Modes.In TS80C51RX2 Timer 2 includes the following enhancements:•Auto-reload mode with up or down counter•Programmable clock-output6.2.1Auto-reload ModeThe auto-reload mode configures timer 2 as a 16-bit timer or event counter with automaticreload. If DCEN bit in T2MOD is cleared, timer 2 behaves as in 80C52 (refer to the Atmel 8-bitMicrocontroller Hardware description). If DCEN bit is set, timer 2 acts as an Up/downtimer/counter as shown in Figure 6-2. In this mode the T2EX pin controls the direction of count.When T2EX is high, timer 2 counts up. Timer overflow occurs at FFFFh which sets the TF2 flagand generates an interrupt request. The overflow also causes the 16-bit value in RCAP2H andRCAP2L registers to be loaded into the timer registers TH2 and TL2.When T2EX is low, timer 2 counts down. Timer underflow occurs when the count in the timerregisters TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers. The under-flow sets TF2 flag and reloads FFFFh into the timer registers.The EXF2 bit toggles when timer 2 overflows or underflows according to the the direction of thecount. EXF2 does not generate any interrupt. This bit can be used to provide 17-bit resolution.AT/TS8xC51Rx2Figure 6-2.Auto-reload Mode Up/Down Counter (DCEN = 1)6.2.2Programmable Clock-OutputIn the clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 6-3) . The input clock increments TL2 at frequency F OSC /2. The timer repeatedly counts to overflow from a loaded value. At overflow, the contents of RCAP2H and RCAP2L reg-isters are loaded into TH2 and TL2. In this mode, timer 2 overflows do not generate interrupts. The formula gives the clock-out frequency as a function of the system oscillator frequency and the value in the RCAP2H and RCAP2L registers:For a 16 MHz system clock, timer 2 has a programmable frequency range of 61 Hz (F OSC /216) to 4 MHz (F OSC /4). The generated clock signal is brought out to T2 pin (P1.0).Timer 2 is programmed for the clock-out mode as follows:•Set T2OE bit in T2MOD register.•Clear C/T2 bit in T2CON register.•Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L registers.•Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the reload value or a different one depending on the application.•To start the timer, set TR2 run control bit in T2CON register.XTAL1F Clock OutFrequency –F osc465536RCAP 2H –RCAP 2L ⁄()×----------------------------------------------------------------------------------------=。

AT89C52中文资料AT89C52的中文资料AT89C52是美国Atmel公司生产的低电压、高性能CMOS 8位单片机，片内含8KB的可反复檫写的程序存储器和12B的随机存取数据存储器（RAM），器件采用Atmel公司的高密度、非易失性存储技术生产，兼容标准MCS-51指令系统，片内配置通用8位中央处理器（CPU）和Flash存储单元，功能强大的AT89C52单片机可灵活应用于各种控制领域。

AT89C52单片机属于AT89C51单片机的增强型，与Intel 公司的80C52在引脚排列、硬件组成、工作特点和指令系统等方面兼容。

其主要工作特性是：片内程序存储器内含8KB的Flash程序存储器，可擦写寿命为1000次；片内数据存储器内含256字节的RAM；具有32根可编程I/O口线；具有3个可编程定时器；中断系统是具有8个中断源、6个中断矢量、2个级优先权的中断结构；串行口是具有一个全双工的可编程串行通信口；具有一个数据指针DPTR；低功耗工作模式有空闲模式和掉电模式；具有可编程的3级程序锁定位；AT89C52工作电源电压为5（1+0.2）V，且典型值为5V；AT89C52最高工作频率为24MHz。

单片机正常工作时，都需要有一个时钟电路和一个复位电路。

本设计中选择了内部时钟方式和按键电平复位电路，来构成单片机的最小电路。

如图3.1所示。

功能特性描述AT89S52是一种低功耗、高性能CMOS8位微控制器，具有8K 在系统可编程Flash 存储器。

使用Atmel 公司高密度非易失性存储器技术制造，与工业80C51 产品指令和引脚完全兼容。

片上Flash允许程序存储器在系统可编程，亦适于常规编程器。

在单芯片上，拥有灵巧的8 位CPU 和在系统可编程Flash，使得AT89S52为众多嵌入式控制应用系统提供高灵活、超有效的解决方案。

AT89S52具有以下标准功能：8k字节Flash，256字节RAM，32 位I/O 口线，看门狗定时器，2 个数据指针，三个16 位定时器/计数器，一个6向量2级中断结构，全双工串行口，片内晶振及时钟电路。