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FPGA可编程逻辑器件芯片XC95216-15PQG160I中文规格书

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Spartan-3 FPGA Family: DC and Switching CharacteristicsThe capacitive load (C L ) is connected between the output and GND. The Output timing for all standards, as published in the speed files and the data sheet, is always based on a C L value of zero . High-impedance probes (less than 1 pF) are used for all measurements. Any delay that the test fixture might contribute to test measurements is subtracted from those measurements to produce the final timing numbers as published in the speed files and data sheet.Using IBIS Models to Simulate Load Conditions in ApplicationIBIS Models permit the most accurate prediction of timing delays for a given application. The parameters found in the IBIS model (V REF , R REF , and V MEAS ) correspond directly with the parameters used in T able 48, V T , R T , and V M . Do not confuse V REF (the termination voltage) from the IBIS model with V REF (the input-switching threshold) from the table. A fourthparameter, C REF , is always zero. The four parameters describe all relevant output test conditions. IBIS models are found in the Xilinx development software as well as at the following link.Simulate delays for a given application according to its specific load conditions as follows:1.Simulate the desired signal standard with the output driver connected to the test setup shown in Figure 35. Useparameter values V T , R T , and V M from Table 48. C REF is zero.2.Record the time to V M .3.Simulate the same signal standard with the output driver connected to the PCB trace with load. Use the appropriate IBISmodel (including V REF , R REF , C REF , and V MEAS values) or capacitive value to represent the load.4.Record the time to V MEAS .pare the results of steps 2 and 4. The increase (or decrease) in delay should be added to (or subtracted from) theappropriate Output standard adjustment (T able 47) to yield the worst-case delay of the PCB trace.DIFF_SSTL2_II -V ICM – 0.75V ICM + 0.75501.25V ICMDIFF_SSTL2_II_DCI Notes:1.Descriptions of the relevant symbols are as follows:VREF – The reference voltage for setting the input switching threshold VICM – The common mode input voltageVM – Voltage of measurement point on signal transition VL – Low-level test voltage at Input pin VH – High-level test voltage at Input pinRT – Effective termination resistance, which takes on a value of 1MW when no parallel termination is required VT – Termination voltage2.The load capacitance (CL) at the Output pin is 0 pF for all signal standards.3.According to the PCI specification.Table 48:Test Methods for Timing Measurement at I/Os (Cont’d)Signal Standard (IOSTANDARD)InputsOutputsInputs and OutputsV REF (V)V L (V)V H (V)R T (Ω)V T (V)V M (V)Table 70:Spartan-3 FPGA Pin DefinitionsPin Name Direction Description I/O: General-purpose I/O pinsI/O User-defined as input, output,bidirectional, three-state output,open-drain output, open-sourceoutput User I/O:Unrestricted single-ended user-I/O pin. Supports all I/O standards except the differential standards.I/O_Lxxy_#User-defined as input, output,bidirectional, three-state output,open-drain output, open-sourceoutput User I/O, Half of Differential Pair:Unrestricted single-ended user-I/O pin or half of a differential pair. Supports all I/O standards including the differential standards.DUAL: Dual-purpose configuration pinsIO_Lxxy_#/DIN/D0, IO_Lxxy_#/D1,IO_Lxxy_#/D2,IO_Lxxy_#/D3,IO_Lxxy_#/D4,IO_Lxxy_#/D5,IO_Lxxy_#/D6,IO_Lxxy_#/D7Input during configurationPossible bidirectional I/O afterconfiguration if SelectMap port isretainedOtherwise, user I/O afterconfigurationConfiguration Data Port:In Parallel (SelectMAP) modes, D0-D7 are byte-wide configuration datapins. These pins become user I/Os after configuration unless theSelectMAP port is retained via the Persist bitstream option.In Serial modes, DIN (D0) serves as the single configuration data input.This pin becomes a user I/O after configuration unless retained by thePersist bitstream option.IO_Lxxy_#/CS_B Input during Parallel modeconfigurationPossible input after configuration if SelectMap port is retained Otherwise, user I/O after configuration Chip Select for Parallel Mode Configuration:In Parallel (SelectMAP) modes, this is the active-Low Chip Select signal. This pin becomes a user I/O after configuration unless the SelectMAP port is retained via the Persist bitstream option.IO_Lxxy_#/RDWR_B Input during Parallel modeconfigurationPossible input after configurationif SelectMap port is retainedOtherwise, user I/O afterconfiguration Read/Write Control for Parallel Mode Configuration:In Parallel (SelectMAP) modes, this is the active-Low Write Enable, active-High Read Enable signal. This pin becomes a user I/O after configuration unless the SelectMAP port is retained via the Persist bitstream option.IO_Lxxy_#/ BUSY/DOUT Output during configurationPossible output afterconfiguration if SelectMap port isretainedOtherwise, user I/O afterconfigurationConfiguration Data Rate Control for Parallel Mode, Serial DataOutput for Serial Mode:In Parallel (SelectMAP) modes, BUSY throttles the rate at whichconfiguration data is loaded. This pin becomes a user I/O afterconfiguration unless the SelectMAP port is retained via the Persistbitstream option.In Serial modes, DOUT provides preamble and configuration data todownstream devices in a multi-FPGA daisy-chain. This pin becomes auser I/O after configuration.IO_Lxxy_#/INIT_B Bidirectional (open-drain) duringconfigurationUser I/O after configuration Initializing Configuration Memory/Detected Configuration Error: When Low, this pin indicates that configuration memory is being cleared. When held Low, this pin delays the start of configuration. After this pin is released or configuration memory is cleared, the pin goes High. During configuration, a Low on this output indicates that a configuration data error occurred. This pin always has an internal pull-up resistor to VCCO_4 or VCCO_BOTTOM during configuration, regardless of the HSWAP_EN pin. This pin becomes a user I/O after configuration.DCI: Digitally Controlled Impedance reference resistor input pinsIO_Lxxy_#/VRN_# or IO/VRN_#Input when using DCIOtherwise, same as I/ODCI Reference Resistor for NMOS I/O Transistor (per bank):If using DCI, a 1% precision impedance-matching resistor is connectedbetween this pin and the VCCO supply for this bank. Otherwise, this pin isa user I/O.IO_Lxxy_#/VRP_# or IO/VRP_#Input when using DCIOtherwise, same as I/ODCI Reference Resistor for PMOS I/O Transistor (per bank):If using DCI, a 1% precision impedance-matching resistor is connectedbetween this pin and the ground supply. Otherwise, this pin is a user I/O.All VCCAUX inputs must be connected together and to the +2.5V voltage supply. Furthermore, there must be sufficient supply decoupling to guarantee problem-free operation, as described in XAPP623.Because VCCAUX connects to the DCMs and the DCMs are sensitive to voltage changes, be sure that the VCCAUX supply and the ground return paths are designed for low noise and low voltage drop, especially that caused by a large number of simultaneous switching I/Os.GND Type: GroundAll GND pins must be connected and have a low resistance path back to the various VCCO, VCCINT, and VCCAUX supplies.Pin Behavior During ConfigurationTable79 shows how various pins behave during the FPGA configuration process. The actual behavior depends on the values applied to the M2, M1, and M0 mode select pins and the HSWAP_EN pin. The mode select pins determine which of the DUAL type pins are active during configuration. In JT AG configuration mode, none of the DUAL-type pins are used for configuration and all behave as user-I/O pins.All DUAL-type pins not actively used during configuration and all I/O-type, DCI-type, VREF-type, GCLK-type pins are high impedance (floating, three-stated, Hi-Z) during the configuration process. These pins are indicated in Table79 as shaded table entries or cells. These pins have a pull-up resistor to their associated VCCO if the HSWAP_EN pin is Low. When HSWAP_EN is High, these pull-up resistors are disabled during configuration.Some pins always have an active pull-up resistor during configuration, regardless of the value applied to the HSWAP_EN pin. After configuration, these pull-up resistors are controlled by Bitstream Options.•All the dedicated CONFIG-type configuration pins (CCLK, PROG_B, DONE, M2, M1, M0, and HSWAP_EN) have a pull-up resistor to VCCAUX.•All JTAG-type pins (TCK, TDI, TMS, TDO) have a pull-up resistor to VCCAUX.•The INIT_B DUAL-purpose pin has a pull-up resistor to VCCO_4 or VCCO_BOTTOM, depending on package style. After configuration completes, some pins have optional behavior controlled by the configuration bitstream loaded into the part. For example, via the bitstream, all unused I/O pins can be collectively configured as input pins with either a pull-up resistor, a pull-down resistor, or be left in a high-impedance state.Table 79:Pin Behavior After Power-Up, During ConfigurationPin NameConfiguration Mode Settings <M2:M1:M0>BitstreamConfigurationOption Serial Modes SelectMap Parallel Modes JTAG Mode<1:0:1>Master <0:0:0>Slave <1:1:1>Master <0:1:1>Slave <1:1:0>I/O: General-purpose I/O pinsIO UnusedPinIO_Lxxy_#UnusedPin DUAL: Dual-purpose configuration pinsIO_Lxxy_#/DIN/D0DIN (I)DIN (I)D0 (I/O)D0 (I/O)Persist UnusedPinIO_Lxxy_#/D1D1 (I/O)D1 (I/O)Persist UnusedPinIO_Lxxy_#/D2D2 (I/O)D2 (I/O)Persist UnusedPinIO_Lxxy_#/D3D3 (I/O)D3 (I/O)Persist UnusedPinIO_Lxxy_#/D4D4 (I/O)D4 (I/O)Persist UnusedPin。

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FPGA可编程逻辑器件芯片XCVU160-1FLGB2104C中文规格书

FPGA可编程逻辑器件芯片XCVU160-1FLGB2104C中文规格书

4
– 2
VU35P 1,906,800 1,743,360 871,680
24.6 1,344 47.3 640 180.0
8 8 416 5,952 2 64 0 0 32 1
4
2 5Leabharlann VU37P 2,851,800 2,607,360 1,303,680
36.7 2,016 70.9
960 270.0
4
4 10
Notes: 1. HP = High-performance I/O with support for I/O voltage from 1.0V to 1.8V.
2. GTY transceivers in the FLGF1924 package support data rates up to 16.3Gb/s. See Table 12. 3. This block operates in compatibility mode for 16.0GT/s (Gen4) operation. Go to PG213, UltraScale+ Devices Integrated
280–668
Virtex UltraScale
FPGA
783–5,541 44.3–132.9
600–2,880 4,268 36–120 30.5 5,616 2,400
338–1,456
Virtex UltraScale+
FPGA
862–8,938 23.6–94.5
90–360 0–16
1,320–12,288 21,897 32–128 58.0 8,384 2,666
1,872–4,272 7,613 8–16 32.75 1,048 2,666
FPGA可编程逻辑器件芯片XC95108-10PQ100I中文规格书

FPGA可编程逻辑器件芯片XC95108-10PQ100I中文规格书

Chapter 1:Configuration OverviewCreating an Encrypted BitstreamBitGen, provided with the Xilinx ISE software, can generate encrypted as well as non-encrypted bitstreams. For AES bitstream encryption, the user specifies a 256-bit key as aninput to BitGen. BitGen in turn generates an encrypted bitstream file (BIT) and anencryption key file (NKY).For specific BitGen commands and syntax, refer to the Development System Reference Guide.Loading the Encryption KeyThe encryption key can only be loaded onto a Virtex-5 device through the JTAG interface.The iMPACT tool, provided with the Xilinx ISE software, can accept the NKY file as aninput and program the device with the key through JTAG, using a supported Xilinxprogramming cable.To program the key, the device enters a special key-access mode using theISC_PROGRAM_KEY instruction. In this mode, all FPGA memory, including theencryption key and configuration memory, is cleared. After the key is programmed andthe key-access mode is exited, the key cannot be read out of the device by any means, andit cannot be reprogrammed without clearing the entire device. The key-access mode istransparent to most users.Loading Encrypted BitstreamsOnce the device has been programmed with the correct encryption key, the device can beconfigured with an encrypted bitstream. After configuration with an encrypted bitstream,it is not possible to read the configuration memory through JTAG or SelectMAP readback,regardless of the BitGen security setting.While the device holds an encryption key, a non-encrypted bitstream can be used toconfigure the device; in this case the key is ignored. After configuring with a non-encrypted bitstream, readback is possible (if allowed by the BitGen security setting). Theencryption key still cannot be read out of the device, preventing the use of Trojan Horsebitstreams to defeat the Virtex-5 encryption scheme.The method of configuration is not affected by encryption. The configuration bitstream canbe delivered in any mode (Serial, JTAG, or any x8 parallel modes) from any configurationsolution (PROM, System ACE™ controller, etc.). The x16 and x32 bus widths are notsupported for encrypted bitstreams. Configuration timing and signaling are alsounaffected by encryption.The encrypted bitstream must configure the entire device because partial reconfigurationthrough any configuration interface is not permitted for encrypted bitstreams. Afterconfiguration, the device cannot be reconfigured without toggling the PROGRAM_B pin,cycling power, or issuing the JPROGRAM instruction. Fallback reconfiguration andIPROG reconfiguration (see “Fallback MultiBoot,” page153) are disabled after encryptionis turned on. Readback is available through the ICAP primitive (see “Bitstream Encryptionand Internal Configuration Access Port (ICAP)”). None of these events resets the key ifV BATT or V CCAUX is maintained.A mismatch between the key in the encrypted bitstream and the key stored in the devicecauses configuration to fail with the INIT_B pin going Low and the DONE pin remainingLow.Bitstream EncryptionBitstream Encryption and Internal Configuration Access Port (ICAP) The Internal Configuration Access Port (ICAP) primitive provides the user logic withaccess to the Virtex-5 configuration interface. The ICAP interface is similar to theSelectMAP interface, although the restrictions on readback for the SelectMAP interface donot apply to the ICAP interface after configuration. Users can perform readback throughthe ICAP interface even if bitstream encryption is used. Unless the designer wires the ICAPinterface to user I/O, this interface does not offer attackers a method for defeating theVirtex-5 AES encryption scheme.Users concerned about the security of their design should not:∙Wire the ICAP interface to user I/O-or-∙Instantiate the ICAP primitive.Like the other configuration interfaces, the ICAP interface does not provide access to thekey register.V BATTThe encryption key memory cells are volatile and must receive continuous power to retaintheir contents. During normal operation, these memory cells are powered by the auxiliaryvoltage input (V CCAUX), although a separate V BATT power input is provided for retainingthe key when V CCAUX is removed. Because V BATT draws very little current (on the order ofnanoamperes), a small watch battery is suitable for this supply. (To estimate the battery life,refer to V BATT DC Characteristics in DS202, Virtex-5 Data Sheet: DC and SwitchingCharacteristics and the battery specifications.) At less than a 100nA load, the endurance ofthe battery should be limited only by its shelf life.V BATT does not draw any current and can be removed while V CCAUX is applied. V BATTcannot be used for any purpose other than retaining the encryption keys when V CCAUX isremoved.Chapter 1:Configuration OverviewSelectMAP Configuration Interface PROM files for ganged serial configuration are identical to the PROM files used toconfigure single devices. There are no special PROM file considerations.SelectMAP Configuration InterfaceThe SelectMAP configuration interface (Figure2-6) provides an 8-bit, 16-bit, or 32-bitbidirectional data bus interface to the Virtex-5 configuration logic that can be used for bothconfiguration and readback. (For details, refer to Chapter7, “Readback and ConfigurationVerification.”) The bus width of SelectMAP is automatically detected (see “Bus Width AutoDetection”).CCLK is an output in Master SelectMAP mode; in Slave SelectMAP, CCLK is an input. Oneor more Virtex-5 devices can be configured through the SelectMAP bus.There are four methods of configuring an FPGA in SelectMAP mode:∙Single device Master SelectMAP∙Single device Slave SelectMAP∙Multiple device SelectMAP bus∙Multiple device ganged SelectMAPTable2-4 describes the SelectMAP configuration interface.Figure 2-6:Virtex-5 Device SelectMAP Configuration InterfaceTable 2-4:Virtex-5 Device SelectMAP Configuration Interface PinsPin Name Type Dedicatedor Dual-PurposeDescriptionM[2:0]Input Dedicated Mode pins - determine configuration modeCCLK Input andOutputDedicatedConfiguration clock source for all configurationmodes except JTAGD[31:0]Three-StateBidirectionalDual-PurposeConfiguration and readback data bus, clockedon the rising edge of CCLK. See “Parallel BusBit Order” and Table1-2.BU S YDONECCLKPROGRAM_BINIT_BD[31:0]M[2:0]C S_BRDWR_BC S O_BUG191_c2_10_072407Board Layout for Configuration Clock (CCLK)。

FPGA可编程逻辑器件芯片XC4VLX160-11FFG1513I中文规格书

FPGA可编程逻辑器件芯片XC4VLX160-11FFG1513I中文规格书

XCN18019 July 16, 2018XCN18019 (v1.0) July 16, 2018 Product Change Notice – FYI OverviewThe purpose of this notification is to communicate that Xilinx ® defense-grade product chip-capacitor manufacturer will change the manufacturing location for chip-capacitors used in Xilinx defense-grade “XQ” products.DescriptionXilinx defense-grade product chip-capacitor manufacturer will change its chip-capacitor manufacturing location for various capacitors. Xilinx has worked with the supplier to qualify this capacitor manufacturing location. This change enables Xilinx to better support long-term customer demand. There is no change in the fit, form, function or reliability of the capacitor with this change.Products AffectedThis change affects all speeds, temperature variations of defense-grade “XQ” product grades of Virtex ®-4, Virtex ®-5, Virtex ®-6, Virtex ®-7, Kintex ®-7 and Zynq ®-7000 as defined in the tables below. Any associated specification control document (SCD) versions of the standard part numbers are also affected.Table 1: Virtex-4Q Device-PackagesDevice Package-PinDevice Package-Pin XQ4VLX60FF1148 XQ4VFX60 FF1152 XQ4VLX100XQ4VFX100 XQ4VLX160XQ4VFX60 EF672XQ4VLX80XQ4VSX55 Table 2:Virtex-5Q Device-PackagesDevicePackage-Pin Device Package-Pin XQ5VFX70TEF665 XQ5VLX110 EF1153 XQ5VSX50TXQ5VLX220T EF1738 XQ5VLX85EF676 XQ5VLX330T XQ5VLX110XQ5VFX100T XQ5VLX110TEF1136 XQ5VFX130T XQ5VLX155TXQ5VFX200T FF1738XQ5VFX70TXQ5VSX240T XQ5VFX100TXQ5VSX95TChip-Capacitor Manufacturing Location Change for Defense-Grade XQ Product XCN18019 July 16, 2018 Table 3: Virtex-6Q Device-PackagesDevice Package-PinDevice Package-Pin XQ6VLX130TRF1156 XQ6VLX240T RF1759XQ6VLX240TXQ6VLX550T XQ6VSX315TXQ6VSX315T XQ6VSX475TXQ6VSX475T XQ6VLX130TRF784 XQ6VLX240T Table 4: Virtex-7Q Devices-PackagesDevice Package-PinXQ7V585TRF1157XQ7VX330TXQ7VX690TXQ7VX690TRF1158 XQ7V585TRF1761 XQ7VX330TXQ7VX485TXQ7VX690TXQ7VX485TRF1930 XQ7VX690TXQ7VX980T Table 5: Kintex-7Q and Zynq-7000 Devices-PackagesDevice Package-PinXQ7Z030RB484 XQ7Z100RF1156XQ7K325TRF676 XQ7K410TXQ7Z030XQ7Z045XQ7K325TRF900 XQ7K410TXQ7Z045XQ7Z100Chip-Capacitor Manufacturing Location Change for Defense-Grade XQ Product XCN18109 July 16, 2018 Revision HistoryThe following table shows the revision history for this document: DateVersion Description of Revisions07/16/2018 1.0 Initial release。

FPGA可编程逻辑器件芯片XC95144-10PQ160I中文规格书

FPGA可编程逻辑器件芯片XC95144-10PQ160I中文规格书

Module 1:Introduction and Ordering Information DS099 (v3.1) June 27, 2013•Introduction•Features•Architectural Overview•Array Sizes and Resources•User I/O Chart•Ordering InformationModule 2: Functional DescriptionDS099 (v3.1) June 27, 2013•Input/Output Blocks (IOBs)•IOB Overview•SelectIO™ Interface I/O Standards •Configurable Logic Blocks (CLBs)•Block RAM•Dedicated Multipliers•Digital Clock Manager (DCM)•Clock Network•ConfigurationModule 3:DC and Switching CharacteristicsDS099 (v3.1) June 27, 2013•DC Electrical Characteristics•Absolute Maximum Ratings•Supply Voltage Specifications•Recommended Operating Conditions•DC Characteristics•Switching Characteristics•I/O Timing•Internal Logic Timing•DCM Timing•Configuration and JT AG Timing Module 4: Pinout DescriptionsDS099 (v3.1) June 27, 2013•Pin Descriptions•Pin Behavior During Configuration•Package Overview•Pinout T ables•FootprintsSpartan-3 FPGA FamilyData SheetDS099 June 27, 2013Product SpecificationTable 35:Recommended Operating Conditions for User I/Os Using Single-Ended StandardsSignal Standard (IOSTANDARD)V CCO V REF V IL V IH Min (V)Nom (V)Max (V)Min (V)Nom (V)Max (V)Max (V)Min (V)GTL(3)–––0.740.80.86V REF – 0.05V REF + 0.05 GTL_DCI– 1.2–0.740.80.86V REF – 0.05V REF + 0.05 GTLP(3)–––0.881 1.12V REF – 0.1V REF + 0.1 GTLP_DCI– 1.5–0.881 1.12V REF – 0.1V REF + 0.1 HSLVDCI_15 1.4 1.5 1.6–0.75–V REF – 0.1V REF + 0.1 HSLVDCI_18 1.7 1.8 1.9–0.9–V REF – 0.1V REF + 0.1 HSLVDCI_25 2.3 2.5 2.7– 1.25–V REF – 0.1V REF + 0.1 HSLVDCI_33 3.0 3.3 3.465– 1.65–V REF – 0.1V REF + 0.1 HSTL_I, HSTL_I_DCI 1.4 1.5 1.60.680.750.9V REF – 0.1V REF + 0.1 HSTL_III,HSTL_III_DCI 1.4 1.5 1.6–0.9–V REF – 0.1V REF + 0.1HSTL_I_18,HSTL_I_DCI_18 1.7 1.8 1.90.80.9 1.1V REF – 0.1V REF + 0.1 HSTL_II_18,HSTL_II_DCI_18 1.7 1.8 1.9–0.9–V REF – 0.1V REF + 0.1HSTL_III_18,HSTL_III_DCI_18 1.7 1.8 1.9– 1.1–V REF – 0.1V REF + 0.1 LVCMOS12 1.14 1.2 1.3–––0.37V CCO0.58V CCO LVCMOS15,LVDCI_15,LVDCI_DV2_151.4 1.5 1.6–––0.30V CCO0.70V CCOLVCMOS18,LVDCI_18,LVDCI_DV2_181.7 1.8 1.9–––0.30V CCO0.70V CCOLVCMOS25(4,5),LVDCI_25,LVDCI_DV2_25(4)2.3 2.5 2.7–––0.7 1.7LVCMOS33,LVDCI_33,LVDCI_DV2_33(4)3.0 3.3 3.465–––0.8 2.0 LVTTL 3.0 3.3 3.465–––0.8 2.0PCI33_3(7) 3.0 3.3 3.465–––0.30V CCO0.50V CCO SSTL18_I,SSTL18_I_DCI 1.7 1.8 1.90.8330.9000.969V REF – 0.125V REF + 0.125 SSTL18_II 1.7 1.8 1.90.8330.9000.969V REF – 0.125V REF + 0.125 SSTL2_I,SSTL2_I_DCI 2.3 2.5 2.7 1.15 1.25 1.35V REF – 0.15V REF + 0.15 SSTL2_II,SSTL2_II_DCI 2.3 2.5 2.7 1.15 1.25 1.35V REF – 0.15V REF + 0.15 Notes:1.Descriptions of the symbols used in this table are as follows:V CCO – the supply voltage for output drivers as well as LVCMOS, LVTTL, and PCI inputsV REF – the reference voltage for setting the input switching thresholdV IL – the input voltage that indicates a Low logic levelV IH – the input voltage that indicates a High logic level2.For device operation, the maximum signal voltage (V IH max) may be as high as V IN max. See Table28.3.Because the GTL and GTLP standards employ open-drain output buffers, V CCO lines do not supply current to the I/O circuit, rather this current isprovided using an external pull-up resistor connected from the I/O pin to a termination voltage (V TT). Nevertheless, the voltage applied to the associated V CCO lines must always be at or above V TT and I/O pad voltages.4.There is approximately 100mV of hysteresis on inputs using LVCMOS25 or LVCMOS33 standards.5.All dedicated pins (M0-M2, CCLK, PROG_B, DONE, HSWAP_EN, TCK, TDI, TDO, and TMS) use the LVCMOS standard and draw power from theV CCAUX rail (2.5V). The dual-purpose configuration pins (DIN/D0, D1-D7, CS_B, RDWR_B, BUSY/DOUT, and INIT_B) use the LVCMOS standard before the user mode. For these pins, apply 2.5V to the V CCO Bank 4 and V CCO Bank 5 rails at power-on and throughout configuration. For information concerning the use of 3.3V signals, see 3.3V-T olerant Configuration Interface, page47.6.The Global Clock Inputs (GCLK0-GCLK7) are dual-purpose pins to which any signal standard can be assigned.7.For more information, see XAPP457.Table 36:DC Characteristics of User I/Os Using Single-Ended StandardsSignal Standard (IOSTANDARD) and Current Drive Attribute (mA)Test Conditions Logic Level Characteristics I OL(mA)I OH(mA)V OLMax (V)V OHMin (V)GTL32–0.4–GTL_DCI Note 3Note 3GTLP36–0.6–GTLP_DCI Note 3Note 3HSLVDCI_15Note 3Note 30.4V CCO – 0.4 HSLVDCI_18HSLVDCI_25HSLVDCI_33HSTL_I8–80.4V CCO – 0.4 HSTL_I_DCI Note 3Note 3HSTL_III24–80.4V CCO – 0.4 HSTL_III_DCI Note 3Note 3HSTL_I_188–80.4V CCO – 0.4 HSTL_I_DCI_18Note 3Note 3HSTL_II_1816–160.4V CCO – 0.4 HSTL_II_DCI_18Note 3Note 3HSTL_III_1824–80.4V CCO – 0.4 HSTL_III_DCI_18Note 3Note 3LVCMOS12(4)22–20.4V CCO – 0.4 44–466–6LVCMOS15(4)22–20.4V CCO – 0.4 44–466–688–81212–12LVDCI_15,LVDCI_DV2_15Note 3Note 3LVCMOS18(4)22–20.4V CCO – 0.4 44–466–688–81212–121616–16LVDCI_18,LVDCI_DV2_18Note 3Note 3LVCMOS25(4,5)22–20.4V CCO – 0.4 44–466–688–81212–121616–162424–24LVDCI_25,LVDCI_DV2_25Note 3Note 3。