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modelsim的VHDL仿真前⾯⽤过vivado⾃带的仿真软件，我这个仿真新⼿发现它不能仿真signal信号，所以改⽤modelsim进⾏仿真，虽然经历了⼀些波折，总归仿出结果了，下⾯记录下仿真过程作为备忘：⾸先新建project ，添加主⽂件.vhd和testbench.vhd,全部编译，如下图即是编译成功：⼀定要在如下library⾥点击仿真，不然可能会出现信号缺失的情况：然后在work下⾯找到testbench中的architecture，右击，simulation：这时⾃动跳到波形界⾯，此时在instance单元左击testbench就会在objects看到输⼊输出信号，但是没有内部型号：左击instance中uut模块就可以看到主⽂件内的signal信号和定义的各种变量常量：这时，就可以将需要的信号抓到观测区，选中需要的信号，右击，add wave：带观测区如下：这时就是最后⼀步了，设置仿真时间点击显⽰，就是点击仿真时间右边的那个run（开始忘记这⼀步，发现总是看不见波形，恼⽕！），其实直接在命令⾏输⼊run也是可以的。
此时就可以看到波形咯！最后放下我两个程序吧，⼀个mystate，⼀个mystate_tb是状态机学习的程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;--------------------------------------------------------ENTITY mystate ISPORT(A,clk,rst: IN STD_LOGIC;output_state: OUT STD_LOGIC);END mystate;--------------------------------------------------------ARCHITECTURE rtl OF mystate ISCONSTANT s0: STD_LOGIC_VECTOR(1downto0):="00";CONSTANT s1: STD_LOGIC_VECTOR(1DOWNTO0):="01";CONSTANT S2: STD_LOGIC_VECTOR(1DOWNTO0):="11";SIGNAL current_state: STD_LOGIC_VECTOR(1DOWNTO0);SIGNAL next_state: STD_LOGIC_VECTOR(1DOWNTO0);BEGINPROCESS(clk,rst)BEGINIF(rst='1') THENcurrent_state<=s0;ELSIF(clk'EVENT AND clk='1') THENcurrent_state<=next_state;END IF;END PROCESS;PROCESS(current_state,A)BEGINCASE current_state ISWHEN s0=>IF(A='0') THENnext_state<=s0;ELSEnext_state<=s1;END IF;WHEN s1=>IF(A='0') THENnext_state<=s2;ELSEnext_state<=s1;END IF;WHEN s2=>next_state<=s0;WHEN OTHERS=>NULL;END CASE;END PROCESS;PROCESS(current_state,A)BEGINCASE current_state ISWHEN s0=>IF(A='0') THENoutput_state<='0';ELSEoutput_state<='1';END IF;WHEN s1=>IF(A='0') THENoutput_state<='1';ELSEoutput_state<='0';END IF;WHEN s2=>IF(A='0') THENoutput_state<='0';ELSEoutput_state<='1';END IF;WHEN OTHERS=>NULL;END CASE;END PROCESS;END rtl;library IEEE;use IEEE.Std_logic_1164.all;use IEEE.Numeric_Std.all;entity mystate_tb isend;architecture bench of mystate_tb is component mystatePORT(A,clk,rst: IN STD_LOGIC;output_state: OUT STD_LOGIC);end component;signal A,clk,rst: STD_LOGIC;signal output_state: STD_LOGIC;constant clock_period: time := 10 ns;signal stop_the_clock: boolean;beginuut: mystate port map ( A => A,clk => clk,rst => rst,output_state => output_state );stimulus: processbeginA<='0';wait for 20ns;A<='1';wait for 20ns;A<='0';wait for 20ns;A<='0';wait;stop_the_clock <= true;wait;end process;clocking: processbeginwhile not stop_the_clock loopclk <= '0', '1'after clock_period / 2;wait for clock_period;end loop;wait;end process;resetmy:PROCESSBEGINrst<='1';wait for30 ns;rst<='0';wait;END PROCESS;end;。
基于FPGA的二值图像连通域快速标记汪滴珠;安涛;何培龙【摘要】针对连通域标记算法运算量大、速度慢、硬件实现困难的缺点,提出一种适于现场可编程逻辑门阵列(FPGA)实现的二值图像连通域快速标记的算法,并用VHDL硬件开发语言在XILINX公司的FPGA上实现.实验结果表明了该算法能对二值图像复杂的连通关系正确标记,易于硬件实现,大大节约了硬件资源,电路结构简单,满足实时性要求.%In order to solve the prablems of low speed large computation and difficult hardware implementation of connected component labeling, a connected component fast labcling algorithm of binary image lageling applicable for field programmable gate array (FPGA) is proposed, which is implemented by VHDI. hardware description language based on FPGA platform of XILINX corporation. Experimental results show that the proposed algorithm can label binary image with complex connections correctly, implement hardware easily,save more hardware resource and meet real-time demands.【期刊名称】《现代电子技术》【年(卷),期】2011(034)008【总页数】3页(P115-117)【关键词】FPGA;二值图像;连通域;快速标记【作者】汪滴珠;安涛;何培龙【作者单位】中国科学院,光电技术研究所,四川,成都,610209;中国科学院研究生院,北京,100039;中国科学院,光电技术研究所,四川,成都,610209;中国科学院,光电技术研究所,四川,成都,610209【正文语种】中文【中图分类】TN919-34;TP391连通域标记算法是图像处理、计算机视觉和模式识别等领域的基本算法，它可以对图像中不同目标标上不同的标记，进而提取、分离目标，确定目标的特征和参数，从而对目标进行识别和跟踪。
VHDL拔河游戏机的设计一、设计要求：用7个发光二极管排列成一行，模拟拔河过程。
游戏开始时只有中间的发光二极管点亮，作为拔河的中心线。
用按键来模拟拔河队员，按下键表示用力，根据甲乙双方按键的快慢与多少，决定亮点移动的方向。
移到任一方终端二极管时，该方获胜，该方记分牌自动加分，然后开始下一局的比赛。
比赛采用五局三胜制，甲乙双方各自记分。
当记分牌清零后，重新开始下一场拔河比赛。
(1)、设置“比赛开始”按键，实现一对一拔河；(2)、设置复位键，按下后比分清零，双方重新开始比赛；(3)、一场比赛结束时演奏一首欢快的曲子；选做：甲乙双方可选一到多个队员进行比赛或自拟其它功能。
二、采用器件及软件环境：硬件：EPM7128SLC84-15 开发版软件：QUARTUS软件及windows2000操作系统三、系统设计：1、概述：使用ispLSl1016E芯片，使用ispEXPERT下载到芯片，采用74LS162计数，采用数字电路实现系统设备模拟测试2、设计思想：8个发光二极管用来模拟拔河的过程，中间一个灯为中线标志。
开始进行5秒的倒计时，然后进入游戏。
使用两个按钮，按钮产生脉冲信号，芯片根据两侧按钮信号的快慢，即1秒钟内的按键次数，控制中间的发光二极管的灯的熄灭，某一侧一秒内按的次数多，中间亮的灯就会向那一侧移动；当亮的灯到达最外侧的灯时，相应端的计数器计数加一，用以表示获胜的次数，在数码管上显示，并开始新的一局。
游戏期间使用右方的8*8点阵显示双方的拔河力度，即每秒按键的次数，同时加一个心跳显示的点阵视觉效果，来烘托气氛，并呈现给玩家计数的频率。
暂设计5局3胜，一方3胜后进入锁定状态，播放音乐，直到使用复位键重新开始游戏为止。
使用复位键可以在任何状态下，将计分板清零，标志灯回到中心并重新进行倒计时开始新游戏。
3、说明：中间灯亮表示中线；最外侧灯亮表示该端获胜；数码管计数表示获胜次数；复位键使游戏重新开始；点阵在游戏开始时进行5秒的倒计时显示，同时在比赛期间显示心跳动画效果和双方按键的力度显示。
基于VHDL的乒乓游戏机的设计与仿真信息工程学院电子信息工程专业刘苏伦（20906022032）指导老师：赵年顺（硕士）摘要：VHDL是一种描述数字电子系统的语言，它源自美国政府的甚高速集成电路（VHSIC）计划。
人民迫切的需要一种标准语言来描述集成电路（IC）的结构和功能。
因此VHSIC硬件描述语言（VHDL）就应运而生了。
目前，VHDL已成为许多设计自动化工具普遍采用的标准化硬件描述语言。
VHDL语言功能强大、设计灵活、支持广泛、易于修改，具有很好的实用性。
EDA（Electronic Design Automation）技术是现代电子工程领域的一门新技术。
作为现在电子设计的核心，它依赖功能强大的计算机，在EDA工具软件平台上，对硬件描述语言HDL为系统逻辑描述手段完成的设计文件，自动的完成逻辑编译，逻辑化简，逻辑分割，逻辑综合，结构布局，以及逻辑优化和仿真测试，直至实现既定的电子线路系统功能。
本文设计的乒乓球游戏机是以Max+Plus II为软件平台，用VHDL硬件语言描述，通过Max+Plus II来实现乒乓球游戏的仿真。
关键词：VHDL；EDA；乒乓球游戏Design and Simulation of table tennis gamemachine based on VHDLLiu Sulun Director：Zhao NianshunAbstract：VHDL is a description language of digital electronic system, it originated from the United States government very high-speed integrated circuit (VHSIC) program. People urgently need a standard language to describe the integrated circuit (IC) structure and function. Therefore, the VHSIC hardware description language (VHDL) will emerge as the times require。
第7卷 第4期信息与电子工程Vo1．7，No．4 2009年8月INFORMATION AND ELECTRONIC ENGINEERING Aug．，2009文章编号：1672-2892(2009)04-0342-04VHDL元件的Simulink/Modelsim功能测试方法颜运强，吕高焕(中国工程物理研究院软件评测中心，四川绵阳 621900)摘 要：由于VHDL语言注重硬件行为描述，VHDL程序的测试方法与传统高级设计语言程序和汇编语言程序的测试方法不同。
VHDL程序测试向量的自动生成方法和覆盖率测试是其功能测试中的难点。
基于Matlab/Simulink的方法，将VHDL程序作为整个模型系统中的一个元件来考察，就其硬件环境进行建模，和Modelsim进行协同仿真。
该方法简化了测试流程，无需采用复杂的testbench编写方法，提高了测试的完整性。
关键词：协同仿真；VHDL组件；模型；测试中图分类号：TP311.5文献标识码：AFunctional testing method of VHDL component using simulink/modelsimYAN Yun-qiang，LV Gao-huan(Software Testing Center，China Academy of Engineering Physics, Mianyang Sichuan 621900，China)Abstract：The test method for VHDL program is different from that for the programs written in high level programming language or assembly language. The difficulty in the functional testing lies in theautomatic generation method of testing vectors and coverage testing. In this paper, the VHDL program istreated as a component in the model system and co-simulated with Modelsim software usingMatlab/Simulink. This method simplifies the testing flow and improves the testing integrity, in stead ofwriting complex testbench.Key words：c o-simulation；VHDL component；model；testing测试VHDL(Very-High-Speed Integrated Circuit Hardware Description Language)语言编写的元件(Component)时，测试用例和测试向量的设计和生成是测试过程中的关键部分，它不仅确定元件的覆盖率，还对元件设计中的可靠性问题有检测作用[1-3]。
Quartus II Simulation with VHDL DesignsThis tutorial introduces the basic features of the Quartus R II Simulator.It shows how the Simulator can be used to assess the correctness and performance of a designed circuit.Contents:Example CircuitUsing the Waveform EditorFunctional SimulationTiming SimulationUsing the Node FinderQuartus R II software includes a simulator which can be used to simulate the behavior and performance of circuits designed for implementation in Altera’s programmable logic devices.The simulator allows the user to apply test vectors as inputs to the designed circuit and to observe the outputs generated in response.In addition to being able to observe the simulated values on the I/O pins of the circuit,it is also possible to probe the internal nodes in the circuit.The simulator makes use of the Waveform Editor,which makes it easy to represent the desired signals as waveforms.Doing this tutorial,the reader will learn about:•Test vectors needed to test the designed circuit•Using the Quartus II Waveform Editor to draw the test vectors•Functional simulation,which is used to verify the functional correctness of a synthesized circuit•Timing simulation,which takes into account propagation delays due to logic elements and interconnecting wiringThis tutorial is aimed at the reader who wishes to simulate circuits defined by using the VHDL hardware de-scription language.An equivalent tutorial is available for the user who prefers the Verilog language.PREREQUISITESThe reader is expected to have access to a computer that has Quartus II software installed.The detailed examples in the tutorial were obtained using the Quartus II version8.0,but other versions of the software can also be used.1Example CircuitAs an example,we will use the adder/subtractor circuit shown in Figure1.The circuit can add,subtract,and accumulate n-bit numbers using the2’s complement number representation.The two primary inputs are numbers A=a n−1a n−2···a0and B=b n−1b n−2···b0,and the primary output is Z=z n−1z n−2···z0.Another input is the AddSub control signal which causes Z=A+B to be performed when AddSub=0and Z=A−B when AddSub=1.A second control input,Sel,is used to select the accumulator mode of operation.If Sel=0,the operation Z=A±B is performed,but if Sel=1,then B is added to or subtracted from the current value of Z. If the addition or subtraction operations result in arithmetic overflow,an output signal,Overflow,is asserted.To make it easier to deal with asynchronous input signals,they are loaded intoflip-flops on a positive edge of the clock.Thus,inputs A and B will be loaded into registers Areg and Breg,while Sel and AddSub will be loaded intoflip-flops SelR and AddSubR,respectively.The adder/subtractor circuit places the result into register Zreg.a a z 0z n 1–A =Z =b 0b n 1–B =SelAddSubOverflowFigure 1.The adder/subtractor circuit.The required circuit is described by the VHDL code in Figure 2.For our example,we use a 16-bit circuit as specified by n =16.Implement this circuit as follows:•Create a project addersubtractor .•Include a file addersubtractor.vhd ,which corresponds to Figure 2,in the project.For convenience,this file is provided in the directory DE2_tutorials \design_files ,which is included on the CD-ROM that accompanies the DE2board and can also be found on Altera’s DE2web pages.•Choose the Cyclone II EP2C35F672C6device,which is the FPGA chip on Altera’s DE2board.•Compile the design.LIBRARY ieee;USE ieee.std_logic_1164.all;−−Top-level entityENTITY addersubtractor ISGENERIC(n:INTEGER:=16);PORT(A,B:IN STD_LOGIC_VECTOR(n−1DOWNTO0);Clock,Reset,Sel,AddSub:IN STD_LOGIC;Z:BUFFER STD_LOGIC_VECTOR(n−1DOWNTO0);Overflow:OUT STD_LOGIC);END addersubtractor;ARCHITECTURE Behavior OF addersubtractor ISSIGNAL G,H,M,Areg,Breg,Zreg,AddSubR_n:STD_LOGIC_VECTOR(n-1DOWNTO0);SIGNAL SelR,AddSubR,carryout,over_flow:STD_LOGIC;COMPONENT mux2to1GENERIC(k:INTEGER:=8);PORT(V,W:IN STD_LOGIC_VECTOR(k-1DOWNTO0);Selm:IN STD_LOGIC;F:OUT STD_LOGIC_VECTOR(k-1DOWNTO0));END COMPONENT;COMPONENT adderkGENERIC(k:INTEGER:=8);PORT(carryin:IN STD_LOGIC;X,Y:IN STD_LOGIC_VECTOR(k-1DOWNTO0);S:OUT STD_LOGIC_VECTOR(k-1DOWNTO0);carryout:OUT STD_LOGIC);END COMPONENT;BEGINPROCESS(Reset,Clock)BEGINIF Reset=’1’THENAreg<=(OTHERS=>’0’);Breg<=(OTHERS=>’0’);Zreg<=(OTHERS=>’0’);SelR<=’0’;AddSubR<=’0’;Overflow<=’0’;ELSIF Clock’EVENT AND Clock=’1’THENAreg<=A;Breg<=B;Zreg<=M;SelR<=Sel;AddSubR<=AddSub;Overflow<=over_flow;END IF;END PROCESS;nbit_adder:adderkGENERIC MAP(k=>n)PORT MAP(AddSubR,G,H,M,carryout);multiplexer:mux2to1GENERIC MAP(k=>n)PORT MAP(Areg,Z,SelR,G);AddSubR_n<=(OTHERS=>AddSubR);H<=Breg XOR AddSubR_n;over_flow<=carryout XOR G(n−1)XOR H(n−1)XOR M(n−1);Z<=Zreg;END Behavior;...continued in Part bFigure2.VHDL code for the circuit in Figure1(Part a).−−k-bit2-to-1multiplexerLIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY mux2to1ISGENERIC(k:INTEGER:=8);PORT(V,W:IN STD_LOGIC_VECTOR(k−1DOWNTO0);Selm:IN STD_LOGIC;F:OUT STD_LOGIC_VECTOR(k−1DOWNTO0));END mux2to1;ARCHITECTURE Behavior OF mux2to1ISBEGINPROCESS(V,W,Selm)BEGINIF Selm=’0’THENF<=V;ELSEF<=W;END IF;END PROCESS;END Behavior;−−k-bit adderLIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_signed.all;ENTITY adderk ISGENERIC(k:INTEGER:=8);PORT(carryin:IN STD_LOGIC;X,Y:IN STD_LOGIC_VECTOR(k−1DOWNTO0);S:OUT STD_LOGIC_VECTOR(k−1DOWNTO0);carryout:OUT STD_LOGIC);END adderk;ARCHITECTURE Behavior OF adderk ISSIGNAL Sum:STD_LOGIC_VECTOR(k DOWNTO0);BEGINSum<=(’0’&X)+(’0’&Y)+carryin;S<=Sum(k−1DOWNTO0);carryout<=Sum(k);END Behavior;Figure2.VHDL code for the circuit in Figure1(Part b).2Using the Waveform EditorQuartus II software includes a simulation tool that can be used to simulate the behavior of a designed circuit. Before the circuit can be simulated,it is necessary to create the desired waveforms,called test vectors,to representthe input signals.It is also necessary to specify the outputs,as well as possible internal points in the circuit,which the designer wishes to observe.The simulator applies the test vectors to the model of the implemented circuit and determines the expected response.We will use the Quartus II Waveform Editor to draw the test vectors,as follows:1.Open the Waveform Editor window by selecting File>New,which gives the window shown in Figure3.Choose Vector Waveform File and click OK.Figure3.Need to prepare a newfile.2.The Waveform Editor window is depicted in Figure4.Save thefile under the name addersubtractor.vwf;note that this changes the name in the displayed window.In thisfigure,we have set the desired simulation to run from0to180ns by selecting Edit>End Time and entering180ns in the dialog box that pops up.Selecting View>Fit in Window displays the entire simulation range of0to180ns in the window,as shown.Resize the window to its maximum size.Figure4.The Waveform Editor window.3.Next,we want to include the input and output nodes of the circuit to be simulated.Click Edit>Insert>Insert Node or Bus to open the window in Figure5.It is possible to type the full hierarchical name ofa signal(pin)into the Name box,but it is easier to click on the button labeled Node Finder to open thewindow in Figure6.The Node Finder utility has afilter used to indicate what types of nodes are to be found.Since we are interested in input and output pins,set thefilter to Pins:all.Click the List button tofind the pin names as indicated on the left side of thefigure.Observe that the input and output signals A,B,and Z can be selected either as individual nodes(denoted by bracketed subscripts)or as16-bit vectors,which is a more convenient form.Figure5.The Insert Node or Bus dialogue.Figure6.Selecting nodes to insert into the Waveform Editor.Use the scroll bar inside the Nodes Found box in Figure6tofind the Clock signal.Click on this signal and then click the>sign in the middle of the window to add it to the Selected Nodes box on the right side of thefigure.Do the same for Reset,Sel,and AddSub.Then choose vectors A,B and Z,as well as the outputOverflow,in the same way(several nodes can be selected simultaneously in a standard Windows manner).Click OK to close the Node Finder window,and then click OK in the window of Figure5.This leaves a fully displayed Waveform Editor window,as shown in Figure7.If you did not select the nodes in the same order as displayed in Figure7,it is possible to rearrange them.To move a waveform up or down in the Waveform Editor window,click on the node name(in the Name column)and release the mouse button.The waveform is now highlighted to show the selection.Click again on the waveform and drag it up or down in the Waveform Editor.Figure7.The nodes needed for simulation.4.We will now specify the logic values to be used for the input signals during simulation.The logic values atthe outputs Z and Overflow will be generated automatically by the simulator.To make it easy to draw the desired waveforms,the Waveform Editor displays(by default)vertical guidelines and provides a drawing feature that snaps to these lines(which can otherwise be invoked by choosing View>Snap to Grid).Observe also a solid vertical line,which can be moved by pointing to its top and dragging it horizontally.This reference line is used in analyzing the timing of a circuit,as described later;move it to the time=0position.The waveforms can be drawn using the Selection Tool,which is activated by selecting the iconin the toolbar,or the Waveform Editing Tool,which is activated by the icon.In the instructions below, we will use the Selection Tool.To simulate the behavior of a large circuit,it is necessary to apply a sufficient number of input valuations and observe the expected values of the outputs.The number of possible input valuations may be huge,so in practice we choose a relatively small(but representative)sample of these input valuations.We will choosea very small set of input test vectors,which is not sufficient to simulate the circuit properly but is adequatefor tutorial purposes.We will use eight20-ns time intervals to apply the test vectors as shown in Figure8.The values of signals Reset,Sel,AddSub,A and B are applied at the input pins as indicated in thefigure.The value of Z at time t i is a function of the inputs at time t i−1.When Sel=1,the accumulator feedback loop is activated so that the current value of Z(rather than A)is used to compute the new value of Z.Time Reset Sel AddSub A B Zt0100000t10005418500t2001132631904t30000069t40017501200t501007000630t60100300007630t70100037630Figure8.The required testing behavior.The effect of the test vectors in Figure8is to perform the following computation:t0:Resett1:Z(t1)=0t2:Z(t2)=A(t1)+B(t1)=54+1850=1904t3:Z(t3)=A(t2)−B(t2)=132−63=69t4:Z(t4)=A(t3)+B(t3)=0+0=0t5:Z(t5)=A(t4)−B(t4)=750−120=630t6:Z(t6)=Z(t5)+B(t5)=630+7000=7630t7:Z(t7)=Z(t6)+B(t6)=7630+30000=37630(overflow)Initially,the circuit is reset asynchronously.Then for two clock cycles the output Z isfirst the sum and then the difference of the values of A and B at that time.This is followed by setting both A and B to zero to clear the contents of register Z.Then,the accumulator feedback path is tested in the next three clock cycles by performing the computationZ=A(t4)−B(t4)+B(t5)+B(t6)using the values of A and B shown above.We can generate the desired input waveforms as follows.Click on the waveform name for the Clock node. Once a waveform is selected,the editing commands in the Waveform Editor can be used to draw the desired mands are available for defining the clock,or setting the selected signal to0,1,unknown (X),high impedance(Z),don’t care(DC),and inverting its existing value(INV).Each command can be activated by using the Edit>Value command,or via the toolbar for the Waveform Editor.The Edit menu can also be opened by right-clicking on a waveform name.With the Clock signal highlighted,click on the Overwrite Clock icon in the toolbar.This leads to the pop-up window in Figure9.Enter the clock period value of20ns,make sure that the offset(phase)is0 and the duty cycle is50percent,and click OK.The desired clock signal is now displayed in the Waveform window.Figure9.Definition of the clock period,offset and duty cycle.We will assume,for simplicity of timing,that the input signals change coincident with the negative edges of the clock.To reset the circuit,set Reset=1in the time interval0to20ns.Do this by pressing the mouse at the start of the interval and dragging it to its end,which highlights the selected interval,and choosing the logic value1in the toolbar.Make Sel=1from100to160ns,and AddSub=1in periods40to60ns and80 to100ns.This should produce the image in Figure10.Figure10.Setting of test values for the control signals.5.Vectors can be treated as either octal,hexadecimal,signed decimal,or unsigned decimal numbers.Thevectors A,B,and Z are initially treated as ASCII codes.For our purpose it is convenient to treat them as signed decimal numbers,so right-click on A and select Properties in the pop-up menu to get to the window displayed in Figure11.Choose signed decimal as the radix,make sure that the bus width is16bits,and click OK.In the same manner,declare that B and Z should be treated as signed decimal numbers.Figure11.Definition of node properties.The default value of A is0.To assign specific values in various intervals proceed as follows.Press theArbitrary Value icon in the toolbar,to bring up the pop-up window in Figure12.Set20ns as the start time and40ns as the end time under Time range,enter the value54in Numeric or named value under Arbitrary value and click OK.Similarly,for the subsequent20-ns intervals set A to the values132, 0,750,and then0to the end.Set the corresponding values of B to1850,63,0,120,7000,30000,and0, to generate the waveforms depicted in Figure13.Observe that the outputs Z and Overflow are displayed as having unknown values at this time,which is indicated by a hashed pattern;their values will be determined during simulation.Save thefile.Figure12.Specifying a value for a multibit signal.Figure13.The specified input test vectors.Another convenient mechanism for changing the input waveforms is provided by the Waveform Editing tool,which is activated by the icon.When the mouse is dragged over some time interval in which the waveform is 0(1),the waveform will be changed to1(0).Experiment with this feature on signal AddSub.3Performing the SimulationA designed circuit can be simulated in two ways.The simplest way is to assume that logic elements and inter-connection wires are perfect,thus causing no delay in propagation of signals through the circuit.This is called functional simulation.A more complex alternative is to take all propagation delays into account,which leads to timing simulation.Typically,functional simulation is used to verify the functional correctness of a circuit as it is being designed.This takes much less time,because the simulation can be performed simply by using the logic expressions that define the circuit.3.1Functional SimulationTo perform the functional simulation,select Assignments>Settings to open the Settings window shown in Figure14.On the left side of this window click on Simulator Settings to display the window in Figure15, choose Functional as the simulation mode,and click OK.The Quartus II simulator takes the inputs and generatesthe outputs defined in the addersubtractor.vwffile.Before running the functional simulation it is necessary to create the required netlist,which is done by selecting Processing>Generate Functional Simulation Netlist.Figure14.Settings window.Figure15.Specifying the simulation mode.Figure16.The result of functional simulation.A simulation run is started by Processing>Start Simulation,or by using the icon.At the end of the simulation,Quartus II software indicates its successful completion and displays a Simulation Report illustrated in Figure16.As seen in thefigure,the Simulator creates waveforms for the outputs Z and Overflow.As expected, the values of Z indicate the correct sum or difference of the applied inputs one clock cycle later because of the registers in the circuit.Note that the last value of Z is incorrect because the expected sum of37630is too big to be represented as a signed number in16bits,which is indicated by the Overflow signal being set to1.In this simulation,we considered only the input and output signals,which appear on the pins of the FPGA chip.It is also possible to look at the behavior of internal signals.For example,let us consider the registered signals SelR,AddSubR,Areg,Breg,and Zreg.Open the addersubtractor.vwffile and activate the Node Finder window,as done for Figure6.Thefilter in Figure6specified Pins:all.There are several other choices.Tofind the registered signals,set thefilter to Registers:post-fitting and press List.Figure17shows the result.Select the signals SelR,AddSubR,Areg,Breg,and Zreg for inclusion in the addersubtractor.vwffile,and specify that Areg, Breg,and Zreg have to be displayed as signed decimal numbers,thus obtaining the display in Figure18.Save the file and simulate the circuit using these waveforms,which should produce the result shown in Figure19.Figure17.Finding the registered signals.Figure18.Inclusion of registered signals in the test.Figure19.The result of new simulation.3.2Timing SimulationHaving ascertained that the designed circuit is functionally correct,we should now perform the timing simulation to see how well it performs in terms of speed.Select Assignments>Settings>Simulator Settings to get to the window in Figure15,choose Timing as the simulation mode,and click OK.Run the simulator,which should produce the waveforms in Figure20.Observe that there are delays in loading the various registers as well as longer delays in producing valid signals on the output pins.Figure20.The result of timing simulation.As an aid in seeing the actual values of the delays,we can use the reference line.Point to the small square handle at the top of the reference line and drag it to the rising edge of thefirst AddSubR pulse,at which time the reg-isters are also loaded,as indicated in thefigure.(To make it possible to move the reference line to any point in the waveform display,you may have to turn off the feature View>Snap on Grid.)This operation places the reference line at about the53.1ns point,which indicates that it takes3.1ns to load the registers after the rising edge of the clock(which occurs at50ns).The output Z attains its correct value some time after this value has been loaded into Zreg.To determine the propagation delay to the output pins,drag the reference line to the point where Z becomes valid.This can be done more accurately by enlarging the displayed simulation waveforms by using the Zoom Tool.Left-click on the display to enlarge it and right-click to reduce it.Enlarge the display so thatit looks like the image in Figure21.(After enlarging the image,click on the Selection Tool icon.Position the reference line where Z changes to1904,which occurs at about57.2ns.The display indicates that the propagation delay from register Zreg to the output pins Z is57.2−53.1=4.1ns.It is useful to note that even before we performed this simulation,the Quartus II timing analyzer evaluated various delays in the implemented circuit and reported them in the Compilation Report.From the Compilation Report we can see that the worst case tco(Clock to Output Delay)for the Z output(pin z13)was estimated as7.349ns;this delay can be found by zooming into the simulation results at the point where Z changes to the value7630.Figure21.An enlarged image of the simulated waveforms.In this discussion,we have used the numbers obtained during our simulation run.The user is likely to obtain somewhat different numbers,depending on the version of Quartus II software that is used.4Using the Node FinderWe have used the Node Finder utility to select the signals needed for simulation.We set thefilter to Pins:all in section2and to Registers:post-fitting in section3tofind the desired signals.In large designs it may be difficult tofind a particular signal if it is not covered by a specificfilter.The Quartus II compiler may modify the names of internal signals,which can make their identification by the user difficult.Moreover,the compiler may implement the circuit such that a particular signal does not even appear as a separate wire.Suppose we want to look at the signal G,which is one of the inputs to the adder circuit in Figure1.This signal will not be found by using thefilters mentioned above.It will also not be found by the Post-synthesis or Post-compilationfilters.However,it is possible to force the Quartus II compiler to keep specially identified signals (wires)and their original names.This is done by associating an attribute called keep with the desired signal.For example,in the VHDL code in Figure2we can include the statements:attribute keep:boolean;attribute keep of G:signal is true;Then,the Post-synthesis and Post-compilationfilters willfind this signal.It is important to note that the inclusion of keep attribute has no effect on the functional behavior of the designed circuit,but it may have an impact on the detailed implementation of the compiled circuit and thus its timing behavior.Therefore,the keep attribute should not be removed after the circuit has been successfully simulated.Copyright c 2008Altera Corporation.All rights reserved.Altera,The Programmable Solutions Company,the stylized Altera logo,specific device designations,and all other words and logos that are identified as trademarks and/or service marks are,unless noted otherwise,the trademarks and service marks of Altera Corporation in the U.S.and other countries.All other product or service names are the property of their respective holders.Altera products are protected under numerous U.S.and foreign patents and pending applications,mask work rights,and copyrights.Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty,but reserves the right to make changes to any products and services at any time without notice.Altera assumes no responsibility or liability arising out of the application or use of any informa-tion,product,or service described herein except as expressly agreed to in writing by Altera Corporation.Altera customers are advised to obtain the latest version of device specifications before relying on any published infor-mation and before placing orders for products or services.This document is being provided on an“as-is”basis and as an accommodation and therefore all warranties,rep-resentations or guarantees of any kind(whether express,implied or statutory)including,without limitation,war-ranties of merchantability,non-infringement,orfitness for a particular purpose,are specifically disclaimed.。
基于VHDL的过采样模拟数字转换器建模ROBERT BARANIECKI, PRZEMYSAW DAIBROWSKI ,AND KONRAD HEJN摘要：本文介绍了过采样SD模拟数字转换器在行为层次的VHDL模型成立。
VHDL语言已被要紧用于数字电路设计，也能够适用于某些混合信号集成电路。
该模型的模拟部份是尽可能简单，并只包括必要的参数，以便确信潜在的第一个转换器。
该模型的数字部份中描述了可合成的VHDL语言子集和其参数依照字长和类型的算术应用.验证进程的转换模型也显示出来。
它是由VHDL语言模拟器和一个后置的工具来展开FFT 。
仿真结果封锁性地证明了所提出的设计方式的效率。
关键词：Sigma - Delta调制器；VHDL语言；行为建模与仿真；RTL综合1 介绍本文有制定混合信号集成电路的行为模型的两个大体缘故。
第一个缘故是他们的高复杂度。
例如：一个过采样Σ - Δ模拟数字转换器（Σ△模数转换器）组成的模拟数字Σ△调制器和可变数字滤波器称为毁灭器。
这种混合信号电路的完全模拟时CPU超级密集，尤其是若是咱们尝试适用于类似SPICE的等同电路模拟器。
另外，混合信号模块的晶体管模型不具有设计进程的开始时期。
第二个缘故是涉及到自上而下的设计方式，其建议验证了该模型设计进程中每一个层次的水平。
因此，一个有效的解决方法似乎是利用行为（离散时刻）模拟模型。
通过对它们，设计者能够快速验证任何正在审议中的模型系统。
不幸的是，适当的工具来做到这一点仍然无法利用。
军刀模拟或ELDO形成Anacad比起数字电路更适合于模拟电路，而且在此期间的VHDL -AMS仍在进展中。
因此，咱们必需采纳_SIGNAL_PROCESSING _WORKSYSTEM （表面等离子体波）和事件驱动模拟器Synopsys 以进行行为建模与过采样Σ△模数转换器的仿真。
VHDL语言的IEEE 已经成为它们之间的界面。
过采样Σ△模数转换器的低级模型是在表面等离子体波环境中创建的。
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY MEALY12 ISPORT ( CLK ,DA TAIN,RESET : IN STD_LOGIC;Q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0));END MEALY12;ARCHITECTURE behav OF MEALY12 ISTYPE states IS (st0, st1, st2, st3,st4);SIGNAL STX : states ;BEGINCOMREG : PROCESS(CLK,RESET) BEGIN--决定转换状态的进程IF RESET ='1' THEN STX <= ST0;ELSIF CLK'EVENT AND CLK = '1' THEN CASE STX ISWHEN st0 => IF DA TAIN = '1' THEN STX <= st1;Q <= "10000" ;else Q<="01010" ;END IF;WHEN st1 => IF DA TAIN = '0' THEN STX <= st2;Q <= "10111" ;else Q<="10100" ; END IF;WHEN st2 => IF DA TAIN = '1' THEN STX <= st3; Q <= "10101" ;else Q<="10011" ;END IF;WHEN st3=> IF DA TAIN = '0' THEN STX <= st4; Q <= "11011" ;else Q<="01001" ;END IF;WHEN st4=> IF DA TAIN = '1' THEN STX <= st0; Q <= "11101" ;else Q<="01101" ;END IF;WHEN OTHERS => STX <= st0; Q<="00000" ;END CASE ;END IF;END PROCESS COMREG ;END behav;（例5-5，双进程时序图）（单进程时序图）要求一：表达的是moore型状态机，特点是输出仅为当前状态的函数。
A VHDL-based HW/SW cosimulation of communicationsystemsMasoud Sabaei a ,Mehdi Dehghan a ,Karim Faez a ,Majid Ahmadi b,*aDepartment of Electrical Engineering,Amirkabir University of Technology,Hafez Ave.,Tehran,15914,Iran bDepartment of Electrical Engineering,College of Engineering Science,University of Windsor,401Sunset Avenue,Windsor,Ontario,Canada N9B 3P4Received 13August 1999;received in revised form 13April 2000;accepted 25May 2000AbstractIn this paper,we introduce homogeneous cosimulation method,which is suitable for modeling and simulation of systems comprising hardware (HW)and software (SW)components.In this method,a hardware description language with embedded programming capabilities (like VHDL)is used to model both HW/SW parts at any desired level of abstraction.Because of platform homogeneity,no sophisticated coordinator interface between HW/SW models is required,and also the ®nal system can be constructed from these models easily and rapidly using CAD tools.We have applied this method to ISDN user±net-work interface and discussed about its bene®ts and drawbacks.Ó2001Elsevier Science Ltd.All rights reserved.Keywords:Hardware and Software codesign;Hardware-level simulation;Heterogeneous cosimulation;Homogeneous cosimulation;VHDL;ISDN1.IntroductionAs the complexity of digital system grows,the use of e cient methods for designing,testing,verifying,and synthesizing of systems becomes necessary.Most digital systems consist of hard-ware (HW)and software (SW)cooperating subsystems.In traditional design methodology,the system is divided into HW/SW subsystems.These subsystems are separately designed by di erent groups and ®nally integrated to create the true system.This methodology has several inherent*Corresponding author.Tel.:+1-519-253-4232,ext.2576;fax:+1-519-971-3695.E-mail address:ahmadi@engn.uwindsor.ca (M.Ahmadi).0045-7906/01/$-see front matter Ó2001Elsevier Science Ltd.All rights reserved.PII:S0045-7906(00)00026-4drawbacks.For example,the development of the main part of SW would be postponed until a prototype HW is available.This delay not only prolongs system design life cycle but also makes SW designers adjust their work to the pre-designed HW.Therefore,the traditional design methods are no longer e cient for HW/SW system design.Codesign methodology,on the other hand,could reduce these drawbacks.In this method,the HW/SW subsystems are developed concurrently,thus shortening the system design life cycle and eliminating redesign overheads[1]. In codesign methodology,the HW/SW subsystems will be modeled simultaneously and fol-lowed by a simulation process which enables the removal of possible design errors to yield the ®nal system with the aid of CAD tools.So,the simultaneous simulation of HW/SW models is a vital stage in the codesign methodology.In this paper,we are going to introduce a cosimulation strategy,called homogeneous simulation,suitable for modeling HW/SW communication systems. The remaining part of this paper is organized as follows:Section2describes the basis of co-simulation methodology and introduces three di erent simulation methods for HW/SW com-munication systems.Homogeneous cosimulation method is explained in the same section in greater details.The ISDN user±network interface(UNI),as a typical communication system,is modeled by using this method in Section3.Section4shows the experimental results obtained from homogeneous cosimulation of the ISDN UNI model.Section5summarizes our approach and shows some aspects of future work.2.Cosimulation methodologyIn order to simulate a communication system comprising HW/SW components,®rst,system operation must be modeled at the highest level of abstraction(behavioral model)and only then the system components can be developed simultaneously.A high level view of a communication system is drawn in Fig.1.Most of the e ort in system development is focused on the design of the associated HW,and on the implementation of the SW executing processing tasks.It has been presumed that the host computer,responsible for executing the system SW,is available and does not require remodeling.Cosimulation methods should provide a design,modeling,and simulation environment for developing HW/SW subsystems simultaneously.Although most computer programming languages are suitable for modeling and developing SW components,they could not model the HW parts e ciently.For modeling HW components, hardware description languages(HDLs)are the best choice.Not only HDLs are able to describe HW parts at all desired level of abstraction,but also they can facilitate and accelerate the other design phases such as testing,verifying,and synthesizing.Most HDLs,however,do not supportM.Sabaei et al./Computers and Electrical Engineering27(2001)333±343335 powerful programming structures for SW modeling.Consequently,each HW/SW component must be modeled using appropriate tools.In order to develop models of the HW and SW si-multaneously,an interface is needed to provide a communication path between the HW and SW models and synchronize their operations.Hence,an HW/SW cosimulation environment must include the following simulation tools[2±4]:1.An HDL,such as VHDL,for modeling HW components.2.A software description language(SDL),such as a programming language,for writing SW com-ponents.3.A proper synchronization tool for interfacing HW/SW models in order to allow simultaneous simulation.Three di erent approaches are possible for HW/SW cosimulation depending on whichever tools are being used as on how detailed simulation is required.1.HW-level simulation:At the lowest level,HW/SW system can be treated as a sole HW system. Thus,an HDL can model the whole system by itself.2.Heterogeneous cosimulation:In this approach,SW is written using any programming language and HW is modeled using a HDL.An interface coordinator is then needed to simulate HW/SW components simultaneously.3.Homogeneous cosimulation:An HDL with embedded programming capabilities can be used to model both HW and SW components.Hence,the simulation environment in this case will be homogeneous and simple.In the following paragraphs,we describe each approach in detail.2.1.Hardware-level simulationBy carefully observing how a processor executes a SW routine,we can simplify the HW/SW components of a system to a purely HW set,containing machine instructions within its memory location.In essence,SW,developed by any programming language,will be translated into bi-nary coded machine instructions and stored in the memory.The processor iteratively fetches, decodes,and executes these machine instructions in order to run the SW[1,2].From this point of view,an HW/SW system can be simulated only at HW level.In this approach,called HW-level simulation,system SW could be written by a programming language(such as C)but its object code stored in memory represents SW model(as shown in Fig.2).Although the modeling of(to-be-designed)HW is the main aim,the host computer should be modeled to execute the machine instructions(SW model)at the lowest level too.An HDL(such as VHDL)can be used to model both parts.The HW-level simulation method can simulate the exact operation of the®nal system,and evaluate the system performance parameters precisely.However,this approach has the following disadvantages:1.To simulate a communication system,not only the(to-be-designed)HW,but also at the same time the host computer itself has to be modeled in su cient details in order to fetch,decode, and execute machine instructions.2.The development of HW/SW models at the lowest level of abstraction is very time consuming.3.Since the SW must be simulated at machine instruction level,the simulation run-time is very long.Consequently,this approach is not suitable for system level modeling and simulation.2.2.Heterogeneous cosimulationIt is quite logical that each of HW/SW component be modeled by separate and suitable tools.In other words,a better approach is to model the system SW by a conventional programming language such that the ®nal SW can be easily implemented using this model.The HW will be modeled by an HDL,enriched with appropriate tools for rapid HW prototyping.In this way,the ®nal system can be constructed from the system models with minimum e orts.In order to simu-late the heterogeneous HW/SW models simultaneously,a coordinator interface is needed to schedule the events communicated between HW/SW models (as shown in Fig.3).Since theHW/336M.Sabaei et al./Computers and Electrical Engineering 27(2001)333±343SW components are modeled in di erent environments,the simulation time unit for HW and SW is di erent.Therefore,the design and implementation of this coordinator interface is very com-plicated [2±4].2.3.Homogeneous cosimulationMost HDLs can describe a system's operation at the low level which is suitable only for modeling HW components.However,if an HDL has the ability to model a system at any desired level of abstraction and also has a set of powerful data structures as well as programming con-structions,it can be used to model both HW/SW components by itself.VHDL is a popular HDL which has all the above capabilities [5].Therefore,VHDL is the only means by which any HW/SW system can be modeled and simulated (as shown in Fig.4).We have called this approach homogeneous cosimulation which has the following advantages:1.Both HW and SW can be modeled at any level of abstraction (behavioral,structural,or oper-ational).2.Because both HW/SW components are modeled and simulated in a single environment,no co-ordinator interface is needed.This is in contrast to heterogeneous cosimulation methodology.3.Both VHDL and communication systems'software are inherently event driven.Thus,the SW model can be constructed by VHDL easily and rapidly [6].4.In contrast to HW-level simulation,the host computer modeling is no longer required.This approach has some drawbacks that need to be resolved by further works.For example,although there are many useful CAD tools for rapid HW prototyping from VHDL based HW model,as yet no practical CAD tool (such as compiler)has been developed for converting VHDL based SW model to an executable one.Also,this approach requires the estimation of an approximate processing time for each SW block such that the stimulated SW run-time will in-dicate the actual SW run-time.As the estimated run-time for each process block of SW modelisM.Sabaei et al./Computers and Electrical Engineering 27(2001)333±343337338M.Sabaei et al./Computers and Electrical Engineering27(2001)333±343more accurate,the performance parameters of system are evaluated more precisely in simulation phase.In Section3,we represent the modeling and simulation of ISDN UNI(as a typical commu-nication system)by homogeneous cosimulation strategy.3.Homogeneous cosimulation of ISDN UNIWe consider ISDN UNI as a typical communication system.This interface consists of several functional units with speci®c functions under certain protocols as shown in Fig.5[7].The network termination type1(NT1)unit terminates the physical connection between user equipment and ISDN local exchange.The network termination type2(NT2)unit is responsible for switching, multiplexing,and concentrating calls at the user side.The terminal equipment type1(TE1)is an ISDN terminal with the capability to support ISDN protocols.The terminal adapter(TA)unit converts an incompatible ISDN terminal(TE2)to a compatible one(TE1).A reference point is de®ned as a communication path between two adjacent functional units.ITU-T has standardized the ISDN protocols for UNI.This interface is an HW/SW system.Its HW components consist of TE1and NT1/2boards,which are attached to a host computer.The host computer executes UNI SW.This SW is responsible for processing incoming/outgoing calls according to ITU-T recom-mendations.In these recommendations,a layer structure is proposed for UNI as follows:·Physical layer:This layer is responsible for transmitting and receiving data in the form of elec-trical signals according to ITU-T I.43Ârecommendation series[8].·Data link layer:This layer is similar to the second layer of open systems interconnection(OSI) reference model and supports link access procedures on the D-channel(LAPD)protocol ac-cording to ITU-T I.44Ârecommendation series[9,10].·Network layer:This layer is similar to the third layer of OSI reference model and supports ISDN signaling functions according to ITU-T I.45Ârecommendation series[11±13].In this paper,the model of UNI system is developed based on functional block diagram as shown in Fig.6.The UNI HW comprising telecommunication chips is included in physical layer, while the other functional blocks make up UNI SW.Each block is modeled according to SDLs developed based on ITU-T recommendations and implementation considerations.Each SW block behaves like a®nite state machine(FSM)[6].Thus,it waits in a state until it detects an incomingevent in its inputs.By processing this event,the SW block may make state transition,modify localdata,and send some events to other blocks.Because of the event-driven nature of each SW block,it can be modeled by a PROCESS block structure in VHDL [5].Fig.7shows the general model of SW blocks in VHDL.PROCESS blocks in VHDL are always active and their instructions are running until they encounter a WAIT instruction.Therefore,a WAIT instruction is placed at the end of each PROCESS block to halt the process until an event arrives.In our homogeneous approach,both HW and SW components are modeled only by VHDL.Thus,no complicated coordinator interface is needed for cosimulating these models.In other words,HW and SW models can communicate the events among themselvesdirectly.Fig.7.VHDL based general model of SW blocks.M.Sabaei et al./Computers and Electrical Engineering 27(2001)333±343339340M.Sabaei et al./Computers and Electrical Engineering27(2001)333±3434.Simulation resultsIn this work,we were pursuing two main objectives for simulating ISDN UNI model as fol-lows:1.Veri®cation of each HW/SW component operation.2.Approximate measurement of system performance parameters.To achieve these objectives,the system model was simulated under various commands issued by the user command/response interface of TE1(as shown in Fig.6)requesting establishment,release, suspension,and resumption of multiple incoming/outgoing calls.In response to each command,a signaling procedure is initiated at the call control unit and the corresponding response will be announced to users through user command/response interface.During this signaling procedure, several events are generated or processed by each HW or SW unit,and each event will be logged in an output®le.All the logged events contain information such as generation time,process time, source,destination,and type of event.The overall system operation can be veri®ed by examining the transactions on the user command/response interface.Furthermore,the exact operation of each unit can be veri®ed by tracing generated/processed events belonging to speci®c calls.For example,Table1shows the logged generated/processed events at the data link layer unit during establishment of an acknowledged logical link.Tracing these logged events(Table1)will show the conformity between data link layer operation and ITU-T recommendations.The system performance parameters are estimated using simulation results obtained from operation of the model under various circumstances with di erent tra c loads.Some of these performance parameters are as follows:Table1Logged events during logical link establishmentTime(l s)Receiver layer Producer layer Event type5000Data link Network DL a-establish-request 5200Data link management Data link MDL b-assign-indication 5500Data link Data link management MDL-unit-data-request(identity request) 5700Data link Data link UI c-frame-queued-up 6000Physical Data link UI-command(identityrequest)20000Data link Physical UI-command(identityassigned)20200Data link management Data link MDL-unit-data-indica-tion(identity assigned) 20400Data link Data link management MDL-assign-request 20600Timer Data link Start timer T200 20700Network Data link DL-establish-con®rm DL±data link.b MDL±management of data link.c UI±unnumbered references.M.Sabaei et al./Computers and Electrical Engineering27(2001)333±3433411.Input queue length of each SW block.2.The approximate amount of main memory needed for each SW block.3.Quality of service parameters such as average response time to process a requested call,and probability of call blocking due to overloaded queues.Based on these simulation results,the appropriate HW architecture for the host computer in each functional device was advised.For example,to implement the NT1/2device,a dual processor architecture(2Â80186-20MHz)with shared memory(64KB,dual port memory)was shown to be su cient.One processor was assigned for input/output handling while the other was assigned for call processing.The SW part of each device was obtained by translating the VHDL SW model to C program,manually.We are working on developing a VHDL to C compiler in order to facilitate the SW development.In cooperation with Iran telecommunication research center(ITRC),the obtained results were used to develop prototype ISDN UNI interfaces such as TE1,TA,NT1,and NT2.5.Conclusion and future workIn this paper,the need for HW/SW cosimulation was discussed in su cient details.Then a cosimulation method,called the homogeneous cosimulation,was introduced in which both HW/ SW were modeled by VHDL.This method was applied to ISDN UNI as a typical communication system comprising HW and SW components.The functionality of each component was veri®ed by simulating system model under various conditions.Homogeneous cosimulation eliminates the need for modeling host computer operation,and provides for a single platform to model and simulate HW/SW components.However,there re-main some problems with this method that must be resolved by further work[2,3].1.The amount of time required by each SW block to perform its operation has to be estimated. However,the more the accuracy of the estimated time,the better the simulation results will represent the real system operation.The main question is how this estimation can be performed.2.As yet,there is no compiler capable of translating a VHDL-based SW model into a set of programming language instructions.If such a compiler is designed,the true system can be easily constructed from the system model[6].References[1]Buchenrieder K,Sedlmeier A,Veith C.HW/SW Co-Design with PRAMs using CODES,in Proceeding ofCHDL'93,1993.p.55±68.[2]Loucks VM,Agnew DG.Experiences in Real-Time Hardware±Software Co-Simulation,in Proceeding of MakingVHDL a Commercial Reality,1993.p.47±57.[3]Valderrama CA,Changuel A,Raghavan PV,Abid M,Ismail TB,Jerraya AA.A Uni®ed Model for Co-simulationand Co-synthesis of Mixed Hardware/Software Systems.European Design and Test Conference,1995.p.180±4.[4]Kreiner C,Steger C,Weiss R.A Hardware/Software Cosimulation Environment for DSP Applications.EuromicroConference,vol.1,1999.p.492±5.[5]Navabi Z.VHDL:Analysis and Modeling of Digital Systems,2nd ed.New York:McGraw-Hill;1997.[6]GlunzW,Kruse T,Rossel T,Monjau D.Integrating SDL and VHDL for System Level Hardware Design,in Proceeding of CHDL'93,1993.p.175±92.[7]Kessler GC.ISDN Concepts,Facilities,and Services,3rd ed.New York:McGraw-Hill,1996.[8]ITU-T Rec.I.430,Basic User-Network Interface ±Layer 1Speci®cation,Nov 1995.[9]ITU-T Rec.Q.920,Digital Subscriber Signalling System No.1(DSS1)±ISDN User-Network Interface Data Link Layer ±General Aspects,''Helsinki,March 1993.[10]ITU-T Rec.Q.921,ISDN User-Network Interface Data Link Layer Speci®cation,Helsinki,March 1993.[11]ITU-T Rec.Q.930,Digital Subscriber Signalling System No.1(DSS1)±ISDN User-Network Interface Layer 3±General Aspects,Helsinki,March 1993.[12]ITU-T Rec.Q.931,Digital Subscriber Signalling System No.1(DSS1)±ISDN User-Network Interface Layer 3Speci®cation for Basic Call Control,Helsinki,March 1993.[13]ITU-T Rec.Q.932,Digital Subscriber Signalling System No.1(DSS1)±Generic Procedures for The Control ofISDN Supplementary Services,Helsinki,March1993.Dr.M.Ahmadi received his B.Sc.degree in electrical engineering from Arya Mehr University in Tehran,Iran and Ph.D.in electrical engineering form Imperial College of Science and Technology,London University,London,England in 1970and 1977,respectively.Dr.Ahmadi has been Professor in electrical engineering,University of Windsor since 1980.His area of interests include digital signal processing,pattern recognition,and neural network.He has published over 280papers in the above areas.Dr.Ahmadi is currently an associate editor of the Journals of Pattern Recognition,Circuit,Systems,Computers and Computers in ElectricalEngineering.Mehdi Dehghan received his B.Sc.degree from University of Science and Technology,Tehran,Iran,and his M.Sc.degree from Amirkabir University of Technology,Tehran,Iran,all in the ®eld of computer engineering in 1992and 1995,respectively.Since 1995,he has been a Ph.D.candidate in electrical engineering at Am-irkabir University of Technology,Tehran,Iran.He has held a visiting research position at University of Windsor,Ontario,Canada (1999±2000).His research interests include high-speed networks,hardware/software co-design,pattern recognition,machinevision.Masoud Sabaei received his B.Sc.degree from Esfahan University of Technology,Esfahan,Iran,and his M.Sc.degree from Amirkabir University of Technology,Tehran,Iran,all in the ®eld of computer engineering in 1992and 1995,respectively.Since 1995,he has been a Ph.D.candidate in electrical engineering at Am-irkabir University of Technology,Tehran,Iran.He has held a visiting research position at University of Windsor,Ontario,Canada (1999±2000).His research interests are in the areas of telecommunication network management,HW/SW codesign,and high-speed telecommunication networks.342M.Sabaei et al./Computers and Electrical Engineering 27(2001)333±343Karim Faez was born in Semnan,Iran.He received his B.S.degree in electrical engineering from Tehran Polytechnic University as the ®rst rank in June 1973,and his M.S.and Ph.D.degrees in computer science from University of California,at Los Angeles UCLA in 1977and 1980,respectively.Dr.Faezwas with Iran Telecommunication Research Center (1981±1983)before joining Amirkabir University of Technology (Teh-ran Polytechnic)in Iran,where he is Professor of electrical engineering.His research interests are in pattern recognition,image processing,neural networks,signal processing,Farsi handwriting processing,earthquake signal processing,fault tolerant system design and hardware design.M.Sabaei et al./Computers and Electrical Engineering 27(2001)333±343343。
