基于FPGA的等精度数字频率计的设计中英文翻译中文译文：数字频率计的介绍数字频率计是通信设备、音、视频等科研生产领域不可缺少的测量仪器。
采用Verilog HDL编程设计实现的数字频率计，除被测信号的整形部分、键输入部分和数码显示部分外，其余全部在一片FPGA芯片上实现。
整个系统非常精简，且具有灵活的现场可更改性。
1 等精度测频原理频率的测量方法主要分为2 种方法:(1) 直接测量法, 即在一定的闸门时间内测量被测信号的脉冲个数。
(2) 间接测量法, 例如周期测频法、V F 转换法等。
间接测频法仅适用测量低频信号。
基于传统测频原理的频率计的测量精度将随被测信号频率的下降而降低, 在实用中有较大的局限性, 而等精度频率计不但具有较高的测量精度, 而且在整个频率区域能保持恒定的测试精度。
频率测量方法的主要测量预置门控信号GATE是由单片机发出，GATE的时间宽度对测频精度影响较少，可以在较大的范围内选择，只要FPGA中32 b计数器在计100 M信号不溢出都行，根据理论计算GATE的时间宽度Tc可以大于42．94 s，但是由于单片机的数据处理能力限制，实际的时间宽度较少，一般可在10～0．1 s间选择，即在高频段时，闸门时间较短；低频时闸门时间较长。
这样闸门时间宽度Tc依据被测频率的大小自动调整测频，从而实现量程的自动转换，扩大了测频的量程范围；实现了全范围等精度测量，减少了低频测量的误差。
本设计频率测量方法的主要测量控制框图如图1 所示。
图1 中预置门控信号GA TE 是由单片机发出, GA TE的时间宽度对测频精度影响较少, 可以在较大的范围内选择, 只要FPGA 中32 b 计数器在计100M 信号不溢出都行, 根据理论计算GA TE 的时间宽度T c 可以大于42194s, 但是由于单片机的数据处理能力限制, 实际的时间宽度较少, 一般可在10～011 s 间选择, 即在高频段时,闸门时间较短; 低频时闸门时间较长。
这样闸门时间宽度T c 依据被测频率的大小自动调整测频, 从而实现量程的自动转换, 扩大了测频的量程范围; 实现了全范围等精度测量, 减少了低频测量的误差。
2 频率计的实现等精度测频的实现方法。
可简化为CNT1和CNT2是两个可控计数器，标准频率(f )信号从CN F1的时钟输入端cI K输入，经整形后的被测信号(f )从CNT2的时钟输入端cI K输入。
每个计数器中的CEN输入端为使能端，用来控制计数器计数。
当预置闸门信号为高电平(预置时间开始)时。
被测信号的上升沿通过D 触发器的输入端，同时启动两个汁数器计数；同样，当预置闸门信号为低电平(预置时间结束)时，被测信号的上升沿通过D触发器的输出端，使计数器停止计数。
3 频率计的位数及相关指标位数：同时最多能显示的数字位数。
平常计数式的8位频率计只有几百元就可买到。
对于高精度的测量，9位刚刚开始，11位算中等，13位才能算比较高级。
溢出位：把溢出位算进去的总等效位。
有些频率计带有溢出功能，即把最高位溢出不显示而只显示后面的位，以便达到提高位数的目的。
这里个别指标是估计值。
速度：即每秒能出多少位。
有了高位数的但测量特别慢也失去了意义。
平常计数式的8位频率计，测量10MHz信号、1秒闸门能得到10,000,000Hz，这实际上才是7位（位数等于取常用对数后的值），要想得到8位，需要10秒闸门；要想得到9位，需要100秒闸门，依次类推，即便显示允许，11位需要10000秒的测量时间了。
但无论如何，还是每秒7位。
因此，要想快速得到高位数则必须高速度。
分辨：这就像一个电压表最小可以分辨出多大的电压的指标是类似的，越小越好，单位ps（皮秒）。
1000ps=1ns。
假设你用1ns的频率计要分辨出1e-12的误差，就需要1ns/1e-12=1000秒的时间。
而假设你有另外一个频率计的分辨是100ps，那么测量时间就可以缩短10倍为100秒，或者可以在相同的1000秒下测量出1e-14的误差。
4 时间频率测量相比传统的电路系统设计方法，EDA技术采用VHDL语言描述电路系统，包括电路的结构、行为方式、逻辑功能及接口。
Verilog HDL具有多层次描述系统硬件功能的能力，支持自顶向下的设计特点。
设计者可不必了解硬件结构。
从系统设计入手，在顶层进行系统方框图的划分和结构设计，在方框图一级用Ver-ilog HDL对电路的行为进行描述，并进行仿真和纠错，然后在系统一级进行验证，最后再用逻辑综合优化工具生成具体的门级逻辑电路的网表，下载到具体的FPGA器件中去，从而实现FPGA的设计。
时间频率测量是电子测量的重要领域。
频率和时间的测量已越来越受到重视，长度、电压等参数也可以转化为与频率测量有关的技术来确定。
本文通过对传统的多周期同步法进行探讨，提出了多周期同步法与量化时延法相结合的测频方法。
最简单的测量频率的方法是直接测频法。
直接测频法就是在给定的闸门信号中填入脉冲，通过必要的计数电路，得到填充脉冲的个数，从而算出待测信号的频率或周期。
在直接测频的基础上发展的多周期同步测量方法，在目前的测频系统中得到越来越广泛的应用。
多周期同步法测频技术的实际闸门时间不是固定的值，而是被测信号的整周期倍，即与被测信号同步，因此消除了对被测信号计数时产生的±1个字误差，测量精度大大提高，而且达到了在整个测量频段的等精度测量，在时频测量方法中，多周期同步法是精度较高的一种，但仍然未解决±1个字的误差，主要是因为实际闸门边沿与标频填充脉冲边沿并不同步Tx=N0T0-△t2+△t1，如果能准确测量出短时间间隔Δt1和Δt2，也就能够准确测量出时间间隔Tx，消除±1个字的计数误差，从而进一步提高精度。
为了测量短时间间隔Δt1和Δt2，通常使用模拟内插法或游标法与多周期同步法结合使用，虽然精度有很大提高，但终未能解决±1个字的误差这个根本问题，而且这些方法设备复杂，不利于推广。
要得到精度高，时间响应快，结构简单的频率和时间测量方法是比较困难的。
从结构尽量简单同时兼顾精度的角度出发，将多周期同步法与基于量化时延的短时间间隔测量方法结合，实现了宽频范围内的等精度高分辨率测量。
量化时延法测短时间间隔光电信号可以在一定的介质中快速稳定的传播，且在不同的介质中有不同的延时。
通过将信号所产生的延时进行量化，实现了对短时间间隔的测量。
其基本原理是“串行延迟，并行计数”，而不同于传统计数器的串行计数方法，即让信号通过一系列的延时单元，依靠延时单元的延时稳定性，在计算机的控制下对延时状态进行高速采集与数据处理，从而实现了对短时间间隔的精确测量。
量化时延思想的实现依赖于延时单元的延时稳定性，其分辨率取决于单位延时单元的延迟时间。
作为延时单元的器件可以是无源导线，有源门器件或其他电路。
其中，导线的延迟时间较短(接近光速传播的延迟)，门电路的延迟时间相对较长。
考虑到延迟可预测能力，最终选择了CPLD器件，实现对短时间间隔的测量。
将短时间间隔的开始信号送入延时链中传播，当结束信号到来时，将此信号在延时链中的延时状态进行锁存，通过CPU读取，判断信号经过的延时单元个数就可以得到短时时间间隔的大小，分辨率决定于单位延时单元的延时时间。
一般来讲，为了测量两个短时间间隔，使用两组延时和锁存模块，但实际上，给定的软件闸门时间足够大，允许CPU完成取数的操作，即能够在待测时间间隔结束之前取走短时间隔Δt1对应的延时单元的个数，通过一定的控制信号，可以只用一组延时和锁存单元，这样可以节省CPLD内部的资源。
利用多周期同步与量化时延相结合的方法，计算公式为：T=n0t0+n1t1-n2t1上式中，n0为对填充脉冲的计数值；t0为填充脉冲的周期，即100ns；n1为短时间隔Δt1对应的延时单元的个数；n2为短时间隔Δt2对应的延时单元的个数；t1为量化延迟器件延时单元的延迟量(4.3ns)。
这样，利用多周期同步法，实现了闸门和被测信号同步；利用量化时延法，测量了原来测不出来的两个短时间间隔，从而准确地测量了实际闸门的大小，也就提高了测频的精度。
由于频率合成器输出的频率信号最小只能调到10Hz，把XDU-17的测量值作为标准，可以计算出样机测频的精度。
例如，被测信号为15.000010MHz时被测信号为5.00001002MHz时，从上面的计算可以看出，样机的分辨率已达ns量级，下面从理论分析的角度来说明这一点。
前面已经分析过，多周期同步法测频时，它的测量不确定度为：当输入f0为10MHz，闸门时间为1s时，测量的不确定度为±1×10-7/s。
当与量化延时测量与短时间间隔电路相结合时，测量的不确定度可以从下述推导出来。
在采用多周期同步法时，Tx为待测的多周期值，T0为采用的时基周期。
Tx= NT0+△t1-△t2与量化延时电路相结合后有：Tx= NT0+(N1-N2)td±δTx这里，δTx为测量的不准确度。
对上式微分得：\δTx≤±2td由上式可知，此方法的测量精度取决于td，它的稳定性与大小直接影响测量值的不确定度。
所以采用各种方法，计数器可在整个频率量程内实现等精度的测量，而且测量精度有显著提高，测量分辨率提高到4.3ns，且消除了±1个字的理论误差，精度提高了20多倍。
结束语本文将给出了一种新的测频方法。
基于此方法的频率计的数字电路部分集成在一片CPLD中，大大减小了整个仪器的体积，提高了可靠性，且达到了很高的测量分辨率。
5 频率计的VHDL 设计利用ALTERA公司的FPGA芯片EPF10K10，使用VHDL编程语言设计等精度频率计，给出核心程序，经过ISPEXPER仿真后，验证设计是成功的，达到预期结果。
传统的频率计相比，FPGA的频率计简化了电路板的设计，提高了系统设计的实现性和可靠性，测频范围达到100 MHz，实现了数字系统硬件的软件化，这是数字逻辑设计的新趋势。
本设计采用AL TERA 公司的FPGA 芯片EPF10K10, 该芯片管脚间的延迟为5 ns, 即频率为200MHz, 应用标准化的硬件描述语言VHDL 有非常丰富的数据类型, 他的结构模型是层次化的, 利用这些丰富的数据类型和层次化的结构模型, 对复杂的数字系统进行逻辑设计并用计算机仿真, 逐步完善后进行自动综合生成符合要求的、在电路结构上可实现的数字逻辑, 再下载到可编程逻辑器件中, 即可完成设计任务。
--------------------译自文斯凯赫尔著的VHDL逻辑设计76-88页Introduction of digital frequency meter Digital Frequency of communications equipment, audio and video, and other areas of scientific research and production of an indispensable instrument. Programming using Verilog HDL Design and Implementation of the digital frequency, in addition to the plastic part of the measured signal, and digital key for a part of the show, all in an FPGA chip to achieve. The entire system is very lean, flexible and have a modification of the scene.1. And other precision measuring frequency PrincipleFrequency measurement methods can be divided into two kinds:(1) direct measurement method, that is, at a certain time measurement gate measured pulse signal number.(2) indirect measurements, such as the cycle frequency measurement, VF conversion law. Frequency Measurement indirect measurement method applies only to low-frequency signals.Based on the principles of traditional frequency measurement of the frequency of measurement accuracy will be measured with the decline in signal frequency decreases in the more practical limitations, such as the accuracy and frequency of measurement not only has high accuracy, but also in the whole frequency region to maintain constant test accuracy. The main method of measurement frequency measurement Preferences gated signal GATE issued by the MCU, GATE time width on the frequency measurement accuracy of less impact, in the larger context of choice, as long as the FPGA in 32 of 100 in the counter b M Signals are not overflow line, in accordance with the theoretical calculation GATE time can be greater than the width Tc 42.94 s, but due to the single-chip microcomputer data processing capacity constraints, the actual width of less time, generally in the range of between 0.1 s choice, that is, high-frequency, shorter gate;, low gate longer. This time gate width Tc based on the size of the measured frequency automatically adjust frequency measurement in order to achieve the automatic conversion range, and expanded therange of frequency measurement; realization of the entire scope of measurement accuracy, reduce the low-frequency measurement error.The design of the main methods of measuring the frequency measurement and control block diagram as shown in Figure 1. Figure 1 Preferences gated signal GA TE issued by the MCU, GA TE time width of less frequency measurement accuracy, in the larger context of choice, as long as the FPGA in 32 of 100 in the counter b M signal Overflow will do, according to theoretical calculations GA TE time width T c can be greater than 42194 s, but due to the single-chip microcomputer data processing capacity constraints, the actual width of less time, generally 10 to 011 s in the inter-choice, that is, high - band, the gate time shorter, low gate longer. This time gate width based on the measured T c automatically adjust the size of frequency measurement frequency range to achieve the automatic conversion, and expanded the range of frequency measurement; realization of the entire scope of measurement accuracy, reduce the low-frequency measurement error.2 .Frequency of achievingFrequency Measurement accuracy of such method. Can be simplified as shown in the diagram. Map CNT1 and CNT2 two controllable counter, standard frequency (f) signal from the CN F1 clock input cI K input, the signal measured after the plastic (f) CNT2 clock input cI K input. Each counter in the CEN input as enable end, used to control the counter count. When the gate signal is HIGH Preferences (Preferences start time). Signal measured by the rising edge of the D flip-flop input, launched at the same time with two counts of juice; Similarly, when preferences for low gate signal (the end of Preferences time), the rising edge of the measured signals through D Trigger output end of the counter to stop counting.3.And the median frequency of relevant indicatorsMedian: At the same time the figures show that up to the median. The usual eight-count frequency of only several hundred yuan can buy. For high precision measurements, nine just beginning, the middle is 11, 13 can be relatively high.Overflow of:-the ability to promote itself to overflow the equivalent of the total.Some of the frequency with overflow function, which is the highest overflow does not display only shows that the bit behind, in order to achieve the purpose of the median. Here is the estimated value of individual indicators.Speed: namely, the number of per second. With the high number of measurement particularly slow but also lose its significance. Counting of the usual eight frequency measurement 10 MHz signals, one second gate will be 10000000 Hz, which is actually seven (equivalent to the median number of common admission after the value), to obtain eight needed 10 seconds gate ; to obtain nine needed 100 seconds gate, followed by analogy, shows that even the permission of 11 need 10,000 second measurement time. But in any case, or seven per second. Therefore, to fast must be a few high speed.Distinction: it is like a minimum voltage meter can tell how much voltage indicators are similar, the smaller the better, unit ps (picoseconds). 1000ps = 1ns. Suppose you use the frequency of 1 ns to differentiate between an e-12 error, we need a ns/1e-12 = 1000 seconds. Also assume that you have a frequency resolution of 100 ps, the measurement time can be shortened by 10 times for 100 seconds, or can be in the same 1000 second measured under an e-14 Error.4. Time and Frequency MeasurementCompared to traditional methods of circuit design, EDA technology uses VHDL language to describe circuit system, including circuit structure, behavior, function and interface logic. Verilog HDL description of a multi-level system hardware functions, and support top-down design features. Designers can not understand the hardware structure. Start from the system design, on the top floor of a system block diagram of the structure and design, in a diagram with Ver-ilog HDL acts on the circuit description and simulation and error correction, and then the system level verification, and finally use logic synthesis optimization tool to create specific gate-level logic circuit netlist, download to the specific FPGA device to in order to achieve FPGA design.Time and frequency measurement is an important area of electronicmeasurement. Frequency and time measurement has been receiving increasing attention, length, voltage, and other parameters can be transformed into a frequency measurement and related technologies to determine. Based on the more traditional method of synchronization cycle, and has proposed a multi-cycle synchronization and quantitative method of measuring delay frequency method.The most simple method of measuring the frequency of direct frequency measurement method. Direct Frequency Measurement is scheduled to enter the gate signal pulse, the adoption of the necessary counting circuit, the number of pulses are filled to calculate the frequency or analyte signal cycle. In the direct frequency measurement on the basis of the development of multi-cycle synchronous measurement method, in the current frequency monitoring system to be more widely used. Multi-cycle synchronization frequency measurement technology actual gate time is not fixed value, but the measured signals in the whole cycle times, and the measured signal synchronization, thereby removing the measured signal count on when the word ± 1 error, measurement accuracy greatly improved, and reached in the entire spectrum of measurement, such as precision measurement.In the time-frequency measurement method, the multi-cycle synchronization is a high precision, but still unresolved ± a word error, mainly because of the actual gate edge and standard frequency synchronization is not filling pulse edge Tx=N0T0-△t2+△t1, if accurately measured short interval Δ t1 and Δ t2, will be able to accurately measure time intervals Tx, eliminating ± a word counting error, so as to further enhance accuracy.To measure a short time interval Δ t1 and Δ t2, commonly used analog interpolation method with the cursor or more combined cycle synchronization, although accuracy is greatly improved, but eventually failed to resolve ± a word error this fundamental issue, but these methods equipment complex and not conducive to the promotion.To obtain high precision, fast response time, simple structure and the frequency and time measurement method is relatively difficult.Judging from the structure as simple as possible at the same time take intoaccount the point of view of accuracy, multi-cycle synchronization and delay based on the quantitative methods in a short period of time interval measurement, achieved within the scope of broadband, such as high-resolution measurement accuracy. Quantified by measuring short time intervals DelayPhotoelectric signal can be in a certain stability in the medium of rapid spread, and in different media have different delay. By signals generated by the delay to quantify, and gave a short period of time interval measurement.The basic principle is that "delay serial, parallel count", and different from the traditional counter serial number, that is, to signal through a series of delay unit, the delay unit on the delay stability, under the control of the computer Delay on the state of high-speed acquisition and data processing, for a short period of time to achieve accurate measurement interval.Delay quantitative thinking depend on the realization of the delay stability delay unit, the unit depends on the resolution of the delay time delay element.Delay device as a unit can be passive conduit, or other active devices gate circuit. Among them, Traverse shorter delay time (nearly the speed of light transmission delay), the gate delay time longer. Taking into account delays can be predictive ability final choice of the CPLD devices, the realization of the short time interval measurement.Will be the beginning of a short time interval signal sent delay in the transmission chain, when the advent of the end of signal, this signal delay in the delay in the chain latch state, read through the CPU, the judge signal a delay unit on the few short-term time interval can be the size of the unit decided to delay resolution of the unit delay time.Generally speaking, in order to measure both short interval, the use of two modules delay and latches, but in reality, given the time software gate large enough to allow completion from the number of CPU operation, which can be measured in the time interval taken before the end of a short period of time at Δ t1 corresponding delay the number of units through the control signals must be used only a delay and latches units, it saves CPLD internal resources. Synchronization and multi-cyclelatency to quantify the method of combining The formula is:T=n0t0+n1t1-n2t1On, n0 for the filling pulse of value; t0 for filling pulse cycle, that is 100 ns; n1 for a short period of time at Δ t1 corresponding delay the number of modules; n2 for a short period of time at Δ t2 corresponding delay unit Number; t1 quantify delay devices for the delay delay unit volume (4.3 ns). In this way, using multi-cycle synchronization and realized the gate and measured signal synchronization; Delay of using quantitative measurement of the original measured not by the two short intervals, to accurately measure the size of the actual gate, it raised frequency measurement accuracy.The frequency synthesizer output frequency signal can only be transferred to the minimum 10 Hz, XDU-17 as a standard of measurement can be calculated prototype frequency measurement accuracy.For example, the measured signal is measured at 15.000010 MHz MHz signal to 5.00001002, from the calculation can be seen above, the resolution of the prototype has reached ns order of magnitude below from the perspective of theoretical analysis to illustrate this point.It has been anal yzed,multi-cycle synchronization frequency measurement, the measurement uncertainty:When the input f0 10 MHz, 1 s gate time, the uncertainty of measurement of ±1×10-7/s. When the measurement and quantification of delay circuit with short intervals combined, the uncertainty of measurement can be derived from the following.In the use of cycle synchronization, multi-analyte Tx for the cycle value of T0 time base for the introduction of the cycle.Tx= NT0+△t1-△t2Delay circuit and quantitative combined:Tx= NT0+(N1-N2)td±δTxHere, δ Tx not for the accuracy of the measurement.On the decline of the share: \δTx≤±2tdFrom the details of the measuring accuracy of this method depends on the td, and its direct impact on the stability and size of the uncertainty of measurement. Therefore, the application of methods, counters can be achieved within the entire frequency range, such as the accuracy of measurement, and measurement accuracy is significantly improved, measuring improvement in resolution to 4.3 ns, and the elimination of the word ± a theoretical error, the accuracy is increased by 20 times.CONCLUSION This paper presents a new method of measuring frequency. Based on the frequency of this method of digital integrated circuit in a CPLD, greatly reduced the volume of the entire apparatus, improved reliability, and a high-resolution measurements.5. Frequency of VHDL DesignALTERA use of the FPGA chip EPF10K10 companies, the use of VHDL programming language design accuracy of frequency, given the core course, ISPEXPER simulation, design verification is successful, to achieve the desired results. Compared to the traditional frequency, the frequency of FPGA simplify the circuit board design, increased system design and the realization of reliability, frequency measurement range of up to 100 MHz and achieve a digital system hardware and software, which is digital logic design the new trendThis design uses the AL TERA EPF10K10 FPGA chip, the chip pin the delay of 5 ns, frequency of 200 MHz, the standardization of application VHDL hardware description language has a very rich data types, the structure of the model is hierarchical, The use of these rich data types and levels of the structure model of a complex digital system logic design and computer simulation, and gradually improve after the automatic generation integrated to meet the requirements of the circuit structure of the digital logic can be realized, then can be downloaded to programmable logic devices, to complete design tasks.----------------------------------from Vin Skahill.VHDL forProgrammable Logic page76-88。
