Freescale公司的QorIQ系列处理器P1010学习

扫码注册平头哥OCC 官网观看各类视频及课程阿里云开发者“藏经阁”海量电子手册免费下载平头哥芯片开放社区交流群扫码关注获取更多信息平头哥RISC-V 系列课程培训扫码登录在线学习目录RISC-V处理器架构 (5)1.RISC-V架构起源 (5)2.RISC-V架构发展 (5)3.RISC-V架构与X86、ARM在商业模式上的区别 (6)4.RISC-V架构现状和未来 (7)5.RISC-V处理器课程学习 (9)平头哥玄铁CPU IP (10)1.概述 (10)2.面向低功耗领域CPU (10)3.面向中高端服务器CPU (16)4.面向高性能领域CPU (23)5.玄铁CPU课程学习 (26)无剑平台 (27)1.无剑100开源SoC平台 (27)2.无剑600SoC平台 (28)平头哥RISC-V工具链 (34)1.RISC-V工具链简介 (34)2.剑池CDK开发工具 (37)3.玄铁CPU调试系统 (44)4.HHB (51)5.剑池CDK开发工具课程学习 (54)平头哥玄铁CPU系统 (55)1.YoC (55)2.Linux (56)3.Android (62)RISC-V玄铁系列开发板实践 (67)1.基于玄铁C906处理器的D1Dock Pro开发实践 (67)2.基于玄铁E906处理器的RVB2601开发实践 (82)RISC-V应用领域开发示例 (100)1.基于D1Dock Pro应用开发示例 (100)2.基于RVB2601应用开发示例 (106)RISC-V未来探索 (116)1.平头哥开源RISC-V系统处理器 (116)2.平头哥对RISC-V基金会贡献 (117)3.高校合作 (117)RISC-V处理器架构1.RISC-V架构起源RISC-V架构是一种开源的指令集架构。

最早是由美国伯克利大学的Krest教授及其研究团队提出的，当时提出的初衷是为了计算机/电子类方向的学生做课程实践服务的。

1IntroductionThe QorIQ T4240 reference system (T4240RDB) is a flexible system that supports the 24-virtual core T4240 processor. The T4240RDB main board is mounted in a 1U rack-mounted chassis. The T4240RDB supports clocking configuration flexibility to change the device frequency. Two expansion slots are also provided for adding standard PCIe cards. The T4240RDB comes with a Linux® board support package (BSP) that provides a comprehensive starting point for Linux development efforts.The part number of the T4240 reference design board (RDB)system is T4240RDB-16GPA (for a board based upon T4240Rev 1.0 silicon) and T4240RDB-PB (for a board based upon T4240 Rev 2.0 silicon).After reading this document, you will be familiar with:•Board configuration settings (frequency, boot location,and, T4240 or T4160 personality selection).•How to get started and boot uboot and Linux.Quick StartRev 0, 11/2013T4240RDB Quick Start Guide© 2013 Freescale Semiconductor, Inc.Contents1Introduction............................................................12References...............................................................23Preparing board.......................................................24SDK information.....................................................35Removing the enclosure.. (56)System board interface...........................................66.1Block diagram.............................................66.2Features.......................................................76.3Port map.......................................................86.4Known issues (9)7Default boot mode (98)Switch settings........................................................98.1SW1 switch.................................................98.2SW2 switch...............................................108.3SW3 switch...............................................108.4SW4 switch (10)9Jumper settings (1110)Revision history (11)2ReferencesThe documents below may be available only under a non-disclosure agreement (NDA). To request access to these documents, contact your local field applications engineer or sales representative.•T4240 QorIQ Integrated Multicore Communications Processor Family Reference Manual (document T4240RM)•T4240 QorIQ Integrated Multicore Communications Processor Family Data Sheet (document T4240)3Preparing boardThe figure below shows the front panel of the T4240RDB.Figure 1. T4240RDB front panelThe steps to prepare the T4240RDB for use are:1.Ensure that the power switch is off.2.Set switch and jumper header settings.3.Default Configuration: CPU: 1.666GHz, DDR: 1600MHz4.Attach an RS-232 cable between the T4240RDB UART1 port and host computer.5.Open a serial console tool on the host computer to communicate with the T4240RDB.6.Configure the host computer's serial port with the following settings:•Data rate: 115200 bps •Number of data bits: 8•Parity: None•Number of stop bits: 1•Flow control: Hardware/None7.Switch on the power button on the front side of the chassis. The board will boot and show the u-boot console messages.U-Boot 2013.01-gecbda14-dirty (Jul 31 2013 - 11:06:06)CPU0: T4240E, Version: 1.0, (0x82480010)Core: E6500, Version: 1.0, (0x80400010)Clock Configuration:CPU0:1666.667 MHz, CPU1:1666.667 MHz, CPU2:1666.667 MHz,CPU3:1666.667 MHz,CPU4:1666.667 MHz, CPU5:1666.667 MHz, CPU6:1666.667 MHz, CPU7:1666.667MHz,CPU8:1666.667 MHz, CPU9:1666.667 MHz, CPU10:1666.667 MHz,CPU11:1666.667 MHz, CCB:666.667 MHz,DDR:800 MHz (1600 MT/s data rate) (Asynchronous), IFC:166.667 MHz FMAN1: 466.667 MHzQMAN: 333.333 MHzPME: 333.333 MHzL1: D-cache 32 kB enabledI-cache 32 kB enabledReset Configuration Word (RCW):00000000: 140c0019 0c101519 00000000 0040000000000010: 70701053 0044bc00 0c023000 0d00000000000020: 00000000 ee0000ee 00000000 000287fc00000030: 00000000 50000000 00000000 00000038Board: T4240RDB, SERDES Reference Clocks: SERDES1=100MHz SERDES2=156.25MHzSERDES3=100MHz SERDES4=100MHzI2C: readySPI: readyDRAM: ing SPDDetected UDIMM 9JSF25672AZ-2G1K1Detected UDIMM 9JSF25672AZ-2G1K1Detected UDIMM 9JSF25672AZ-2G1K14 GiB left unmappedDDR: 6 GiB (DDR3, 64-bit, CL=11, ECC on)DDR Controller Interleaving Mode: 3-way 4KBFlash: 128 MiBL2: 2048 KB enabledenable l2 for cluster 1 fec60000enable l2 for cluster 2 feca0000Corenet Platform Cache: 1536 KB enabledUsing SERDES1 Protocol: 28 (0x1c)Using SERDES2 Protocol: 56 (0x38)Using SERDES3 Protocol: 2 (0x2)Using SERDES4 Protocol: 10 (0xa)SRIO1: disabledSRIO2: disabledNAND: 2048 MiBMMC: FSL_SDHC: 0PCIe1: Root Complex, no link, regs @ 0xfe240000PCIe1: Bus 00 - 00PCIe3: Root Complex, no link, regs @ 0xfe260000PCIe3: Bus 01 - 01In: serialOut: serialErr: serialWarning: SERDES2 expects reference clock 125MHz, but actual is 156.25MHzNet: Fman1: Uploading microcode version 106.4.9Fman2: Uploading microcode version 106.4.9FM1@DTSEC1 [PRIME], FM1@DTSEC2, FM1@DTSEC3, FM1@DTSEC4, FM1@TGEC1,FM1@TGEC2, FM2@DTSEC1, FM2@DTSEC2, FM2@DTSEC3, FM2@DTSEC4,FM2@TGEC1, FM2@TGEC2Hit any key to stop autoboot: 0The system auto boots and shows the following Linux login screen.Poky 9.0 (Yocto Project 1.4 Reference Distro) 1.4 t4240rdb ttyS0t4240rdb login: rootroot@t4240rdb:~# uname -aLinux t4240rdb 3.8.13-rt9-g7a2b5bd-dirty #5 SMP Wed Jul 31 13:45:53 CST 2013ppc64 GNU/Linuxroot@t4240rdb:~#4SDK informationTo access the SDK i nformation on your Linux or Windows® based machine, follow these steps.To mount an ISO image on a Linux based machine:1.Locate the QorIQ-SDK-V1.4-SOURCE-20130830-yocto.iso image file in the SW image directory of the USB2.Copy the ISO file to your Documents folder or to your preferred location.3.Open a new terminal using the keyboard shortcut, Ctrl-Alt-T .4.Enter the following command at the terminal window:$ sudo -i5.Enter your Password.6.Enter the following commands at the terminal window:a.$ mkdir /mnt/QorIQ-SDK-V1.4-SOURCE-20130830-yocto.isob.$ mount -o loop ISOPATH /QorIQ-SDK-V1.4-SOURCE-20130830-yocto.iso /mnt/QorIQ-SDK-V1.4-SOURCE-20130830-yocto.isoReplace ISOPATH with the location of the ISO file.c.$ mkdir ~/Documents/T4240_Documentationd.$ cp -R /mnt/QorIQ-SDK-V1.4-SOURCE-20130830-yocto.iso/* ~/Documents/T4240_Documentation7.Browse to the location where you extracted the ISO file and open STARTHERE.html .To mount an ISO image on a Windows based machine:1.Download and Install 7Zip .2.Locate the QorIQ-SDK-V1.4-SOURCE-20130830-yocto.iso image file in the SW image directory of the USB memory stick.3.Copy the ISO file to your Documents folder or to your preferred location.4.Right-click the ISO file and select Extract Here from the 7Zip context menu.5.Browse to the location where you extracted the ISO file and open STARTHERE.html .The image below is a screenshot of STARTHERE.html page.Figure 2. STARTHERE.html page5Removing the enclosureTo change switch or jumper settings, you need to open the board chassis. The steps to open the board chassis are:1.Remove both screws from the top side of the chassis, as shown in the figure below.Figure 3. Removing screws from top side of chassis2.Remove both screws from the back side of the chassis, as shown in the figure below.Figure 4. Removing screws from back side of chassis3.Remove the top cover carefully.6System board interfaceThe figure below shows the top view of the T4240RDB s ystem board interface.ETH8ETH9ETH10ETH11ETH6ETH7ETH4ETH5ETH2ETH3ETH0ETH1SDUART1UART2USB1USB2Power button ResetBatterySW1SW2SW4SW3DIMM2DIMM3DIMM1JP1JTAG PCIex8PCIex4Figure 5. T4240RDB top view6.1Block diagramThe figure below shows a high-level block diagram of the T4240RDB.0 1234567 ON main board RJ45891011on main board SFP+Figure 6. T4240RDB block diagram6.2FeaturesSome key features of the T4240RDB are:•Freescale QorIQ Processing Platform•QorIQ T4240 Communications Processor with 24 virtual cores, 1.6 GHz•Memory subsystem•DDR3 SDRAM• 3 DIMM slots; supports 2 GB per DIMM•Supports DDR3 UDIMM/RDIMM at 1600MT/s for T4240RDB-16GPA and supports 1866MT/s forT4240RDB-PB•NOR flash•128 MB 16-bit NOR flash, SPANSION:S29GL01GS10TFI010•NAND flash• 2 GB SLC NAND flash, MICRON:MT29F16G08ABABAWP:B• 2 Kbit 24C02 I2C EPPROM•SD connector to interface•PCIe•PCIe-x4 connector•PCIe-x8 connector•USB 2.0•Ethernet•ETH0 - ETH7: Connected to SGMII PHY - VSC8664•ETH8 - ETH11: Connected to XFI Quad SFP+ PHY CS4340•UART•UART interface: Supports two UARTs up to 115200 bps for console display; dual RJ45 slot is used for the two UART ports•Miscellaneous•LED•Power LED (green indicates power on; yellow indicates stand by)•Link LED (green indicates 1 Gbps and yellow indicates 10/100 Mbps) on each RJ45 ethernet connector•Active LED (green) on each RJ45 ethernet connector•JTAG for debugging•Reset: Hardware reset•I2C•Serial EEPROM, for board identification•Real-time clock•PCB•Power button is located at the front of the casing•Reset button is located inside of the casing•Power LED and Ethernet LED are located at the front of the casing•Power•ATX Power Supply, 300W6.3Port mapThe table below shows how ETH matches to Linux and Uboot.The image below shows the port map of T4240.Figure 7. Port map6.4Known issuesThe T4240RDB has the following known issues:•XFI: Two 10 Gbps (ETH10, ETH11) are not working; other two 10 Gbps (ETH8 , ETH9) are working fine.NOTEThis is a limitation of T4240 Rev 1.0 silicon, and will be resolved with Rev 2.0 silicon.7Default boot modeIn the T4240RDB, the boot loader, by default, executes from the NOR flash.8Switch settings8.1SW1 switchThe SW1 switch is used to control system clock (SYSCLK) and DDR reference clock (DDRCLK). The table below shows the SW1 settings for SYSCLK/DDRCLK ratio 4:1.For an SW1 value in the table above, 0 indicates on and 1 indicates off.8.2SW2 switchThe SW2 switch is reserved for debug testing purposes and is currently not in use. For an SW2 value, 0 indicates on and 1 indicates off. The default SW2 value is 1111.8.3SW3 switchThe SW3 switch is reserved for RCW bank selection and is currently not in use. For an SW3 value, 0 indicates on and 1 indicates off. The default SW3 value is 1111.8.4SW4 switchThe table below shows the SW4 settings, where value 0 indicates on and value 1 indicates off.9Jumper settingsThe jumper, JP1, is used to select JTAG mode. JP1 is shown in the figure below.Figure 8. JP1The table below shows the JP1 settings.10Revision historyThis table summarizes revisions to this document.T4240RDB Quick Start Guide, Rev 0, 11/2013Freescale Semiconductor, Inc.11How to Reach Us: Home Page: Web Support: /support Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein.Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages.“Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer's technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: /SalesTermsandConditions. Freescale, the Freescale logo, AltiVec, CodeWarrior, Energy Efficient Solutions logo, and QorIQ are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. CoreNet, is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. The Power Architecture and word marks and the Power and logos and related marks are trademarks and service marks licensed by .© 2013 Freescale Semiconductor, Inc.Document Number: T4240RDBQSRevision 0, 11/2013。

I NDUSTRY TECH 产业技术　@(投稿专用)　年第期M &Sy 　1.5GHz 不等。

QorIQ 系列的高端产品还具有进一步提升性能的突破性嵌入式处理创新,包括每个内核的专属后端缓存、数据路径加速架构(DPAA )和C oreNet 相干性构造。

Qor IQ 平台最低为45n m 量级,并提供了一个32nm (及以上)路线图。

与其他嵌入式多核架构相比,基于Qor IQ 技术的产品功耗要低得多。

45nm 节点上提供的Qor IQ 产品包括的解决方案,其范围从4W 上高度集成的产品到30W 以下的“多核”器件。

QorIQ P3和P4平台允许系统开发人员严格管理器件频率和电压。

通过在基于e500P o wer A rchit ect ure 内核的架构上的整合,Qor IQ 平台为客户提供了一条向多核处理移植的简单路径,从单核到双核再到多核器件的移植。

平台继续利用广泛的Power A rchit ecture 生态系统,飞思卡尔也会一如既往地与其合作伙伴密切合作,应对一些常见的多核开发挑战。

在高端QorIQ 平台中,旨在简化开发的片上功能,包括嵌入式hyperviso r 技术、代码性能监视器和广泛的调试可视性及接入。

飞思卡尔也一直在与虚拟化软件开发公司Virtut ech 合作,以便为嵌入式多核环境中的软件开发、调试和基准开发出一个混合模拟环境,提供可控制的、确定的和完全可逆的环境。

5款针对不同要求的QorIQ 平台系列产品在45nm 量级,Qor IQ 系列推出了5款产品平台,每款都基于飞思卡尔的e500P o wer A rchit ect ure 内核。

平台与PowerQ U ICC 处理器产品软件兼容,能够满足各种功率、性能和价格要求。

平台包括:(1)Qo rIQ P1平台系列由双核和提供了向双核处理移植路径的单核产品组成,提高了PowerQU ICC II Pro 处理器客户的性能。

Application Module Student Learning Kit (AP5211SLK Shown)Freescale’s Microcontroller Student Learning Kits The PBMCUSLK can be used standalone for introductory circuit design orused in conjunction with the application modules. The PBMCUSLK allowsyou to easily migrate from one application module to another, providinggreat flexibility in using a range of 8-, 16- and 32-bit microcontrollers.Features:>Integrated HCS12/HCS12X/HCS08USB BDM pod>USB or wall transformer powered(+3.3, +5 or ±15V*)>Replaceable, solderless breadboard>Eight LED’s, push buttons,DIP switches>2-line, 8-character LCD display>Integrated buzzer and potentiometer>COM port (RS-232/MONO8 capable)>Configurable direct connect feature*15V not available when powered from USB BDM Project Board Student Learning Kit (PBMCUSLK)OverviewFreescale’s Microcontroller Student Learning Kits (MCUSLK) now give you the flexibility to choose!The MCUSLKs now come with a feature-rich project board and your choice of an Application Module Student Learning Kit (APSLK).Best of all, the application modules are specifically designed to plug directly into the project board to enrich development.The APSLK can be used standalone for small projects or plugged into the project board. The APSLK contains an application module (microcontroller board), CodeWarrior ®programming development tools, as well as documentation, power and communications cables to provide you with a comprehensive learning environment. Application Modules:>8-bit HCS08• APS08QG8SLK >16-bit HCS12/HCS12X/DSP • APS12DT256SLK • APS12C32SLK • APS12XDT512SLK • AP56F801SLK >32-bit ColdFire ® Processor • AP5211SLK • AP5223SLK (on-chip Ethernet)>RF transceiver**• AP13192USLK **Freescale’s newest SLK keeps you up to date with the latest innovations.Now, wireless development is simple by providing ZigBee™specification-ready RF transceivers, SMAC software andsupport documentation.CodeWarrior Development Studio is a powerful and user-friendly tool suite designed to increase your software development productivity.It shares a common interface across MCU families, making the environmenteasy to use. With unrivaled features such as the Processor Expert TM applicationdesign tool, a highly optimized compiler and the project manager with built-intemplates, the tool suite’s integrated development environment (IDE) allowsthe student to focus on the application software. The CodeWarrior environmentalso features an intuitive graphical source-level debugger with integratedprofiling capabilities, data visualization, instruction set simulation and much more.National Instrument’s Educational Laboratory VirtualInstrumentation Suite (NI ELVIS)is a LabVIEW-based, hands-ondesign and prototyping environment geared for university engineering andscience courses. NI ELVIS consists of LabVIEW virtual instruments, amultifunction data acquisition device and a custom-designed bench-topworkstation. The combination of NI ELVIS with the MCUSLK is ideal forconducting microcontroller instruction, as they provide a powerful developmentand debugging platform through the integrated instrument suite of NI ELVIS.The NI ELVIS integrated instrument suite provides essential functionalityfor teaching microcontrollers, including:> Manual and programmable power supply for poweringthe student project board > Manual and programmable signal generator and digital/analog outputs to provide stimulus to MCU input signals > Multiple instruments to acquire, visualize and analyze MCU output signals > LabVIEW integration to provide flexible design, analysis, testing and reporting Contacts for additional information:Andy Mastronardi Director, University Program Freescale Semiconductor, Inc.******************************John McLellan Applications Engineer Freescale Semiconductor, Inc.********************Ravi Marawar, Ph.D.Academic Program Manager National Instruments*******************A Prototyping Environment for EducationMicrocontroller Student Learning Kit PLUS CodeWarrior Development Tools and National Instruments’Educational Laboratory Virtual Instrumentation Suite (NI ELVIS)Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners.© Freescale Semiconductor, Inc. 2006Document Number: STUDENTLEARNFSREV 1Learn More: For more information about other University Program product solutions from Freescale, please visit /universityprogram .The MCUSLKs are excellent teachingsolutions and can be used in a diversemix of coursework, such as:>Electronic Circuit Design I and II>Introduction to Microcontrollers>Microcontroller Interfacingand Applications>Mixed Signals and Circuits>Real-Time Digital Signal Processing>Real-Time Embedded Microcontrollers>Senior Project Design>MechatronicsYour students can also benefit from thereasonable price point and versatilityof MCUSLKs and are encouraged topurchase their own kit to use throughouttheir studies.。

压缩BCD码与非压缩BCD码的压缩BCD码的每一位用4位二进制表示，一个字节表示两位十进制数。

例如1001区别——0110B表示十进制数96D；非压缩BCD码用1个字节表示一位十进制数，高四位总是0000，低4位的0000~1001表示0~9.例如00001000B表示十进制数8.中断控制技术的作用：速度匹配故障处理实时处理微处理器的两种结构从内核访问指令和数据的不同空间与总线结构，可以把处理器分为哈佛结构和普林斯顿结构（或冯.诺伊曼结构）。

冯.诺伊曼结构的机器指令、数据和I/O共用一条总线，这样内核在取指时就不能进行数据读写，反之亦然。

这在传统的非流水线处理器（如MCS51）上是没有什么问题的，它们取指、执行分时进行，不会发生冲突。

但在现代流水线处理器上，由于取指、译码和执行是同时进行的（不是同一条指令），一条总线就会发生总线冲突，必须插入延迟等待，从而影响了系统性能。

ARM7TDMI 内核就是这种结构的。

而哈佛结构的处理器采用独立的指令总线和数据总线，可以同时进行取指和数据读写操作，从而提高了处理器的运行性能。

ARM Cortex-M3、ARM966E、ARM926EJ、ARM1136JF等内核都采用了哈佛结构。

简单指令集的CPU在处理一些特定的运算时速度远高于复杂指令集，所以它常被用在工业领域，比如某些软件的专用服务器，流水线操作等方面。

RISC是英文“Reduced Instruction Set Computing ” 的缩写，中文意思是“精简指令集”。

它是在CISC指令系统基础上发展起来的，有人对CISC机进行测试表明，各种指令的使用频度相当悬殊，最常使用的是一些比较简单的指令，它们仅占指令总数的20％，但在程序中出现的频度却占80％。

复杂的指令系统必然增加微处理器的复杂性，使处理器的研制时间长，成本高。

并且复杂指令需要复杂的操作，必然会降低计算机的速度。

基于上述原因，20世纪80年代RISC型CPU诞生了，相对于CISC型CPU ,RISC型CPU不仅精简了指令系统，还采用了一种叫做“超标量和超流水线结构”，大大增加了并行处理能力。

Freescale Semiconductor User’s GuideDocument Number: MPC5746REVB176UGRev. 1.6, 9/2015 Contents1IntroductionThis document describes the Qorivva MPC5746R evaluation board (EVB) for the 176LQFP, the252MAPBGA, and the 144LQFP packages. The EVB is targeted at providing a platform for the evaluation and development of the MPC5746R automotive MCU, facilitating hardware and software development as well as debugging. Settings for switches, jumpers, LEDs, and push-buttons are shown for basic operation of the prototype version of the EVB.This document is preliminary and is subject to change without notice.2FeaturesThe EVB provides the following primary features listed below:•Standalone operation or use with the optional MPC57XXX MB main board 1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3Modular concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4EVB configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34.1Methods of operation. . . . . . . . . . . . . . . . . . . . . . . . 34.2Power source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34.3Clock Configuration Options . . . . . . . . . . . . . . . . . . 54.4Micro Second Channel Connections. . . . . . . . . . . . 54.5ADC Channel Filters . . . . . . . . . . . . . . . . . . . . . . . . 64.6SIPI Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74.7JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84.8I/O Connectivity and Port Routing. . . . . . . . . . . . . . 9 5Reset switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7Test points. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8EVB Top View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 10EVB Errata. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 11Revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Qorivva MPC5746R-176D S/252D S Evaluation Board (EVB)User’s Guideby:Bill Terry32-bit Automotive ApplicationsModular concept•Socketed MPC5746R in 176-pin LQFP package, 144-pin LQFP package, or 252MAPBGA package•Power options—Power supplied via the two interface connectors when using the EVB with the optionalMPC57XXX MMB main board—Power supplied via terminal block when using the EVB in standalone configuration •Debug and trace—debug via JTAG connector—Trace using internal trace memory•Clocks—20MHz crystal—SMA connector for external clock—Oscillator•MicroSecond Channel—SAMTECH connector providing easy connection to microsecond channel pins •I/O connectivity—Access to all port pins when using the EVB with the optional MPC57XXX MB mainboard—Access to SCI, CAN, LIN, and UART physical interfaces when using the EVB withthe optional MPC57XXXMB main board•Switches—Power-on reset•LEDs for power indication•Test points3Modular conceptThe MPC5746R-176D S/252D S/144D S is part of a modular EVB hardware system that consists of:• A common main board that provides power and access to common communication interfaces and the MCU I/O port pins. The MPC5746R-176D S/252D S/144D S is compatible with theMPC57XXXMB main board.• A package-specific EVB to support all available production package types of the MPC5746R1.NOTEThe MPC57XXXMB User Guide should be obtained to provide additionalconfiguration information when used with the MPC5746-xxxD S.See Figure1., “MPC5746R EVB and main board system” for an illustration of the modular EVB hardware system concept.1.The MPC5746R Emulation Device (ED) requires separate hardware that may be ordered through your FreescaleSalesperson or Representative.EVB configurationFigure1. MPC5746R EVB and main board system4EVB configurationThis section provides information on how to configure the jumper settings on the EVB. Default settings are marked as such.4.1Methods of operationPower to the EVB is supplied by one of two options:1.The MPC57XXXMB main board generates the 5V/3.3 V/1.25V supplies and provides these tothe EVB via the interface connectors.2.In standalone configuration, external 5V/3.3V/1.25V supplies are provided to the EVB via theterminal block. (This option provides minimal access to I/O)4.2Power sourceThe default jumper settings are configured for using the EVB with the MPC57XXXMB main board. Power is supplied from the main board to the EVB via the two interface connectors.The EVB can also operate as a standalone device, where power can be supplied from an external power source.Table1 summarizes the jumper settings for the available power options.Table1. Jumper Settings — Power OptionsJumper Setting DescriptionJ23Choose one:1-2 ON2-3 ON Main IO Voltage Supply - VDD_HV_IO_MAIN 5V supply from motherboard (default)5V supply from external sourceMPC57XXXMBMPC5746R-176D S/252D SEVB configurationJ19Choose one:1-3 ON7-9 ON3-4 ON7-8 ON Low voltage power select - VDD_LV_SELECT 3.3V mother board supply (default)5.0V mother board supply3.3V external supply5.0V external supplyJ18Choose one:3-5 ON3-4 ON1-3 ON Low voltage core select - VDD_LV 1.25V external supply 1.25V internal regulator supply1.25V mother board supply (default)J22Choose one:1-2 ON2-3 ON SAR ADC Voltage Supply - VDD_HV_ADV_SAR 5.0V mother board supply (default)5.0V external supplyJ8Choose one:1-2 ON2-3 ON SD ADC Voltage Supply - VDD_HV_ADV_SD 5.0V mother board supply (default)5.0V external supplyJ3Choose one:7-9 ON1-3 ON7-8 ON3-4 ON High voltage JTAG power - VDD_HV_IO_JTAG 5.0V mother board supply3.3V mother board supply (default)5.0V external supply3.3V external supplyJ5Choose one:7-9 ON1-3 ON3-4 ON7-8 ON Microsecond Channel I/O Segment Voltage Supply - VDD_HV_IO_MSC 5.0V mother board supply (default)3.3V mother board supply3.3V external supply5.0V external supplyJ20Choose one7-9 ON1-3 ON3-4 ON7-8 ON Ethernet I/O Segment Voltage Supply - VDD_HV_IO_FEC 5.0V mother board supply3.3V mother board supply (default)3.3V external supply5.0V external supplyJ14Choose one:1-2 ON2-3 ON High voltage PMC supply - VDD_HV_PMC 5.0V motherboard supply (default)5.0V external supplyJ4Choose one:7-9 ON1-3 ON3-4 ON7-8 ON3-5 ON Standby RAM Supply Input - VDDSTBY 5.0V mother board supply3.3V mother board supply (default)3.3V external supply5.0V external supplyGND (default)J17Choose one:InstalledRemoved BCTRL - On-chip regulator pass transistor control Control enabledControl disabledJ12Choose one:1-22-3Oscillator Power - OSC_PWR 3.3V mother board supply (default) 3.3V external supplyTable1. Jumper Settings — Power Options (continued) Jumper Setting DescriptionEVB configurationIf stand alone operation is desired, the following power supplies connections should be made on J6 (see Table 2). If using the external supplies option, the user should reference the MPC5746R Data Sheet to ensure that IDD requirements for each supply are met.4.3Clock Configuration OptionsThe EVB provides three clocking options that are controlled by jumpers:•On board 20 MHz crystal oscillator •On board oscillator•SMA connector for external clock sourceTable 3 summarizes the jumper settings for the available clock options. Note that some of these jumpers are ‘non-populated’ by default and the clock source is configured by default for crystal oscillator operation.Table 2. External power inputJ6Description Pin 1 1.25V Pin 2 3.3V Pin 35V Pin 4GNDTable 3. Jumper Settings - Clock Configuration JumpersSelected Clock SourceReference DesignatorDescriptionCrystal (default)Oscillator SMA JP2Shunt to terminate EXTAL with 49.9 ohm resistor to GND Remove Remove Install JP3Shunt to connect EXTAL to crystal Install Remove Remove JP4Shunt to connect EXTAL to oscillator Remove Install Remove JP5Shunt to connect EXTAL to SMA connector Remove Remove Install JP6Shunt to connect XTAL to GND Remove Install Install J10Oscillator enableRemoveInstall 11If the oscillator is selected as the clock source, check that J12 (see Table 1) is used to select the desired oscillator power.4.4 Micro Second Channel ConnectionsThe microsecond channel signals on MSC1 are grouped at a SAMTECH ERF-8 connector on the EVB to provide easier user access. This also allows better trace routing of the differential pair signals. The connections of MSC1 on the connector are shown in Figure 2.RemoveEVB configurationNote that by default these signals are not routed to the motherboard via the motherboard interfaceconnectors. However, zero ohm resistors may be installed at the reference designators listed in Figure 2 if the signals need to be routed to the motherboard for use as GPIO or other purposes.Figure 2. Samtech ERF8 - MSC1 Connections (20-pin)The following table lists the port and pins associated with each of the MSC channel signals.4.5 ADC Channel FiltersFor convenience, the EVB implements analog RC filters on one differential ADC channel pair, and two single ended ADC channels. The single ended filter configuration is shown in Figure 3, and the differential pair filter configuration is shown in Figure 4. The user may modify these component values for the desired application.Table 4. MSC Signal MappingSignal Name Device Port Pin Assignment 176LQFP 252MAPBGAMSC1MSC1_SOUTN PA7165C6MSC1_SOUTP PA8164A6MSC1_CLKN PA9161A7MSC1_CLKP PA10160B7MSC1_RX PA11159C7MSC1_CS1PA12158B8MSC1_CS0PA13157A8121920VSSMSC1_SOUTN PA[7]MSC1_SOUTP PA[8]MSC1_CLKN PA[9]MSC1_CLKP PA[10]MSC1_RX PA[11]MSC1_CS1 PA[12]MSC1_CS0 PA[13]VSSVSSVSSVSSMotherboard Connector0000000Not populatedR2R3R4R5R15R14R16EVB configurationFigure 3. Single Ended ADC Channel FiltersFigure 4. Differential ADC Channel Filter4.6SIPI InterfaceA SIPI interface is provided on the EVB for high speed interprocessor communications. The SIPI interface connections are shown in Figure 5 and listed in Table 5.PZ1420KPZ1520K0.01μF 0.01μFC390.01μF C380.01μFC48C47J111234R19R21PY020K PY120K C62100pFC61100pFJ1512R23R24EVB configurationFigure5. SIPI InterfaceTable5. SIPI connector(J1)Pin Signal Pin Signal1SIPI TXP2GND3SIPI TXN4GND5GND6SIPI_CLK7SIPI RXN8GND9SIPI RXP10GND4.7JTAG InterfaceA standard JTAG interface is provided on the EVB for debug connections. Note that the Aurora high speed debug interface is only available with the MPC5746R BD trace adapter board provided as part of the Freescale calibration solution. The JTAG interface connections are shown in Figure6 and listed in Table6.EVB configurationFigure 6. JTAG Interface 4.8 I/O Connectivity and Port RoutingMost of the MCU’s I/Os are routed to the main mother board. These include the pins associated with the FlexCAN, Ethernet, and LinFlex interfaces and other normal GPIO pins. The MPC57XXXMB provides physical layer drivers for these communication protocols. See the MPC57XXXMB User Guide for the correct jumper settings to enable and configure these drivers and associated circuits.Table 7 lists the mapping from the MPC5746R device ports to the existing headers/ports on the MPC57XXXMB motherboard, and to the FlexCAN, Ethernet, UART and LinFlex drivers.Table 6. JTAG connector (J7)Pin SignalPin Signal1TDI 2GND 3TDO 4GND 5TCK 6GND 7EVTI08PORST_B 9RESET_B10TMS 11VDD_HV_IO_JTAG 12GND 13EVTO014JCOMPEVB configurationTable 7. Port to Motherboard Mapping — 144LQFP , 176LQFP and 252MAPBGAMPC5746RPin NumberMPC57XXXMB MotherboardPortFunction144LQFP176LQFP252MAPBGA144LQFP176LQFP 252MAPBGA144LQFP176LQFP 252MAPBGAPA[0]MSC0_CS0—142174A3PP[7]2PA[0]PA[1]MSC0_CS1/SIPI_RXN SIPI_RXN 141173B3PP[8]2no connect 1PA[2]MSC0_RX/SIPI_RXPSIPI_RXP140172A4PP[9]2no connect 1PA[3]MSC0_CLKN —139171B4PP[10]2PA[3]PA[4]MSC0_CLKP/SIPI_CLK SIPI_CLK 138170C4PP[11]2no connect 1PA[5]MSC0_SOUTN/SIPI_TXN SIPI_TXN 137169C5PP[12]2no connect 1PA[6]MSC0_SOUTP/SIPI_TXPSIPI_TXP 136168B5PP[13]2no connect 1PA[7]n/a MSC1_SOUTN 165C6n/a PP[7]2PA[8]n/a MSC1_SOUTP 164C7n/a PP[8]2PA[9]n/a MSC1_CLKN 161A6n/a PP[92]PA[10]n/a MSC1_CLKP 160A7n/a PP[10]2PA[11]n/a MSC1_RX 159B7n/a PP[11]2PA[12]n/a MSC1_CS1158B8n/a PP[12]2PA[13]n/aMSC1_CS0157A8n/aPP[13]2PB[0]TDO 143175D1no connect 3PB[1]TDI144176E3no connect 3PC[0]FEC_REF_CLK 4556Y9PA[15]PC[1]FEC_TXCLK 4657W9PK[14]PC[2]FEC_TXEN 4758V9PC[14]PC[3]FEC_TXD34859U9PM[5]PC[4]FEC_TXD24960W10PM[4]PC[5]FEC_TXD15061V10PE[12]PC[6]FEC_TXD05162U10PC[15]PC[7]FEC_RXD05465Y11PC[12]PC[8]FEC_RXD15566V11PC[13]PC[9]FEC_RXD25667U11PM[1]PC[10]FEC_RXD35768Y12PK[15]PC[11]FEC_RXER 5869W12PM[3]PC[12]FEC_RXCLK 5970V12PC[10]PC[13]FEC_RXDV6071U12PM[0]PD[0]—3745Y3PL[0]PD[1]—3846W3PL[1]PD[2]—Y4PL[2]PD[3]—W4PL[3]PD[4]—47V4PL[4]EVB configurationPD[5]—Y5PL[5]PD[6]—W5PL[6]PD[7]—3948V5PL[7]PD[8]FEC_MDC4049V6PC[3]PD[9]—Y7PL[9]PD[10]—52W7PL[10]PD[11]—53V7PL[11]PD[12]—U7PL[12]PD[13]FEC_MDIO4354Y8PC[2]PD[14]—4455W8PL[14]PD[15]—V8PL[15]PE[0]—U8PE[0]PF[0]LIN2TX 126G20PD[14]PF[1]LIN2RX 127G19PD[15]PF[2]LIN3TX G18PF[2]PF[3]LIN3RX G17PF[3]PF[4]CAN0TX F19PF[4]PF[5]CAN0RX D19PF[5]PF[6]CAN1TX E20PF[6]PF[7]CAN1RXE18PF[7]PF[8]—D20PF[8]PF[9]—D19PF[9]PF[10]CAN1TXD18PF[10]PF[11]CAN0RX/CAN1RX106130C20PF[11]PF[12]CAN0TX 107131C19PC[9]PF[13]CAN0RX 108132B20PC[8]PG[1]CAN2RX 109133A18PG[14]PG[2]CAN2TX 110134A17PE[5]PG[3]—B17PG[3]PG[4]—C18PG[4]PG[5]LIN1RX 111135B16PE[6]PG[6]LIN1TX 112136A16PE[7]PG[7]—C17PG[7]PG[9]CAN3RX113137C16PA[11]PG[10]—138A15PG[10]PG[11]CAN3TX 115140B15PA[10]PG[12]—116141B14PG[12]PG[13]—117142A14PG[13]Table 7. Port to Motherboard Mapping — 144LQFP , 176LQFP and 252MAPBGAMPC5746RPin NumberMPC57XXXMB Motherboard PortFunction144LQFP176LQFP252MAPBGA144LQFP176LQFP 252MAPBGA144LQFP176LQFP 252MAPBGAEVB configurationPG[14]—C15PE[14]PG[15]—C14PE[15]PH[0]—118143D14PH[0]PH[1]—A13PH[1]PH[2]—B13PH[2]PH[3]—119144C13PH[3]PH[4]—D14PH[4]PH[5]—A12PH[5]PH[6]—C12PH[6]PH[7]—120145D12PH[7]PH[8]—121146B11PH[8]PH[9]—C11PH[9]PH[10]—D11PH[10]PH[11]—125150A10PH[11]PH[12]—126151B10PH[12]PH[13]—C10PH[13]PH[14]—127152D10PH[14]PH[15]—128153A9PH[15]PI[0]—129154B9PI[0]PI[1]—130155C9PI[1]PI[2]—D9PI[2]PI[3]—131156C8PI[3]PI[4]—D8PI[4]PI[5]—D7PI[5]PJ[0]—1010H1PJ[0]PJ[1]—1111G4PJ[1]PJ[2]—H2PJ[2]PJ[3]—12H3PJ[3]PJ[4]EVTI_01213H4no connect 3PJ[5]—1718J2PJ[5]PJ[6]—J3PJ[6]PJ[7]EVTO_01819J4no connect 3PJ[8]—K2PJ[8]PJ[9]—K3PJ[9]PJ[10]—K4PJ[10]PJ[11]—2425L3PJ[11]PJ[12]—26L4PJ[12]PJ[13]—27M3PJ[13]Table 7. Port to Motherboard Mapping — 144LQFP , 176LQFP and 252MAPBGAMPC5746RPin NumberMPC57XXXMB Motherboard PortFunction144LQFP176LQFP252MAPBGA144LQFP176LQFP 252MAPBGA144LQFP176LQFP 252MAPBGAEVB configurationPJ[14]—2528M4PJ[14]PJ[15]—29N2PJ[15]PK[0]—30N3PS[0]PK[1]—2631N4PS[1]PK[2]—2732P1PS[2]PK[4]—33P2PS[4]PK[5]—2834P3PS[5]PK[7]—3137P4PS[7]PK[8]—3238R1PS[8]PK[9]—39R3PS[9]PK[10]—3340T2PS[10]PK[11]—3441T3PS[11]PK[12]—42U1PS[12]PK[13]—3543U2PS[13]PK[14]—3644V1PS[14]PW[0]—Y13PW[0]PW[1]—6476W13PW[1]PW[2]—75V13PW[2]PW[3]—6374U13PW[3]PX[0]—U19PX[0]PX[1]—7389U18PX[1]PX[2]—7288V18PX[2]PX[3]—7187Y17PX[3]PX[4]—W17PX[4]PX[5]—6884V17PX[5]PX[6]—Y16PX[6]PX[7]—6783W16PX[7]PX[8]—U14PX[8]PX[9]—82Y15PX[9]PX[10]—6681W15PX[10]PX[11]—V15PX[11]PX[12]—80Y14PX[12]PX[13]—79W14PX[13]PX[14]—6578V14PX[14]PX[15]—77V16PX[15]PY[0]SD2_0101N20n/a no connect 4PY[1]SD2_180100N19no connect 6no connect 5Table 7. Port to Motherboard Mapping — 144LQFP , 176LQFP and 252MAPBGAMPC5746RPin NumberMPC57XXXMB MotherboardPortFunction144LQFP176LQFP252MAPBGA144LQFP176LQFP 252MAPBGA144LQFP176LQFP 252MAPBGAReset switches5Reset switchesThe push-button switch SW1 provides a power-on-reset signal to the MCU.PY[2]—99N18PT[2]PY[3]—N17PT[3]PY[4]—98P20PT[4]PY[5]—P19PT[5]PY[6]—7997P18PT[6]PY[7]—96P17PT[7]PY[8]—R20PT[8]PY[9]—7895R19PT[9]PY[10]—94R18PT[10]PY[11]—T20PT[11]PY[12]—T19PT[12]PY[13]—7793T18PT[13]PY[14]—U20PT[14]PY[15]—7490V20PT[15]PZ[0]—102123H20PN[0]PZ[1]—101122H19PN[1]PZ[2]—100121H18PN[2]PZ[3]—99120H17PN[3]PZ[4]—98119J20PN[4]PZ[5]—97118J19PN[5]PZ[6]—96117J18PN[6]PZ[7]—95116J17PN[7]PZ[8]—90111K18PB[0]PZ[9]—89110K17PB[1]PZ[10]—88109L18PB[2]PZ[11]—87108L17PB[3]PZ[12]—86107M18PB[4]PZ[13]—85106M17PB[5]PZ[14]—84105M20no connect 5no connect 6PZ[15]—83104M19no connect 4no connect 61Routed to Samtech connector 1 on daughter card.2Routed to Samtech connector 2 on daughter card and to this port number on MB via a zero ohm resistor..3Routed to JTAG connector on daughter card4Routed to N side of differential PI-filter on daughter card 5Routed to P side of differential PI-filter on daughter card 6Routed to Pi-filter on daughter cardTable 7. Port to Motherboard Mapping — 144LQFP , 176LQFP and 252MAPBGAMPC5746RPin NumberMPC57XXXMB MotherboardPortFunction144LQFP176LQFP252MAPBGA144LQFP176LQFP 252MAPBGA144LQFP176LQFP 252MAPBGALEDs 6LEDsLEDs shown in Table8 provide indicators for:•Power from external 5.0 V supply•Reset statesTable8. LEDsLED DescriptionD15V External SupplyD2RESET_BD3PORST_B7Test pointsTest points shown in Table9 are available to allow probing of various voltages and signals.Table9. Test pointsTest Point DescriptionTP1SIPI_CLKTP2VDD_HV_MSCTP3VDD_STBYTP4VDD_HV_IO_JTAGTP5SIPI_TXPTP6SIPI_TXNTP7SIPI_RXNTP8SIPI_RXPTP9GNDTP10GNDTP11VSSA_JTAGTP12VDD_HV_ADV_SDTP13VSSA_ADCTP14VDD_HV_PMCTP15VDD_HV_FLATP16VDD_LV_CORETP17GNDTP18GNDTP19VDD_HV_IO_FECTP20VDD_HV_ADV_SARSchematics8SchematicsThe MPC5746R-176D S, MPC5746R-252DS and MPC5746R-144D S schematics are available as an attachment in this PDF document. To access the schematic open the bookmark window and click on the paper clip icon on the left side of the page.9EVB ErrataEVB errata are listed in the following table.TP21VDD_HV_IO_MAINErrata ListErrata DescriptionAffectedWorkaround 176D S252D S144D S1Port pin PG[9] (CAN3RX) on the MPC5746R wasrouted to motherboard port pin PA[13] instead ofPA[11]. PA[11] is also routed on the motherboard toJ38, which is a selectable RX pin for the CANtransceiver. This prevents the CAN RX signal frombeing connected directly via motherboard trace tothe PG[9] pin on the MPC5746R for the CAN3RXfunction.Yes No NoTo connect the RX signal fromthe CAN bus interface (J6) to theCAN3RX signal on theMPC5746R device at pin PG[9],place a wire jumper from PA[13]on the motherboard to pin 3 onJ38.Table9. Test points (continued)Test Point DescriptionRevision history 10Revision historyTable10. Revision historyRevision number Date Description1.004/24/2013Initial version.1.104/25/2013Updated from review comments.1.204/25/2013Added EVB Errata section and updatedwith current known errata.1.309/09/2013Updated Table7 to include portmappings from 252MAPBGA pins. Otherminimal modifications to various sectionsso that User Guide supports both 176and 252 packages.1.409/11/2013Removed Top View section. UpdatedErrata list to included affected D S1.504/23/2014Updated Table7 to include portmappings from 144LQFP pins. Otherminimal modifications to various sectionsso that User Guide supports the 176,252, and 144 packages.1.609/01/2015Changed all instances of MPC5746Mto MPC57XXX.Document Number:MPC5746REVB176UG Rev. 1.69/2015Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document.Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: /v2/webservices/Freescale/Docs/TermsandConditions.htmHow to Reach Us:Home Page:Web Support:/supportFreescale, the Freescale logo, AltiVec, C-5, CodeTest, CodeWarrior, ColdFire,C-Ware, Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC, ProcessorExpert, QorIQ, Qorivva, StarCore, Symphony, and VortiQa are trademarks ofFreescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack,ColdFire+, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge,QUICC Engine, Ready Play, SafeAssure, SMARTMOS, TurboLink, Vybrid, and Xtrinsicare trademarks of Freescale Semiconductor, Inc. All other product or service namesare the property of their respective owners. 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This document contains information on a new product. Specifications and information herein are subject to change without notice.Freescale SemiconductorAdvance InformationThis document describes part number-specific changes to recommended operating conditions and revised electrical specifications, as applicable, from those described in the general MPC7410 Hardware Specifications (Document No. MPC7410EC).Specifications provided in this document supersede those in the MPC7410 Hardware Specifications , for the part numbers listed in Table A only. Specifications not addressed herein are unchanged. Because this document is frequently updated, refer to or to your Freescale sales office for the latest version.Note that headings and table numbers in this document are not consecutively numbered. They are intended tocorrespond to the heading or table affected in the general hardware specification. Part numbers addressed in this document are listed in Table A. For more detailed ordering information see Table 17.Document Number:MPC7410ECS02ADRev. 2.0, 11/2007Freescale Part Numbers Affected:MPC7410RX400NE MPC7410HX400NE MPC7410VS400NE MC7410VU400NE MPC7410RX450NE MPC7410HX450NE MPC7410VS450NE MC7410VU450NE--- Preliminary ---MPC7410 RISC MicroprocessorHardware Specifications Addendum for the MPC7410xxnnnNE SeriesFeatures2 FeaturesThis section summarizes changes to the features of the MPC7410 described in the MPC7410 Hardware Specifications .•Bus interface—Selectable interface voltages of 1.8 V , 2.5 V (3.3 V not supported)4.1 DC Electrical CharacteristicsV oltage to the L2 I/Os and processor interface I/Os are provided through separate sets of supply pins and may be provided at the voltages shown in Table 2.Table A. Part Numbers Addressed by this Data SheetFreescale PartNumber Operating ConditionsSignificant Differences from HardwareSpecification CPU Frequency Vdd T J (°C)OVdd MPC7410RX400NE MPC7410HX400NE MPC7410VS400NE MC7410VU400NE400 MHz1.5V±50mV0 to 1051.8/2.5 VReduced core voltage to achieve lower power consumption. Removes 3.3V OVdd support. For all AC/DC specifications not mentioned in this document, please refer to the MPC7410(RX/HX/VS)400LE andMC7410VU400LE specifications in the general MPC7410 Hardware Specifications .450 MHz1.8V ±100mV 0 to 1051.8/2.5/3.3 V The MPC7410(RX/HX/VS)400NE andMC7410VU400NE also fully conform to the MPC7410(RX/HX/VS)450LE andMC7410VU450LE specifications, respectively. Refer to the general MPC7410 Hardware Specifications .MPC7410RX450NE MPC7410HX450NE MPC7410VS450NE MC7410VU450NE450 MHz 1.5V±50mV0 to 1051.8/2.5 VReduced core voltage to achieve lower power consumption. Removes 3.3V OVdd support. For all AC/DC specifications not mentioned in this document, please refer to the MPC7410(RX/HX/VS)450LE andMC7410VU450LE specifications in the general MPC7410 Hardware Specifications .500 MHz1.8V ±100mV 0 to 1051.8/2.5/3.3 V The MPC7410(RX/HX/VS)450NE andMC7410VU400NE also fully conform to the MPC7410(RX/HX/VS)500LE andMC7410VU500LE specifications, respectively. Refer to the general MPC7410 Hardware Specifications .FeaturesTable 3 provides the recommended operating conditions for the MPC7410 part numbers described herein.Table 2. Input Threshold Voltage SettingBVSEL Signal 3Processor Bus Input Threshold is Relative to:L2VSEL Signal 3L2 Bus Input Threshold isRelative to:Note 0 1.8 V 0 1.8 V 1 HRESET2.5 V HRESET2.5 V 1, 21 Not Supported 1 2.5 V 1, 4, 5HRESETNot SupportedHRESETNot Supported—Notes:1. Caution: The input threshold selection must agree with the OVdd/L2OVdd voltages supplied.2. T o select the 2.5-V threshold option, BVSEL and/or L2VSEL should be tied to HRESET so that the two signalschange state together. This is the preferred method for selecting this mode of operation.3. T o overcome the internal pull-up resistance, a pull-down resistance less than 250 ohms should be used.4. Default voltage setting if left unconnected (internal pulled-up).5. Caution: The XPC7410RXnnnNE does not support the default OVdd setting of 3.3 V . The BVSEL input must be tieeither low or to HRESET .Table 3. Recommended Operating ConditionsCharacteristicSymbol Recommended ValueUnit Core supply voltage Vdd 1.5V ± 50mV V PLL supply voltage AVdd 1.5V ± 50mV V L2 DLL supply voltageL2AVdd 1.5V ± 50mV V Processor bus supply voltage BVSEL = 0OVdd 1.8V ± 100mV V BVSEL = HRESET OVdd 2.5V ± 100mV V BVSEL = HRESET or BVSEL = 1OVdd Not Supported V L2 bus supply voltageL2VSEL = 0 L2OVdd 1.8V ± 100mV V L2VSEL = HRESET or L2VSEL = 1L2OVdd 2.5V ± 100mV V Input voltageProcessor bus and JT AG Signals V in GND to OVdd V L2 BusV in GND to L2OVddV Die-junction temperatureT j0 to 105°CNote: These are the recommended and tested operating conditions. Proper device operation outside ofthese conditions is not guaranteed.FeaturesTable 7 provides the power consumption for the MPC7410 part at the frequencies described herein.Table7. Power Consumption for MPC7410Processor(CPU) Frequency Processor(CPU)Frequency Unit Notes400Mhz450Mhz Full-On ModeT ypical Maximum 2.92 3.29W1, 3 6.67.43W1, 2,Doze ModeMaximum 3.6 4.1W1, 2Nap ModeMaximum 1.35 1.5W1, 2 Sleep ModeMaximum 1.3 1.45W1, 2 Sleep Mode—PLL and DLL DisabledT ypical0.60.6W1, 3Maximum 1.1 1.1W1, 2Notes:1. These values apply for all valid processor bus and L2 bus ratios. The valuesdo not include I/O Supply Power (OVdd and L2OVdd) or PLL/DLL supply power (AVdd and L2AVdd). OVdd and L2OVdd power is system dependent, but is typically <10% of Vdd power. Worst case power consumption for AVdd = 15 mw and L2AVdd = 15 mW.2. Maximum power is measured at 105 °C and Vdd = 1.5V while running anentirely cache-resident, contrived sequence of instructions which keep the execution units, including AltiVec, maximally busy.3. T ypical power is an average value measured at 65 °C and Vdd = 1.5V in asystem while running typical benchmarks.Document Revision History 9 Document Revision HistoryTable 16 provides a revision history for this Hardware Specification Addendum.Table16. Document Revision HistoryRevision Date Substantive Changes2.011/16/2007Updated document title to remove “RX” from part number since other non-RX package deviceswere added to this specification.Added MPC7410HX400NE, MPC7410VS400NE, MC7410VU400NE, MPC7410HX450NE,MPC7410VS450NE, and MC7410VU450NE devices to list on cover page and to Table A.Updated Table 17 to match corresponding table in MPC7410 Hardware Specifications1.104/19/2005Document template updateDocument ID change from MPC7410RXNEPNS for Part Number Specification toMPC7410ECS02AD for Hardware Specification Addendum.110/2002Minor formatting.Added Section 1.9 Document Revision History.Section 1.10.1 - added T able 17 - Part Marking Nomenclature.0Initial releaseOrdering Information10 Ordering Information10.1 Part Numbers Addressed by this SpecificationTable 17 provides the ordering information for the MPC7410 part described in this document.Table 17. Part Marking Nomenclature.10.3 Part MarkingParts are marked as the example shown in Figure 26.Figure 26. Freescale Part Marking for BGA DeviceMxx7410xxnnnNEProduct Code Part Identifier Package Processor Frequency 1Application Modifier Revision LevelMPC7410RX =CBGA400450500N: 1.5 V ± 50mV0 to 105 °CE: 1.4;PVR = 800C 1104HX =HCTE_CBGA VS =HCTE_LGA400450MCVU =HCTE_CBGA (Lead Free C5 Solder Spheres)Notes:1. Processor core frequencies supported by parts are addressed by this specification only. Parts addressed by other specifications may support other maximum core frequencies.BGA Notes :CCCCC is the country of assembly (this space is left blank if parts are assembled in the United States)MMMMMM is the 6-digit mask number ATWLYYWWA is the traceability codeMPC7410RXnnnNE MMMMMM ATWLYYWWA7410nnn is the speed grade of the partOrdering Information THIS PAGE INTENTIONALLY LEFT BLANKDocument Number:MPC7410ECS02AD Rev. 2.011/2007Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. The Power Architecture and word marks and the Power and logos and related marks are trademarks and service marks licensed by .© Freescale Semiconductor, Inc., 2002, 2007. Printed in the United States of America. All rights reserved.Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. 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飞思卡尔半导体应用笔记文档号: AN3102第0版, 2005年9月目录©飞思卡尔半导体（中国）有限公司, 2005-2008. 版权所有. 初稿，本手册可能会在未经通知的情况下更新1引言56F801x 系列设备与其它56800E 系列设备相比，有很多不同的特征和改进功能。

本应用笔记将对这些不同功能进行详细介绍，以帮助用户了解更多相关知识。

2一体化RAM56F801x 系列设备采用了与先前56800E 设备不同的存储模型。

该系列设备的RAM 结构体系经过修改后，在程序和数据存储映像图中均可使用，这也使开发人员需要考虑这些修改所带来的影响。

• RAM 是一个单一的存储块，可以出现在程序和数据存储映像图中。

虽然在两个图中的地址不同，但对应的是相同的物理块。

• 为了适应RAM 的一体化功能，飞思卡尔半导体公司的CodeWarrior 修改了使用的存储配置文件。

程序空间和数据空间之间在一体化RAM 中的动态（联接时）分配，请参见应用示例。

1引言. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12一体化RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13时钟. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.1内部时钟 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33.2外部时钟 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34输入/输出（I/O ）引脚的复用. . . . . . . . . . . . . . . . . . . . . . . 45带LIN 从机模式的SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66SPI 的输入/输出问题 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76.1主机模式 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76.2从机模式 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77ADC 变动. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77.1独立的并行扫描定时 . . . . . . . . . . . . . . . . . . . . . . . . . . . 77.2定时触发器的ADC 同步输入. . . . . . . . . . . . . . . . . . . . 87.3VREF 的选择 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88定时器的输入/输出 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89PWM 控制 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109.1传统的PWM 操作 . . . . . . . . . . . . . . . . . . . . . . . . . . . .129.2ADC 控制PWM 输出. . . . . . . . . . . . . . . . . . . . . . . . . .149.3提供PWM 控制的定时器驱动ADC 采样 . . . . . . . . .179.4定时器控制PWM 输出 . . . . . . . . . . . . . . . . . . . . . . . .199.5由外部引脚控制的PWM 输出 . . . . . . . . . . . . . . . . . .229.6带ADC 采样触发的由外部引脚控制的PWM 输出 .2310节能功能. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2411参考资料. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2556F801x 系列设备的特殊功能作者:Les Lewis56F801x 系列设备的特殊功能, 第0版初稿，本手册可能会在未经通知的情况下更新时钟飞思卡尔半导体23时钟图1展示了56F801x 的片内时钟合成(OCCS)模块框图。