IS62LV2568ALL-70T中文资料

20
20
25
25
15
15
20
20
单位 mA mA mA mA
电容(1)
符号
参数
条件
最大
CIN
输入电容
VIN=0V
6
COUT
输入/输出电容
VOUT=0V
8
注
1. 这两个参数均在最开始时测得 设计或处理的任何变化都将影响它们的值
单位 pF pF
4
电子发烧友 电子技术论坛 广州周立功单片机发展有限公司 Tel 020 38730976 38730977 Fax 38730925 http //
2
电子发烧友 电子技术论坛 广州周立功单片机发展有限公司 Tel 020 38730976 38730977 Fax 38730925 http //
管脚配置
44 脚 LQFP
读周期变化特性(1) 工作范围内
符号
参数
10
12
单位
最小
最大
最小
最大
tRC tAA tOHA tACE tDOE tHZOE(2) tLZOE(2) tHZCE(2) tLZCE(2) tBA tHZB(2) tLZB(2) tPU tPD 注
读周期时间 地址访问时间 输出保持时间
CE 访问时间 OE 访问时间 OE 到高阻输出 OE 到低阻输出 CE 到高阻输出 CE 低阻输出 LB , UB 访问时间 LB , UB 到高阻输出 LB , UB 到低阻输出 上电时间 掉电时间
其可靠性
3
电子发烧友 电子技术论坛 广州周立功单片机发展有限公司 Tel 020 38730976 38730977 Fax 38730925 http //

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.DESCRIPTIONThe 1+51 IS62LV2568L and IS62LV2568LL are low powerand low V CC , 262,144-bit words by 8 bits CMOS static RAMs.They are fabricated using 1+51's high-performance CMOS technology. This highly reliable process coupled with innova-tive circuit design techniques, yields higher performance and low power consumption devices.When CE1 is HIGH or CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced by using CMOS input levels.Easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable (WE )controls both writing and reading of the memory.The IS62LV2568L and IS62LV2568LL are available in 32-pin 8*20mm TSOP-1, 8*13.4mm TSOP-1 and 48-pin 6*8mm TF-BGA.FEATURESAccess times of 55, 70, 100 nsLow active power: 126 mW (max, L, LL)Low standby power: 36 µW (max, L) and 7.2µW (max, LL) CMOS standbyLow data retention voltage: 1.5V (min.) Available in Low Power (-L) and Ultra-Low Power (-LL)Output Enable (OE ) and two Chip Enable TTL compatible inputs and outputs Single 2.7V-3.6V power supplyAvailable in the 32-pin 8x20mm TSOP-1, 32-pin 8x13.4mm TSOP-1 and 48-pin 6*8mm TF-BGA2Integrated Circuit Solution Inc.IS62LV2568L IS62LV2568LLPIN CONFIGURATIONS32-Pin 8*20mm TSOP-1, 8*13.4mm STSOP-1PIN DESCRIPTIONSA0-A17Address Inputs CE1Chip Enable 1 Input CE2Chip Enable 2 Input OE Output Enable Input WE Write Enable Input I/O0-I/O7Data Input/Output NC No Connection Vcc Power GNDGround48-Pin 6*8mm TF-BGAOPERATING RANGERangeAmbient TemperatureV CCCommercial 0°C to +70°C 2.7V - 3.6V Industrial40°C to +85°C2.7V -3.6VIS62LV2568L IS62LV2568LLABSOLUTE MAXIMUM RATINGS (1)Symbol ParameterValueUnit V TERM Terminal Voltage with Respect to GND 0.5 to Vcc + 0.5V V CC Vcc related to GND0.3 to +4.0V T BIAS Temperature Under Bias 40 to +85°C T STG Storage Temperature 65 to +150°C P TPower Dissipation0.7WNotes:1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.CAPACITANCE (1)Symbol Parameter Conditions Max.Unit C IN Input Capacitance V IN = 0V 6pF C OUTOutput CapacitanceV OUT = 0V8pFNotes:1.Tested initially and after any design or process changes that may affect these parameters.DC ELECTRICAL CHARACTERISTICS (Over Operating Range)Symbol ParameterTest ConditionsMin.Max.Unit V OH Output HIGH Voltage V CC = Min., I OH = 1.0 mA 2.2 V V OL Output LOW Voltage V CC = Min., I OL = 2.1 mA0.4V V IH Input HIGH Voltage 2.2V CC + 0.3V V IL (1)Input LOW Voltage (1) 0.30.4V I LI Input Leakage GND ≤ V IN ≤ V CC 11µA I LOOutput LeakageGND ≤ V OUT ≤ V CC11µANotes:1.V IL =2.0V for pulse width less than 10 ns.TRUTH TABLEModeWE CE1CE2OE I/O OperationVcc Current Not Selected X H X X High-Z I SB , I SB (Power-down)X X L X High-Z I SB , I SBOutput Disabled H L H H High-Z I CC Read H L H L D OUT I CC WriteLLHXD INI CCIS62LV2568LIS62LV2568LLIS62LV2568L POWER SUPPLY CHARACTERISTICS(1)(Over Operating Range)-55-70-100Symbol Parameter Test Conditions Min.Max.Min.Max.Min.Max.UnitI CC Vcc Dynamic Operating V CC = Max.,Com. 40 30 20mASupply Current I OUT = 0 mA, f = f MAX Ind. 45 35 25I SB TTL Standby Current V CC = Max.,Com. 0.4 0.4 0.4mA(TTL Inputs)V IN = V IH or V IL,Ind. 1.0 1.0 1.0CE1≥ V IH or CE2 ≤ V IL, f = 0I SB CMOS Standby V CC = Max., f = 0Com. 35 35 35µACurrent (CMOS Inputs)CE1≥ V CC 0.2V,Ind. 50 50 50CE2 ≤ 0.2V,or V IN≥ V CC 0.2V, V IN≤ 0.2VNote:1.At f = f MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.IS62LV2568LL POWER SUPPLY CHARACTERISTICS(1)(Over Operating Range)-55-70-100Symbol Parameter Test Conditions Min.Max.Min.Max.Min.Max.UnitI CC Vcc Dynamic Operating V CC = Max.,Com. 40 30 20mASupply Current I OUT = 0 mA, f = f MAX Ind. 45 35 25I SB TTL Standby Current V CC = Max.,Com. 0.4 0.4 0.4mA(TTL Inputs)V IN = V IH or V IL,Ind. 1.0 1.0 1.0CE1≥ V IH or CE2 ≤ V IL, f = 0I SB CMOS Standby V CC = Max., f = 0Com. 10 10 10µACurrent (CMOS Inputs)CE≥ V CC 0.2V,Ind. 15 15 15CE2 ≤ 0.2V,or V IN≥ V CC 0.2V, V IN≤ 0.2VNote:1.At f = f MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.4Integrated Circuit Solution Inc.IS62LV2568LIS62LV2568LLREAD CYCLE SWITCHING CHARACTERISTICS(1)(Over Operating Range)-55-70-100Symbol Parameter Min.Max.Min.Max.Min.Max.Unit t RC Read Cycle Time55 70 100 nst AA Address Access Time 55 70 100nst OHA Output Hold Time10 10 15 nst ACE1CE1 Access Time 55 70 100nst ACE2CE2 Access Time 55 70 100nst DOE OE Access Time 30 35 50nst LZOE(2)OE to Low-Z Output5 5 5 nst HZOE(2)OE to High-Z Output 20025030nst LZCE1(2)CE1 to Low-Z Output10 10 10 nst LZCE2(2)CE2 to Low-Z Output10 10 10 nst HZCE(2)CE1 or CE2 to Low-Z Output020025030nsNotes:1.Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levelsof 0.4V to 2.2V and output loading specified in Figure 1.2.Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.AC TEST CONDITIONSParameter UnitInput Pulse Level0.4V to 2.2VInput Rise and Fall Times 5 nsInput and Output Timing 1.5Vand Reference LevelOutput Load See Figures 1 and 2AC TEST LOADSFigure 1Figure 26Integrated Circuit Solution Inc.IS62LV2568L IS62LV2568LLNotes:1.WE is HIGH for a Read Cycle.2.The device is continuously selected. OE , CE1 = VIL , CE2 = V IL .3.Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.AC WAVEFORMS(1,3)AC TEST LOADSREAD CYCLE NO.1(1,2)IS62LV2568L IS62LV2568LL-55-70-100SymbolParameter Min.Max.Min.Max.Min.Max Unit t WC Write Cycle Time 55 70 100 ns t SCE 1CE1 to Write End 45 65 80 ns t SCE 2CE2 to Write End45 65 80 ns t AW Address Setup Time to Write End 45 65 80 ns t HA Address Hold from Write End 0 0 0 ns t SA Address Setup Time 0 0 0 ns t PWE (4)WE Pulse Width 50 55 70 ns t SD Data Setup to Write End 25 30 40 ns t HDData Hold from Write End0 0 0 ns t HZWE (3)WE LOW to High-Z Output 25 25 30ns t LZWE (3)WE HIGH to Low-Z Output555nsNotes:1.Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to2.2V and output loading specified in Figure 1.2.Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.3.The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write.4.Tested with OE HIGH.WRITE CYCLE SWITCHING CHARACTERISTICS (1,2) (Over Operating Range, Standard and Low Power)AC WAVEFORMSWRITE CYCLE NO. 1 (WE Controlled )(1,2)IS62LV2568LIS62LV2568LLWRITE CYCLE NO. 2 (CE1, CE2 Controlled)(1,2)Notes:1.The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid statesto initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write.2.I/O will assume the HIGH-z state if OE =V IH.8Integrated Circuit Solution Inc.IS62LV2568L IS62LV2568LLDATA RETENTION SWITCHING CHARACTERISTICSSymbolParameterTest ConditionMin.Max.Unit V DRVcc for Data Retention See Data Retention Waveform 1.5 3.6V I DRData Retention CurrentVcc = 2.0V, CE1 ≥ Vcc 0.2VCom. (-L) 20µA Com. (-LL) 5µA Ind. (-L) 25µA Ind. (-LL)7µA t SDR Data Retention Setup Time See Data Retention Waveform 0ns t RDRRecovery TimeSee Data Retention Waveformt RCnsDATA RETENTION WAVEFORM (CE2 Controlled)DATA RETENTION WAVEFORM (CE1Controlled)IS62LV2568L IS62LV2568LLORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns)Order Part No.Package55IS62LV2568L-55T8*20mm TSOP-1IS62LV2568L-55H8*13.4mm TSOP-1IS62LV2568L-55B6*8mm TF-BGA 70IS62LV2568L-70T8*20mm TSOP-1IS62LV2568L-70H8*13.4mm TSOP-1IS62LV2568L-70B6*8mm TF-BGA 100IS62LV2568L-100T8*20mm TSOP-1IS62LV2568L-100H8*13.4mm TSOP-1IS62LV2568L-100B6*8mm TF-BGA Industrial Range: -40°C to +85°CSpeed (ns)Order Part No.Package55IS62LV2568L-55TI8*20mm TSOP-1IS62LV2568L-55HI8*13.4mm TSOP-1IS62LV2568L-55BI6*8mm TF-BGA70IS62LV2568L-70TI8*20mm TSOP-1IS62LV2568L-70HI8*13.4mm TSOP-1IS62LV2568L-70BI6*8mm TF-BGA100IS62LV2568L-100TI8*20mm TSOP-1IS62LV2568L-100HI8*13.4mm TSOP-1IS62LV2568L-100BI6*8mm TF-BGAIntegrated Circuit Solution Inc.HEADQUARTER:NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,HSIN-CHU, TAIWAN, R.O.C.TEL: 886-3-5780333Fax: 886-3-5783000BRANCH OFFICE:7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.TEL: 886-2-26962140FAX: 886-2-2696225210Integrated Circuit Solution Inc.。

IS62WV25616ALL IS62WV25616BLLISSI®Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.256K x 16 LOW VOLTAGE,ULTRA LOW POWER CMOS STATIC SRAMFEATURES•High-speed access time: 55ns, 70ns •CMOS low power operation 36 mW (typical) operating 9 µW (typical) CMOS standby •TTL compatible interface levels •Single power supply1.65V--2.2V V DD (IS62WV25616ALL)2.5V--3.6V V DD (IS62WV25616BLL)•Fully static operation: no clock or refresh required •Three state outputs•Data control for upper and lower bytes •Industrial temperature available •Lead-free availableDESCRIPTIONThe ISSI IS62WV25616ALL/IS62WV25616BLL are high-speed, low power, 4M bit SRAMs organized as 256K words by 16 bits. It is fabricated using ISSI 's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices.When CS1 is HIGH (deselected) or when CS1 is LOW and both LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels.Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE ) controls both writing and reading of the memory. A data byte allows Upper Byte (UB ) and Lower Byte (LB )access.The IS62WV25616ALL/IS62WV25616BLL are packaged in the JEDEC standard 44-Pin TSOP (TYPE II) and 48-pin mini BGA (6mmx8mm).MAY 20052 Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.C IS62WV25616ALL, IS62WV25616BLLISSI®PIN DESCRIPTIONSA0-A17Address Inputs I/O0-I/O15Data Inputs/Outputs CS1Chip Enable Input OE Output Enable Input WE Write Enable InputLB Lower-byte Control (I/O0-I/O7)UB Upper-byte Control (I/O8-I/O15)NC No Connection V DD Power GNDGround44-Pin mini TSOP (Type II)(Package Code T)1234567891011121314151617181920212244434241403938373635343332313029282726252423A4A3A2A1A0CS1I/O0I/O1I/O2I/O3V DD GND I/O4I/O5I/O6I/O7WE A16A15A14A13A12A5A6A7OE UB LB I/O15I/O14I/O13I/O12GND V DD I/O11I/O10I/O9I/O8NC A8A9A10A11A17PIN CONFIGURATIONS48- ball mini BGA (6mm x 8mm)(Package Code B)IS62WV25616ALL, IS62WV25616BLL ISSI®TRUTH TABLEI/O PINMode WE CS1OE LB UB I/O0-I/O7I/O8-I/O15V DD Current Not Selected X H X X X High-Z High-Z I SB1, I SB2X X X H H High-Z High-Z I SB1, I SB2 Output Disabled H L H L X High-Z High-Z I CCH L H X L High-Z High-Z I CCRead H L L L H D OUT High-Z I CCH L L H L High-Z D OUTH L L L L D OUT D OUTWrite L L X L H D IN High-Z I CCL L X H L High-Z D INL L X L L D IN D INABSOLUTE MAXIMUM RATINGS(1)Symbol Parameter Value UnitV TERM Terminal Voltage with Respect to GND–0.2 to V DD+0.3VV DD V DD Related to GND–0.2 to V DD+0.3VT STG Storage Temperature–65 to +150°CP T Power Dissipation 1.0WNote:1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. Thisis a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.OPERATING RANGE (V DD)Range Ambient Temperature IS62WV25616ALL IS62WV25616BLLCommercial0°C to +70°C 1.65V - 2.2V 2.5V-3.6VIndustrial–40°C to +85°C 1.65V - 2.2V 2.5V-3.6VDC ELECTRICAL CHARACTERISTICS(Over Operating Range)Symbol Parameter Test Conditions V DD Min.Max.Unit V OH Output HIGH Voltage I OH = -0.1 mA 1.65-2.2V 1.4—VI OH = -1 mA 2.5-3.6V 2.2—VV OL Output LOW Voltage I OL = 0.1 mA 1.65-2.2V—0.2VI OL = 2.1 mA 2.5-3.6V—0.4VV IH Input HIGH Voltage 1.65-2.2V 1.4V DD + 0.2V2.5-3.6V 2.2V DD + 0.3VV IL(1)Input LOW Voltage 1.65-2.2V–0.20.4V2.5-3.6V–0.20.6VI LI Input Leakage GND ≤ V IN≤ V DD–11µAI LO Output Leakage GND ≤ V OUT≤ V DD, Outputs Disabled–11µA Notes: 1. V IL (min.) = –1.0V for pulse width less than 10 ns.IS62WV25616ALL, IS62WV25616BLL ISSI®IS62WV25616ALL, POWER SUPPLY CHARACTERISTICS(1)(Over Operating Range)Symbol Parameter Test Conditions Max.Unit70I C C V DD D ynamic O perating V DD=M ax.,Com.25m ASupply C urrent I OUT = 0 mA, f = f MAX Ind.30I CC1Operating S upply V DD = Max., CS1 = 0.2V Com.10m ACurrent WE=V DD-0.2V Ind.10f=1MHZI SB1TTL Standby Current V DD=M ax.,Com.0.35m A(TTL Inputs)V IN = V IH or V IL Ind.0.35CS1 = V IH , f = 1 MH ZORULB Control V DD = Max., V IN = V IH or V ILCS1 = V IL, f = 0, UB = V IH, LB = V IHI SB2CMOS S tandby V DD=M ax.,Com.15µACurrent (CMOS Inputs)CS1≥V DD – 0.2V,Ind.15V IN≥V DD – 0.2V, orV IN≤ 0.2V, f = 0ORULB Control V DD = Max., CS1 = V IL,V IN≤ 0.2V, f = 0; UB / LB = V DD – 0.2VIS62WV25616BLL, POWER SUPPLY CHARACTERISTICS(1)(Over Operating Range)Symbol Parameter Test Conditions Max.Max.Unit5570I C C V DD D ynamic O perating V DD=M ax.,Com.4035m ASupply C urrent I OUT = 0 mA, f = f MAX Ind.4540I CC1Operating S upply V DD = Max., CS1 = 0.2V Com.1515m ACurrent WE=V DD-0.2V Ind.1515f=1MHZI SB1TTL Standby Current V DD=M ax.,Com.0.350.35m A(TTL Inputs)V IN = V IH or V IL Ind.0.350.35CS1 = V IH, f = 1 MH ZORULB Control V DD = Max., V IN = V IH or V ILCS1 = V IL, f = 0, UB = V IH, LB = V IHI SB2CMOS S tandby V DD=M ax.,Com.1515µACurrent (CMOS Inputs)CS1≥V DD – 0.2V,Ind.1515V IN≥V DD – 0.2V, orV IN≤ 0.2V, f = 0ORULB Control V DD = Max., CS1 = V IL,V IN≤ 0.2V, f = 0; UB / LB = V DD – 0.2V4 Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.CIS62WV25616ALL, IS62WV25616BLL ISSI®CAPACITANCE(1)Symbol Parameter Conditions Max.UnitC IN Input Capacitance V IN = 0V8pFC OUT Input/Output Capacitance V OUT = 0V10pFNote:1.Tested initially and after any design or process changes that may affect these parameters.AC TEST CONDITIONSIS62WV25616ALL IS62WV25616BLLParameter(Unit)(Unit)Input Pulse Level0.4V to V DD-0.2V0.4V to V DD-0.3VInput Rise and Fall Times 5 ns5nsInput and Output Timing V REF V REFand Reference LevelOutput Load See Figures 1 and 2See Figures 1 and 2IS62WV25616ALL IS62WV25616BLL1.65V-2.2V 2.5V -3.6VR1(Ω)30703070R2(Ω)31503150V REF0.9V 1.5VV TM 1.8V 2.8VFigure 1Figure 2IS62WV25616ALL, IS62WV25616BLL ISSI®READ CYCLE SWITCHING CHARACTERISTICS(1)(Over Operating Range)55 ns70 nsSymbol Parameter Min.Max.Min.Max.Unit t RC Read Cycle Time55—70—ns t AA Address Access Time—55—70ns t OHA Output Hold Time10—10—ns t ACS1CS1 Access Time—55—70ns t DOE OE Access Time—25—35ns t HZOE(2)OE to High-Z Output—20—25ns t LZOE(2)OE to Low-Z Output5—5—ns t HZCS1CS1 to High-Z Output020025ns t LZCS1CS1 to Low-Z Output10—10—ns t BA LB, UB Access Time—55—70ns t HZB LB, UB to High-Z Output020025ns t LZB LB, UB to Low-Z Output0—0—ns Notes:1.Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 toV DD-0.2V/V DD-0.3V and output loading specified in Figure 1.2.Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.6 Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.CIS62WV25616ALL, IS62WV25616BLL ISSI®AC WAVEFORMSREAD CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = V IL, WE = V IH, UB or LB = V IL)READ CYCLE NO. 2(1,3)(CS1, OE, AND UB/LB Controlled)Notes:1.WE is HIGH for a Read Cycle.2.The device is continuously selected. OE, CS1, UB, or LB = V IL. WE=V IH.3.Address is valid prior to or coincident with CS1 LOW transition.IS62WV25616ALL, IS62WV25616BLL ISSI®WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)55 ns70 nsSymbol Parameter Min.Max. Min.Max.Unit t WC Write Cycle Time 55— 70—ns t SCS1CS1 to Write End 45— 60—ns t AW Address Setup Time to Write End45— 60—ns t HA Address Hold from Write End0— 0—ns t SA Address Setup Time 0— 0—ns t PWB LB, UB Valid to End of Write45— 60—ns t PWE WE Pulse Width 40— 50—ns t SD Data Setup to Write End 25— 30—ns t HD Data Hold from Write End0— 0—ns t HZWE(3)WE LOW to High-Z Output—20 —20ns t LZWE(3)WE HIGH to Low-Z Output 5— 5—ns Notes:1.Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4V toV DD-0.2V/V DD-0.3V and output loading specified in Figure 1.2.The internal write time is defined by the overlap of CS1 LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one cango inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write.3.Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.8 Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.CIS62WV25616ALL, IS62WV25616BLL ISSI®AC WAVEFORMSWRITE CYCLE NO. 1(1,2)(CS1 Controlled, OE = HIGH or LOW)1.WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS1 and WE inputs and atleast one of the LB and UB inputs being in the LOW state.2.WRITE = (CS1) [ (LB) = (UB) ] (WE).WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)IS62WV25616ALL, IS62WV25616BLL ISSI®WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)WRITE CYCLE NO. 4 (UB/LB Controlled)10 Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.CIS62WV25616ALL, IS62WV25616BLL ISSI®DATA RETENTION SWITCHING CHARACTERISTICSSymbol Parameter Test Condition Min.Max.UnitV DR V DD for Data Retention See Data Retention Waveform 1.2 3.6VI DR Data Retention Current V DD = 1.2V, CS1≥ V DD – 0.2V—15µAt SDR Data Retention Setup Time See Data Retention Waveform0—nst RDR Recovery Time See Data Retention Waveform t RC—nsDATA RETENTION WAVEFORM (CS1 Controlled)IS62WV25616ALL, IS62WV25616BLL ISSI®ORDERING INFORMATIONIS62WV25616ALL (1.65V-2.2V)Commercial Range: 0°C to +70°CSpeed (ns)Order Part No.Package70IS62WV25616ALL-70T TSOPIndustrial Range: –40°C to +85°CSpeed (ns)Order Part No.Package70IS62WV25616ALL-70TI TSOP70IS62WV25616ALL-70BI mini BGA (6mmx8mm)IS62WV25616BLL (2.5V - 3.6V)Commercial Range: 0°C to +70°CSpeed (ns)Order Part No.Package55IS62WV25616BLL-55T TSOP70IS62WV25616BLL-70T TSOPIndustrial Range: –40°C to +85°CSpeed (ns)Order Part No.Package55IS62WV25616BLL-55TI TSOP55IS62WV25616BLL-55TLI TSOP, Lead-free55IS62WV25616BLL-55BI mini BGA (6mmx8mm)55IS62WV25616BLL-55BLI mini BGA (6mmx8mm), Lead-freePACKAGING INFORMATIONISSI®Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to Mini Ball Grid ArrayPackage Code: B (48-pin)PACKAGING INFORMATIONISSI®Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any timewithout notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to Plastic TSOPPackage Code: T (Type II)。

IS61LV25616AL3.3V的256K x 16高速静态随机存储器。

特点：◆高速存取时间：10，12ns◆CMOS低功耗工作◆低备用电源，低于5mA的备用电源◆TTL兼容接口电平◆ 3.3V电源单独供电◆全静态操作：无需刷新，无需时钟◆三态输出◆数据控制为上部或下部字节◆可在工业温度下使用说明：IS61LV25616AL是由高速的，4，194，304字节静态RAM，由16位的262，144字节组成。

并利用ISSI的高性能CMOS技术合成。

这种高可靠性的处理加上创新的电路设计技术，生产出高性能，低功耗的设备。

当/CE是高电平（悬空）时，设备呈现待机模式，并且此时的功耗可以降低到CMOS 输入时的功耗。

简单的存储器扩展是由芯片使能端和输出使能端来提供，/CE和/OE。

激活低电平的/WE 可以同时控制存储器的读和写。

数据字节既允许高字节（/UB）进入，也允许低字节(/LB)进入。

IS61LV25616AL被按照JEDEC（联合电子设备工程会议）分别打包成44引脚400mil （千分之一寸）J型塑料封装(SOJ)，44引脚微型薄片II式封装(TSOP)，44引脚小外形四方扁平封装(LQFP)和48引脚迷你球状栅级阵列型封装(BGA)（8mm x 10mm）。

原理框图如下：引脚配置：44引脚400mil（千分之一寸）J型塑料封装(SOJ)和44引脚微型薄片II式封装(TSOP)引脚功能介绍：A0—A17 地址输入端I/O0—I/O15 数据输入端/输出端/CE 芯片使能输入端/OE 输出使能输入端/WE 写使能输入端/LB 低字节控制端（I/O0—I/O7）/UB 高字节控制端（I/O8—I/O15）NC 无连接VDD 电源GND 接地44引脚小外形四方扁平封装(LQFP)48引脚迷你球状栅级阵列型封装(BGA)（8mm x 10mm）绝对最大额定参数V TERM 接地端的电压–0.5到VDD+0.5T STG存储温度–65到+150P T功率损耗 1.0说明：当表中所列出的参数超过绝对最大额定参数时会引起器件的毁坏。