IS62WV6416ALL中文资料
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IS62WV6416ALL IS62WV6416BLLISSI®Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.64K x 16 LOW VOLTAGE,ULTRA LOW POWER CMOS STATIC RAMFEATURES•High-speed access time: 45ns, 55ns •CMOS low power operation:30 mW (typical) operating 15 µW (typical) CMOS standby •TTL compatible interface levels •Single power supply1.7V--2.2V V DD (62WV6416ALL) 2.5V--3.6V V DD (62WV6416BLL)•Fully static operation: no clock or refresh required •Three state outputs•Data control for upper and lower bytes •Industrial temperature available •2CS Option Available •Lead-free availableDESCRIPTIONThe ISSI IS62WV6416ALL/ IS62WV6416BLL are high-speed, 1M bit static RAMs organized as 64K words by 16bits. It is fabricated using ISSI 's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices.When CS1 is HIGH (deselected) or when CS2 is LOW (deselected) or when CS1 is LOW, CS2 is HIGH and both LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels.Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE ) controls both writing and reading of the memory. A data byte allows Upper Byte (UB ) and Lower Byte (LB )access.The IS62WV6416ALL and IS62WV6416BLL are packaged in the JEDEC standard 48-pin mini BGA (6mm x 8mm) and 44-Pin TSOP (TYPE II).FUNCTIONAL BLOCK DIAGRAMJUNE 20052Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.B IS62WV6416ALL, IS62WV6416BLLISSI®PIN CONFIGURATIONS 48-Pin mini BGA (6mm x 8mm)(Package Code B)PIN DESCRIPTIONSA0-A15Address Inputs I/O0-I/O15Data Inputs/Outputs CS1, CS2Chip Enable Input OE Output Enable Input WE Write Enable InputLB Lower-byte Control (I/O0-I/O7)UB Upper-byte Control (I/O8-I/O15)NC No Connection V DD Power GNDGround48-Pin mini BGA (6mm x 8mm)2 CS Option (Package Code B2)44-Pin mini TSOP (Type II)(Package Code T)1 2 3 4 5 6A B C D E F G HLB OE A0A1A2CS2I/O 8UB A3A4CS1I/O 0I/O 9I/O 10A5A6I/O 1I/O 2GND I/O 11NC A7I/O 3V DD V DD I/O 12NC NC I/O 4GND I/O 14I/O 13A14A15I/O 5I/O 6I/O 15NC A12A13WE I/O 7NCA8A9A10A11NC1234567891011121314151617181920212244434241403938373635343332313029282726252423A4A3A2A1A0CS1I/O0I/O1I/O2I/O3V DD GND I/O4I/O5I/O6I/O7WE A15A14A13A12NC A5A6A7OE UB LB I/O15I/O14I/O13I/O12GND V DD I/O11I/O10I/O9I/O8NC A8A9A10A11NCIS62WV6416ALL, IS62WV6416BLL ISSI®TRUTH TABLEI/O PINMode WE CS1CS2OE LB UB I/O0-I/O7I/O8-I/O15V DD Current Not Selected X H X X X X High-Z High-Z I SB1, I SB2X X L X X X High-Z High-Z I SB1, I SB2X X X X H H High-Z High-Z I SB1, I SB2 Output Disabled H L H H L X High-Z High-Z I CCH L H H X L High-Z High-Z I CCRead H L H L L H D OUT High-Z I CCH L H L H L High-Z D OUTH L H L L L D OUT D OUTWrite L L H X L H D IN High-Z I CCL L H X H L High-Z D INL L H X L L D IN D INOPERATING RANGE (V DD)Range Ambient Temperature IS62WV6416ALL IS62WV6416BLLCommercial0°C to +70°C 1.7V - 2.2V 2.5V - 3.6VIndustrial–40°C to +85°C 1.7V - 2.2V 2.5V - 3.6VABSOLUTE MAXIMUM RATINGS(1)Symbol Parameter Value UnitV TERM Terminal Voltage with Respect to GND–0.2 to V DD+0.3VV DD V DD Related to GND–0.2 to +3.8VT STG Storage Temperature–65 to +150°CP T Power Dissipation 1.0WNote:1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is astress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.IS62WV6416ALL, IS62WV6416BLL ISSI®DC ELECTRICAL CHARACTERISTICS(Over Operating Range)Symbol Parameter Test Conditions V DD Min.Max.Unit V OH Output HIGH Voltage I OH = -0.1 mA 1.7-2.2V 1.4—VI OH = -1 mA 2.5-3.6V 2.2—VV OL Output LOW Voltage I OL = 0.1 mA 1.7-2.2V—0.2VI OL = 2.1 mA 2.5-3.6V—0.4VV IH Input HIGH Voltage 1.7-2.2V 1.4V DD + 0.2V2.5-3.6V 2.2V DD + 0.3VV IL(1)Input LOW Voltage 1.7-2.2V–0.20.4V2.5-3.6V–0.20.6VI LI Input Leakage GND ≤ V IN≤ V DD–11µAI LO Output Leakage GND ≤ V OUT≤ V DD, Outputs Disabled–11µA Notes:1.V IL (min.) = –1.0V for pulse width less than 10 ns.CAPACITANCE(1)Symbol Parameter Conditions Max.UnitC IN Input Capacitance V IN = 0V8pFC OUT Input/Output Capacitance V OUT = 0V10pFNote:1.Tested initially and after any design or process changes that may affect these parameters.4Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.BIS62WV6416ALL, IS62WV6416BLL ISSI®AC TEST CONDITIONSParameter62WV6416ALL62WV6416BLL(Unit)(Unit)Input Pulse Level0.4V to V DD-0.2V0.4V to V DD-0.3VInput Rise and Fall Times 5 ns5nsInput and Output Timing V REF V REFand Reference LevelOutput Load See Figures 1 and 2See Figures 1 and 2AC TEST LOADSFigure 1Figure 21.7-2.2V 2.5V -3.6VR1(Ω)30703070R2(Ω)31503150V REF0.9V 1.5VV TM 1.8V 2.8VIS62WV6416ALL, IS62WV6416BLL ISSI®IS62WV6416ALL, POWER SUPPLY CHARACTERISTICS(1)(Over Operating Range)Symbol Parameter Test Conditions Max.Unit55I C C V DD D ynamic O perating V DD=M ax.,Com.10m ASupply C urrent I OUT = 0 mA, f = f MAX Ind.10typ.(1)6I CC1Operating S upply V DD=M ax.,Com.5m ACurrent I OUT = 0 mA, f = 0Ind.5I SB1TTL Standby Current V DD=M ax.,Com. 1.2m A(TTL Inputs)V IN = V IH or V IL Ind. 1.2CS1= V IH, CS2 = V IL,f = 1 MH Z ORULB Control V DD = Max., V IN = V IH or V ILCS1 = V IL, f = 0, UB = V IH, LB = V IHI SB2CMOS S tandby V DD=M ax.,Com.10µACurrent (CMOS Inputs)CS1≥V DD – 0.2V,Ind.10CS2 ≤ 0.2V,typ.(1)4V IN≥V DD – 0.2V, orV IN≤ 0.2V, f = 0ORULB Control V DD = Max., CS1 = V IL, CS2=V IHV IN≤ 0.2V, f = 0; UB / LB = V DD – 0.2VNote:1.Typical values are measured at V DD=1.8V, T A=25o C. Not 100% tested.6Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.BIS62WV6416ALL, IS62WV6416BLL ISSI®IS62WV6416BLL, POWER SUPPLY CHARACTERISTICS(1)(Over Operating Range)Symbol Parameter Test Conditions Max.Max.Unit4555I C C V DD D ynamic O perating V DD=M ax.,Com.1715m ASupply C urrent I OUT = 0 mA, f = f MAX Ind.1715typ.(2)1210I CC1Operating S upply V DD=M ax.,Com.55m ACurrent I OUT = 0 mA, f = 0Ind.55I SB1TTL Standby Current V DD=M ax.,Com. 1.2 1.2m A(TTL Inputs)V IN = V IH or V IL Ind. 1.2 1.2CS1 = V IH , CS2 = V IL,f = 1 MH ZORULB Control V DD = Max., V IN = V IH or V ILCS1 = V IL, f = 0, UB = V IH, LB = V IHI SB2CMOS S tandby V DD=M ax.,Com.1515µACurrent (CMOS Inputs)CS1≥V DD – 0.2V,Ind.1515CS2 ≤ 0.2V,typ.(2)55V IN≥V DD – 0.2V, orV IN≤ 0.2V, f = 0ORULB Control V DD = Max., CS1 = V IL, CS2=V IHV IN≤ 0.2V, f = 0; UB / LB = V DD – 0.2VNote:1.At f = f MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.2.Typical values are measured at V DD=3.0V, T A=25o C. Not 100% tested.IS62WV6416ALL, IS62WV6416BLL ISSI®READ CYCLE SWITCHING CHARACTERISTICS(1)(Over Operating Range)45 ns 55 nsSymbol Parameter Min.Max.Min.Max.Unitt RC Read Cycle Time45—55—nst AA Address Access Time—45—55nst OHA Output Hold Time10—10—nst ACS1/t ACS2CS1/CS2 Access Time—45—55nst DOE OE Access Time—20—25nst HZOE(2)OE to High-Z Output—15—20nst LZOE(2)OE to Low-Z Output5—5—nst HZCS1/t HZCS2(2)CS1/CS2 to High-Z Output015020nst LZCS1/t LZCS2(2)CS1/CS2 to Low-Z Output10—10—nst BA LB, UB Access Time—45—55nst HZB LB, UB to High-Z Output015020nst LZB LB, UB to Low-Z Output0—0—nsNotes:1.Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 toV DD-0.2V/V DD-0.3V and output loading specified in Figure 1.2.Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.8Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.BIS62WV6416ALL, IS62WV6416BLL ISSI®AC WAVEFORMSREAD CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = V IL,CS2 = WE = V IH, UB or LB = V IL)AC WAVEFORMSREAD CYCLE NO. 2(1,3)(CS1,CS2, OE, AND UB/LB Controlled)Notes:1.WE is HIGH for a Read Cycle.2.The device is continuously selected. OE, CS1, UB, or LB = V IL. CS2=WE=V IH.3.Address is valid prior to or coincident with CS1 LOW transition.IS62WV6416ALL, IS62WV6416BLL ISSI®WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)45ns 55 nsSymbol Parameter Min.Max. Min.Max.Unitt WC Write Cycle Time 45— 55—nst SCS1/t SCS2CS1/CS2 to Write End 35— 45—nst AW Address Setup Time to Write End 35— 45—nst HA Address Hold from Write End 0— 0—nst SA Address Setup Time 0— 0—nst PWB LB, UB Valid to End of Write 35— 45—nst PWE WE Pulse Width 35— 40—nst SD Data Setup to Write End 20— 25—nst HD Data Hold from Write End 0— 0—nst HZWE(3)WE LOW to High-Z Output —20 —20nst LZWE(3)WE HIGH to Low-Z Output 5— 5—nsNotes:1.Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4V toV DD-0.2V/V DD-0.3V and output loading specified in Figure 1.2.The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be invalid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write.3.Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.AC WAVEFORMSWRITE CYCLE NO. 1(1,2)(CS1 Controlled, OE = HIGH or LOW)Notes:1.WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS1 , CS2 and WE inputs and atleast one of the LB and UB inputs being in the LOW state.2.WRITE = (CS1) [ (LB) = (UB) ] (WE).10Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.BIS62WV6416ALL, IS62WV6416BLL ISSI®WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)IS62WV6416ALL, IS62WV6416BLL ISSI®WRITE CYCLE NO. 4 (UB/LB Controlled)IS62WV6416ALL, IS62WV6416BLLISSI®DATA RETENTION WAVEFORM (CS1 Controlled)DATA RETENTION SWITCHING CHARACTERISTICSSymbolParameterTest ConditionMin.Max.Unit V DRV DD for Data Retention See Data Retention Waveform 1.2 3.6V I DRData Retention Current V DD = 1.2V, CS1 ≥ V DD – 0.2V —5µA t SDR Data Retention Setup Time See Data Retention Waveform 0—ns t RDRRecovery TimeSee Data Retention Waveformt RC—nsDATA RETENTION WAVEFORM(CS2 Controlled)IS62WV6416ALL, IS62WV6416BLL ISSI®ORDERING INFORMATIONIS62WV6416ALL (1.7V - 2.2V)Commercial Range: 0°C to +70°CSpeed (ns)Order Part No.Package55IS62WV6416ALL-55T TSOP-IIIS62WV6416ALL-55B mini BGA (6mm x 8mm)Industrial Range: –40°C to +85°CSpeed (ns)Order Part No.Package55IS62WV6416ALL-55TI TSOP-IIIS62WV6416ALL-55TLI TSOP-II, Lead-freeIS62WV6416ALL-55BI mini BGA (6mm x 8mm)IS62WV6416ALL-55BLI mini BGA (6mm x 8mm), Lead-freeIS62WV6416ALL-55B2I mini BGA (6mm x 8mm), 2 CS OptionIS62WV6416ALL, IS62WV6416BLL ISSI®ORDERING INFORMATIONIS62WV6416BLL (2.5V - 3.6V)Commercial Range: 0°C to +70°CSpeed (ns)Order Part No.Package45IS62WV6416BLL-45T TSOP-IIIS62WV6416BLL-45B mini BGA (6mm x 8mm)Industrial Range: –40°C to +85°CSpeed (ns)Order Part No.Package45IS62WV6416BLL-45TI TSOP-IIIS62WV6416BLL-45BI mini BGA (6mm x 8mm)55IS62WV6416BLL-55TI TSOP-IIIS62WV6416BLL-55TLI TSOP-II, Lead-freeIS62WV6416BLL-55BI mini BGA (6mm x 8mm)IS62WV6416BLL-55BLI mini BGA (6mm x 8mm), Lead-freeIS62WV6416BLL-55B2I mini BGA (6mm x 8mm), 2 CS OptionPACKAGING INFORMATIONISSI®Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to Mini Ball Grid ArrayPackage Code: B (48-pin)PACKAGING INFORMATIONISSI®Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any timewithout notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to Plastic TSOPPackage Code: T (Type II)。