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IS61LPS25618A-200TQ中文资料

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Integrated Silicon Solution, Inc. — 1-800-379-47741Rev.00A 10/07/04ISSI®Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.IS61(64)LPS12832AIS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618AFEATURES•Internal self-timed write cycle•Individual Byte Write Control and Global Write •Clock controlled, registered address, data and control •Burst sequence control using MODE input •Three chip enable option for simple depth expansion and address pipelining •Common data inputs and data outputs •Auto Power-down during deselect •Single cycle deselect•Snooze MODE for reduced-power standby •Power SupplyLPS: V DD 3.3V + 5%, V DDQ 3.3V/2.5V + 5%VPS: V DD 2.5V + 5%, V DDQ 2.5V + 5%•JEDEC 100-Pin TQFP, 119-ball PBGA, and 165-ball PBGA packages •Automotive temperature available •Lead Free availableDESCRIPTIONThe ISSI IS61(64)LPS12832A, IS61(64)LPS/VPS12836Aand IS61(64)LPS/VPS25618A are high-speed, low-power synchronous static RAMs designed to provide burstable,high-performance memory for communication and network-ing applications. The IS61(64)LPS12832A is organized as 131,072 words by 32 bits. The IS61(64)LPS/VPS12836A is organized as 131,072 words by 36 bits. The IS61(64)LPS/VPS25618A is organized as 262,144 words by 18 bits.Fabricated with ISSI 's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single mono-lithic circuit. All synchronous inputs pass through regis-ters controlled by a positive-edge-triggered single clock input.Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be one to four bytes wide as controlled by the write control inputs.Separate byte enables allow individual bytes to be written.The byte write operation is performed by using the byte write enable (BWE ) input combined with one or more individual byte write signals (BWx ). In addition, Global Write (GW ) is available for writing all bytes at one time,regardless of the byte write controls.Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller)input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin.The mode pin is used to select the burst sequence order,Linear burst is achieved when this pin is tied LOW.Interleave burst is achieved when this pin is tied HIGH or left floating.128K x 32, 128K x 36, 256K x 184 Mb SYNCHRONOUS PIPELINED,SINGLE CYCLE DESELECT STATIC RAMPRELIMINARY INFORMATIONFEBRUARY 2005FAST ACCESS TIMESymbol Parameter250200Units t KQ Clock Access Time 2.6 3.1ns t KCCycle Time 45ns Frequency250200MHz2Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.00A 10/07/04ISSI®IS61(64)LPS12832AIS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618ABLOCK DIAGRAMIntegrated Silicon Solution, Inc. — 1-800-379-47743Rev.00A 10/07/04ISSI®IS61(64)LPS12832AIS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A165-PIN BGA165-Ball, 13x15 mm BGA 1mm Ball Pitch, 11x15 Ball Array119-PIN BGA119-Ball, 14x22 mm BGA 1mm Ball Pitch, 7x17 Ball Array4Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.00A 10/07/04ISSI®IS61(64)LPS12832AIS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A119 BGA PACKAGE PIN CONFIGURATION128K X 36 (TOP VIEW)PIN DESCRIPTIONS1234567A V DDQ A A ADSP A A V DDQB NC CE2A ADSC A CE2 NC C NC A A V DD A A NC D DQc DQPc Vss NC Vss DQPb DQbE DQc DQc Vss CE Vss DQb DQbF V DDQ DQc Vss OE Vss DQb V DDQG DQc DQc BWc ADV BWb DQb DQbH DQc DQc Vss GW Vss DQb DQb J V DDQ V DD NC V DD NC V DD V DDQ K DQd DQd Vss CLK Vss DQa DQa L DQd DQd BWd NC BWa DQa DQa M V DDQ DQd Vss BWE Vss DQa V DDQ N DQd DQd Vss A 1*Vss DQa DQa P DQd DQPd Vss A 0*Vss DQPa DQa R NC A MODE V DD NC A NC T NC NC A A A NC ZZ UV DDQNCNCNCNCNC V DDQSymbol Pin NameA Address InputsA0, A1Synchronous Burst Address Inputs ADV Synchronous Burst Address AdvanceADSP Address Status Processor ADSC Address Status Controller GW Global Write Enable CLKSynchronous Clock CE , CE2, CE2Synchronous Chip Select BW x (x=a-d)Synchronous Byte Write Controls BWEByte Write EnableSymbol Pin Name OE Output Enable ZZ Power Sleep Mode MODE Burst Sequence Selection NC No Connect DQa-DQd Data Inputs/Outputs DQPa-Pd Output Power Supply V DD Power Supply V DDQ Output Power Supply VssGroundNote: * A 0 and A 1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.Integrated Silicon Solution, Inc. — 1-800-379-47745Rev.00A 10/07/04ISSI®IS61(64)LPS12832AIS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A119 BGA PACKAGE PIN CONFIGURATION256K X 18 (TOP VIEW)PIN DESCRIPTIONSNote: * A 0 and A 1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.1234567A V DDQ A A ADSP A A V DDQB NC CE2A ADSC A CE2 NC C NC A A V DD A A NC D DQb NC Vss NC Vss DQPa NCE NC DQb Vss CE Vss NC DQaF V DDQ NC Vss OE Vss DQa V DDQG NC DQb BWb ADV Vss NC DQaH DQb NC Vss GW Vss DQa NC J V DDQ V DD NC V DD NC V DD V DDQ K NC DQb Vss CLK Vss NC DQa L DQb NC Vss NC BWa DQa NC M V DDQ DQb Vss BWE Vss NC V DDQ N DQb NC Vss A 1*Vss DQa NC P NC DQPb Vss A 0*Vss NC DQa R NC A MODE V DD NC A NC T NC A A NC A A ZZ UV DDQNCNCNCNCNC V DDQ Symbol Pin NameA Address InputsA0, A1Synchronous Burst Address Inputs ADV Synchronous Burst Address AdvanceADSP Address Status Processor ADSC Address Status Controller GW Global Write Enable CLKSynchronous Clock CE , CE2, CE2Synchronous Chip Select BW x (x=a,b)Synchronous Byte Write Controls BWEByte Write EnableSymbol Pin Name OE Output Enable ZZ Power Sleep Mode MODE Burst Sequence Selection NC No Connect DQa-DQb Data Inputs/Outputs DQPa-Pb Output Power Supply V DD Power Supply V DDQ Output Power Supply VssGround6Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.00A 10/07/04ISSI®IS61(64)LPS12832AIS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618APIN DESCRIPTIONS165 PBGA PACKAGE PIN CONFIGURATION128K X 36 (TOP VIEW)Note: * A 0 and A 1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.1234567891011A NC A CE BWc BWb CE2BWE ADSC ADV A NC B NC A CE2BWd BWa CLK GW OE ADSP A NC C DQPc NC V DDQ Vss Vss Vss Vss Vss V DDQ NC DQPbD DQc DQc V DDQ V DD Vss Vss Vss V DD V DDQ DQb DQbE DQc DQc V DDQ V DD Vss Vss Vss V DD V DDQ DQb DQbF DQc DQc V DDQ V DD Vss Vss Vss V DD V DDQ DQb DQbG DQc DQc V DDQ V DD Vss Vss Vss V DD V DDQ DQb DQbH NC NC NC V DD Vss Vss Vss V DD NC NC ZZ J DQd DQd V DDQ V DD Vss Vss Vss V DD V DDQ DQa DQa K DQd DQd V DDQ V DD Vss Vss Vss V DD V DDQ DQa DQa L DQd DQd V DDQ V DD Vss Vss Vss V DD V DDQ DQa DQa M DQd DQd V DDQ V DD Vss Vss Vss V DD V DDQ DQa DQa N DQPd NC V DDQ Vss NC NC NC Vss V DDQ NC DQPaP NC NC A A NC A 1*NC A A A NC RMODENCAANCA 0*NCAAAASymbol Pin NameA Address InputsA0, A1Synchronous Burst Address Inputs ADV Synchronous Burst Address AdvanceADSP Address Status Processor ADSC Address Status Controller GW Global Write Enable CLKSynchronous Clock CE , CE2, CE2Synchronous Chip SelectBW x (x=a,b,c,d)Synchronous Byte WriteControlsSymbol Pin Name BWE Byte Write Enable OE Output Enable ZZ Power Sleep Mode MODE Burst Sequence Selection NC No ConnectDQx Data Inputs/Outputs DQPx Data Inputs/OutputsV DD 3.3V/2.5V Power SupplyV DDQIsolated Output Power Supply 3.3V /2.5V VssGroundIntegrated Silicon Solution, Inc. — 1-800-379-47747Rev.00A 10/07/04ISSI®IS61(64)LPS12832AIS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618ANote: * A 0 and A 1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.165 PBGA PACKAGE PIN CONFIGURATION256K X 18 (TOP VIEW)PIN DESCRIPTIONS1234567891011A NC A CE BWb NC CE2BWE ADSC ADV A A B NC A CE2NC BWa CLK GW OE ADSP A NC C NC NC V DDQ Vss Vss Vss Vss Vss V DDQ NC DQPa D NC DQb V DDQ V DD Vss Vss Vss V DD V DDQ NC DQa E NC DQb V DDQ V DD Vss Vss Vss V DD V DDQ NC DQa F NC DQb V DDQ V DD Vss Vss Vss V DD V DDQ NC DQa G NC DQb V DDQ V DD Vss Vss Vss V DD V DDQ NC DQa H NC NC NC V DD Vss Vss Vss V DD NC NC ZZ J DQb NC V DDQ V DD Vss Vss Vss V DD V DDQ DQa NC K DQb NC V DDQ V DD Vss Vss Vss V DD V DDQ DQa NC L DQb NC V DDQ V DD Vss Vss Vss V DD V DDQ DQa NC M DQb NC V DDQ V DD Vss Vss Vss V DD V DDQ DQa NC N DQPb NC V DDQ Vss NC NC NC Vss V DDQ NC NC P NC NC A A NC A 1*NC A A A NC RMODENCAANCA 0*NCAAAASymbol Pin NameA Address InputsA0, A1Synchronous Burst Address Inputs ADV Synchronous Burst Address AdvanceADSP Address Status Processor ADSC Address Status Controller GW Global Write Enable CLKSynchronous Clock CE , CE2, CE2Synchronous Chip Select BW x (x=a,b)Synchronous Byte Write ControlsSymbol Pin NameBWE Byte Write Enable OE Output Enable ZZ Power Sleep Mode MODE Burst Sequence Selection NC No ConnectDQx Data Inputs/Outputs DQPx Data Inputs/OutputsV DD 3.3V/2.5V Power SupplyV DDQIsolated Output Power Supply 3.3V/2.5V VssGround8Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.00A 10/07/04ISSI®IS61(64)LPS12832AIS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618APIN DESCRIPTIONSA0, A1Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus.A Synchronous Address Inputs ADSC Synchronous Controller Address StatusADSP Synchronous Processor Address StatusADV Synchronous Burst Address Advance BWa -BWd Synchronous Byte Write Enable BWESynchronous Byte Write EnableCE , CE2, CE2Synchronous Chip Enable CLK Synchronous ClockDQa-DQd Synchronous Data Input/Output DQPa-DQPd Parity Data Input/OutputGW Synchronous Global Write Enable MODE Burst Sequence Mode Selection OE Output EnableV DD 3.3V/2.5V Power Supply V DDQ Isolated Output Buffer Supply:3.3V/2.5V Vss Ground ZZSnooze EnablePIN CONFIGURATION100-PIN TQFP (128K X 32)100-PIN TQFP (128K X 36)Integrated Silicon Solution, Inc. — 1-800-379-47749Rev.00A 10/07/04ISSI®IS61(64)LPS12832AIS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618APIN CONFIGURATIONPIN DESCRIPTIONSA0, A1Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus.A Synchronous Address Inputs ADSC Synchronous Controller Address Status ADSP Synchronous Processor Address Status ADV Synchronous Burst Address Advance BWa -BWb Synchronous Byte Write Enable BWE Synchronous Byte Write Enable CE , CE2, CE2Synchronous Chip EnableCLK Synchronous ClockDQa-DQbSynchronous Data Input/OutputDQPa-DQPb Parity Data I/O; DQPa is parity for DQa1-8; DQPb is parity for DQb1-8GW Synchronous Global Write Enable MODE Burst Sequence Mode Selection OE Output EnableV DD 3.3V/2.5V Power Supply V DDQ Isolated Output Buffer Supply:3.3V/2.5V Vss Ground ZZSnooze Enable100-PIN TQFP (256K X 18)10Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.00A 10/07/04ISSI®IS61(64)LPS12832AIS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618APARTIAL TRUTH TABLEFunction GW BWE BWa BWb BWc BWd Read H H X X X X ReadH L H H H H Write Byte 1H L L H H H Write All Bytes H L L L L L Write All Bytes LXXXXXTRUTH TABLE (1-8)OPERATIONADDRESS CE CE2CE2ZZ ADSP ADSC ADV WRITE OE CLK DQDeselect Cycle, Power-Down None H X X L X L X X X L-H High-Z Deselect Cycle, Power-Down None L X L L L X X X X L-H High-Z Deselect Cycle, Power-Down None L H X L L X X X X L-H High-Z Deselect Cycle, Power-Down None L X L L H L X X X L-H High-Z Deselect Cycle, Power-Down None L H X L H L X X X L-H High-Z Snooze Mode, Power-Down None X X X H X X X X X X High-Z Read Cycle, Begin Burst External L L H L L X X X L L-H Q Read Cycle, Begin Burst External L L H L L X X X H L-H High-Z Write Cycle, Begin Burst External L L H L H L X L X L-H D Read Cycle, Begin Burst External L L H L H L X H L L-H Q Read Cycle, Begin Burst External L L H L H L X H H L-H High-Z Read Cycle, Continue Burst Next X X X L H H L H L L-H Q Read Cycle, Continue Burst Next X X X L H H L H H L-H High-Z Read Cycle, Continue Burst Next H X X L X H L H L L-H Q Read Cycle, Continue Burst Next H X X L X H L H H L-H High-Z Write Cycle, Continue Burst Next X X X L H H L L X L-H D Write Cycle, Continue Burst Next H X X L X H L L X L-H D Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q Read Cycle, Suspend Burst Current X X X L H H H H H L-H High-Z Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q Read Cycle, Suspend Burst Current H X X L X H H H H L-H High-Z Write Cycle, Suspend Burst Current X X X L H H H L X L-H D Write Cycle, Suspend BurstCurrentHXXLXHHLXL-HDNOTE:1.X means “Don’t Care.” H means logic HIGH. L means logic LOW.2.For WRITE , L means one or more byte write enable signals (BWa-d ) and BWE are LOW or GW is LOW. WRITE = H for all BWx , BWE , GW HIGH.3.BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and DQPc. BWd enables WRITEs to DQd’s and DQPd. DQPa and DQPb are available on the x18 version.DQPa-DQPd are available on the x36 version.4.All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.5.Wait states are inserted by suspending burst.6.For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during the input data hold time.7.This device contains circuitry that will ensure the outputs will be in High-Z during power-up.8.ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.INTERLEAVED BURST ADDRESS TABLE (MODE = V DD or No Connect) External Address1st Burst Address2nd Burst Address3rd Burst Address A1A0A1A0A1A0A1A000011011010011101011000111100100 LINEAR BURST ADDRESS TABLE (MODE = VSS)ABSOLUTE MAXIMUM RATINGS(1)Symbol Parameter Value UnitT STG Storage Temperature–55 to +150°CP D Power Dissipation 1.6WI OUT Output Current (per I/O)100mAV IN, V OUT Voltage Relative to Vss for I/O Pins–0.5 to V DDQ + 0.5VV IN Voltage Relative to Vss for–0.5 to V DD + 0.5Vfor Address and Control InputsV DD Voltage on V DD Supply Relative to Vss–0.5 to 4.6VNotes:1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-nent damage to the device. This is a stress rating only and functional operation of the device atthese or any other conditions above those indicated in the operational sections of thisspecification is not implied. Exposure to absolute maximum rating conditions for extendedperiods may affect reliability.2. This device contains circuity to protect the inputs against damage due to high static voltages orelectric fields; however, precautions may be taken to avoid application of any voltage higher thanmaximum rated voltages to this high-impedance circuit.3. This device contains circuitry that will ensure the output devices are in High-Z at power up.OPERATING RANGE (IS61/64LPSXXXXX)Range Ambient Temperature V DD V DDQCommercial0°C to +70°C 3.3V + 5% 3.3V / 2.5V + 5%Industrial–40°C to +85°C 3.3V + 5% 3.3V / 2.5V + 5%Automotive–40°C to +125°C 3.3V + 5% 3.3V / 2.5V + 5%OPERATING RANGE (IS61/64VPSXXXXX)Range Ambient Temperature V DD V DDQCommercial0°C to +70°C 2.5V + 5% 2.5V + 5%Industrial–40°C to +85°C 2.5V + 5% 2.5V + 5%Automotive–40°C to +125°C 2.5V + 5% 2.5V + 5%DC ELECTRICAL CHARACTERISTICS (Over Operating Range)3.3V 2.5VSymbol Parameter Test Conditions Min.Max.Min.Max.UnitV OH Output HIGH Voltage I OH = –4.0 mA (3.3V) 2.4— 2.0—VI OH = –1.0 mA (2.5V)V OL Output LOW Voltage I OL = 8.0 mA (3.3V)—0.4—0.4VI OL = 1.0 mA (2.5V)V IH Input HIGH Voltage 2.0V DD + 0.3 1.7V DD + 0.3VV IL Input LOW Voltage-0.30.8-0.30.7VI LI Input Leakage Current Vss ≤ V IN≤ V DD(1)-55-55µAI LO Output Leakage Current Vss ≤ V OUT≤ V DDQ,-55-55µAOE = V IH12Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.00APOWER SUPPLY CHARACTERISTICS(1)(Over Operating Range)-250-200MAX MAXSymbol Parameter Test Conditions Temp. r ange x18x32/x36x18x32/x36Uni t I CC AC Operating Device Selected,Com.225225200200mASupply Current OE = V IH, ZZ ≤ V IL,Ind.250250210210All Inputs ≤ 0.2V or Auto.275275225225≥ V DD – 0.2V,Cycle Time ≥ t KC min.I SB Standby Current Device Deselected,Com.90909090mATTL Input V DD = Max.,Ind.100100100100All Inputs ≤ V IL or ≥ V IH,Auto.120120120120ZZ ≤ V IL, f = Max.I SBI Standby Current Device Deselected,Com.70707070mACMOS Input V DD = Max.,Ind.75757575V IN≤ V SS + 0.2V or Auto.90909090≥V DD – 0.2V typ.(2) 40 40f = 0I SB2Sleep Mode ZZ>V IH Com.30303030mAInd.35353535Auto.45454545typ.(2) 25 25Note:1.MODE pin has an internal pullup and should be tied to V DD or V SS. It exhibits ±100µA maximum leakage current when tied to ≤V SS + 0.2V or ≥ V DD – 0.2V.2. Typical values are measured at V DD =3.3V, T A = 25o C and not 100% tested.14Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.00A CAPACITANCE (1,2)Symbol Parameter Conditions Max.Unit C IN Input Capacitance V IN = 0V 6pF C OUTInput/Output CapacitanceV OUT = 0V8pFNotes:1.Tested initially and after any design or process changes that may affect these parameters.2.Test conditions: T A = 25°C, f = 1 MHz, V DD =3.3V.3.3V I/O AC TEST CONDITIONSParameterUnit Input Pulse Level0V to 3.0V Input Rise and Fall Times 1.5 ns Input and Output Timing 1.5V and Reference Level Output LoadSee Figures 1 and 2AC TEST LOADSFigure 2Figure 12.5V I/O AC TEST CONDITIONSParameterUnit Input Pulse Level0V to 2.5V Input Rise and Fall Times 1.5 ns Input and Output Timing 1.25V and Reference Level Output LoadSee Figures 3 and 42.5 I/O OUTPUT LOAD EQUIVALENTFigure 4Figure 3READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)-250 -200Symbol Parameter Min.Max.Min.Max.Unitf MAX Clock Frequency—250—200MHzt KC Cycle Time 4.0—5—nst KH Clock High Time 1.7—2—nst KL Clock Low Time 1.7—2—nst KQ Clock Access Time— 2.6— 3.1nst KQX(2)Clock High to Output Invalid0.8— 1.5—nst KQLZ(2,3)Clock High to Output Low-Z0.8—1—nst KQHZ(2,3)Clock High to Output High-Z— 2.6— 3.0nst OEQ Output Enable to Output Valid— 2.8— 3.1nst OELZ(2,3)Output Enable to Output Low-Z0—0—nst OEHZ(2,3)Output Disable to Output High-Z— 2.6— 3.0nst AS Address Setup Time 1.2— 1.4—nst WS Read/Write Setup Time 1.2— 1.4—nst CES Chip Enable Setup Time 1.2— 1.4—nst AVS Address Advance Setup Time 1.2— 1.4—nst DS Data Setup Time 1.2— 1.4—nst AH Address Hold Time0.3—0.4—nst WH Write Hold Time0.3—0.4—nst CEH Chip Enable Hold Time0.3—0.4—nst AVH Address Advance Hold Time0.3—0.4—nst DH Data Hold Time0.3—0.4—nst PDS ZZ High to Power Down—2—2cyct PUS ZZ Low to Power Down—2—2cycNote:1. Configuration signal MODE is static and must not change during normal operation.2. Guaranteed but not 100% tested. This parameter is periodically sampled.3.Tested with load in Figure 2.16Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.00AREAD/WRITE CYCLE TIMINGWRITE CYCLE TIMING18Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.00ASNOOZE MODE ELECTRICAL CHARACTERISTICSSymbol Parameter Conditions Min.Max.UnitI SB2Current during SNOOZE MODE ZZ ≥ Vih—60mAt PDS ZZ active to input ignored—2cycle t PUS ZZ inactive to input sampled2—cycle t ZZI ZZ active to SNOOZE current—2cycle t RZZI ZZ inactive to exit SNOOZE current0—nsSNOOZE MODE TIMINGORDERING INFORMATION (3.3V core/2.5V-3.3V I/O)Commercial Range: 0°C to +70°CConfiguration Frequency Order Part Number Package128Kx32250IS61LPS12832A-250TQ100 TQFPIS61LPS12832A-250B2119 PBGAIS61LPS12832A-250B3165 PBGA200IS61LPS12832A-200TQ 100 TQFPIS61LPS12832A-200B2119 PBGAIS61LPS12832A-200B3165 PBGA128Kx36250IS61LPS12836A-250TQ100 TQFPIS61LPS12836A-250B2119 PBGAIS61LPS12836A-250B3165 PBGA200IS61LPS12836A-200TQ 100 TQFPIS61LPS12836A-200B2119 PBGAIS61LPS12836A-200B3165 PBGA256Kx18250IS61LPS25618A-250TQ100 TQFPIS61LPS25618A-250B2119 PBGAIS61LPS25618A-250B3165 PBGA200IS61LPS25618A-200TQ100 TQFPIS61LPS25618A-200B2119 PBGAIS61LPS25618A-200B3165 PBGA20Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.00AISSI®IS61(64)LPS12832AIS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618AORDERING INFORMATION (3.3V core/2.5V-3.3V I/O)Industrial Range: -40°C to +85°CConfiguration FrequencyOrder Part NumberPackage128Kx32250IS61LPS12832A-250TQI 100 TQFP IS61LPS12832A-250B2I 119 PBGA IS61LPS12832A-250B3I 165 PBGA200IS61LPS12832A-200TQI 100 TQFPIS61LPS12832A-200TQLI 100 TQFP, Lead-free IS61LPS12832A-200B2I 119 PBGA IS61LPS12832A-200B3I 165 PBGA 128Kx36250IS61LPS12836A-250TQI 100 TQFP IS61LPS12836A-250B2I 119 PBGA IS61LPS12836A-250B3I 165 PBGA200IS61LPS12836A-200TQI 100 TQFPIS61LPS12836A-200TQLI 100 TQFP, Lead-free IS61LPS12836A-200B2I 119 PBGA IS61LPS12836A-200B3I 165 PBGA 256Kx18250IS61LPS25618A-250TQI 100 TQFP IS61LPS25618A-250B2I 119 PBGA IS61LPS25618A-250B3I 165 PBGA200IS61LPS25618A-200TQI 100 TQFPIS61LPS25618A-200TQLI 100 TQFP, Lead-free IS61LPS25618A-200B2I 119 PBGA IS61LPS25618A-200B3I165 PBGAAutomotive Range: -40°C to +125°CConfiguration FrequencyOrder Part NumberPackage128Kx32200IS64LPS12832A-200TQA3100 TQFP128Kx36200IS64LPS12836A-200TQA3100 TQFP256Kx18200IS64LPS25618A-200TQA3100 TQFPISSI®IS61(64)LPS12832AIS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618AORDERING INFORMATION (2.5V core/2.5V I/O)Commercial Range: 0°C to +70°CConfiguration FrequencyOrder Part NumberPackage128Kx36250IS61VPS12836A-250TQ 100 TQFP IS61VPS12836A-250B2119 PBGA IS61VPS12836A-250B3165 PBGA 200IS61VPS12836A-200TQ 100 TQFP IS61VPS12836A-200B2119 PBGA IS61VPS12836A-200B3165 PBGA256Kx18250IS61VPS25618A-250TQ 100 TQFP IS61VPS25618A-250B2119 PBGA IS61VPS25618A-250B3165 PBGA 200IS61VPS25618A-200TQ 100 TQFP IS61VPS25618A-200B2119 PBGA IS61VPS25618A-200B3165 PBGAISSI®IS61(64)LPS12832AIS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618AIndustrial Range: -40°C to +85°CConfiguration FrequencyOrder Part NumberPackage128Kx36250IS61VPS12836A-250TQI 100 TQFP IS61VPS12836A-250B2I 119 PBGA IS61VPS12836A-250B3I 165 PBGA 200IS61VPS12836A-200TQI 100 TQFP IS61VPS12836A-200B2I 119 PBGA IS61VPS12836A-200B3I 165 PBGA 256Kx18250IS61VPS25618A-250TQI 100 TQFP IS61VPS25618A-250B2I 119 PBGA IS61VPS25618A-250B3I 165 PBGA 200IS61VPS25618A-200TQI 100 TQFP IS61VPS25618A-200B2I 119 PBGA IS61VPS25618A-200B3I165 PBGAAutomotive Range: -40°C to +125°CConfiguration FrequencyOrder Part NumberPackage128Kx32200IS64VPS12832A-200TQA3100 TQFP128Kx36200IS64VPS12836A-200TQA3100 TQFP256Kx18200IS64VPS25618A-200TQA3100 TQFPPACKAGING INFORMATIONISSI®Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to Plastic Ball Grid ArrayPackage Code: B (119-pin)PACKAGING INFORMATIONISSI®Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised toBall Grid ArrayPackage Code: B (165-pin)PACKAGING INFORMATION ISSI®TQFP (Thin Quad Flat Pack Package)Package Code: TQ。

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LM2596T中文资料

LM2596T中文资料

LM2596T中文资料元器件交易网/doc/a66360844.html,3.0A, 150Khz, Step-Down Switching RegulatorFEATURES3.3V, 5.0V, 12V, 15V, and Adjustable Output Versions Adjustable Version Output Voltage Range, 1.23 to 37V +/- 4%. Maximum Over Line and Load Conditions Guaranteed 3.0A Output Current Wide Input Voltage Range Requires Only 4 External Components 150Khz Fixed Frequency Internal Oscillator TTL Shutdown Capability, Low Power Standby Mode High Efficiency Uses Readily Available Standard Inductors Thermal Shutdown and Current Limit Protection Moisture Sensitivity Level(MSL) Equals1 TO-263(D2) TO-220V TO-220LM2596ApplicationsSimple High-Efficiency Step-Down(Buck) Regulator Efficient Pre-Regulator for Linear Regulators On-Card Switching Regulators Positive to Negative Converter(Buck-Boost) Negative Step-Up Converters Power Supply for Battery Chargers1. 2. 3. 4. 5. Vin Output Ground Feedback On/OffDESCRIPTIONThe LM2596 series of regulators are monolithic integrated circuits ideally suited for easy and convenient design of a step-down switching regualtor(buck converter). All circuits of this series are capable of driving a 3.0A load with excellent line and load regulation. These devices are available in fixed output voltages of 3.3V, 5.0V,12V, 15V, and an adjustable output version.ORDERING INFORMATIONDevice LM2596T-X.X LM2596TV-X.X LM2596R MarkingLM2596T-X.X LM2596T-X.X LM2596R-X.X Package TO-220 TO-220V TO-263These regulatiors were designed to minimize the number of externalcomponents to simplify the power supply design. Standard series of inductors optimized for use with the LM2576 are offered by several different inductor manufacturers. Since the LM2596 converter is a switch-mode power supply, its efficiency is significantly higher in comparison with popular three-terminal limear reguators, especially with higher input voltages. In many cases, the power dissipated is so low that no heatsink is required or its size could be reduced dramatically. A standard series of inductors optimized for use with the LM2596 are available from several different manufacturers. This feature greatly simplifies the design of switch-mode power supplies. The LM2596 features include a guaranteed +/- 4% tolerance on output voltage within specified input voltages and output load conditions, and +/-15% on the oscillator frequency (+/- 2% over 0oC to 125 oC). External shutdown is included, featuring 80 uA(typical) standby current. The output switch includes cycle-bycycle current limiting, as well as thermal shutdown for full protection under fault conditions.HTC1Oct 2004 - Rev 0元器件交易网/doc/a66360844.html,3.0A, 15V, Step-Down Switching RegulatorTypical Application (Fixed Output Voltage Versions)LM2596LM2596-5.033 uH680 uF1N5824220 uFFigure 1. Block Diagram and Typical ApplicationABSOLUTE MAXIMUM RATINGS(Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.)Power DissipationTO-220, 5-LeadThermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-caseTO-263Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-caseHTC2Oct 2004 - Rev 0元器件交易网/doc/a66360844.html,3.0A, 15V, Step-Down Switching RegulatorLM2596OPERATING RATINGS (Operating Ratings indicate conditions for which the device is intended to befunctional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.)ELECTRICAL CHARACTERISTICS / SYSTEM PARAMETERS ([Note 1] Test Circuit Figure 2) (Unless otherwise specified, Vin = 12 V for the 3.3 V, 5.0 V, and Adjustable version, Vin = 25 V for the 12 V version, and Vin = 30 V for the 15 V version. ILoad = 500mA. For typical values TJ = 25°C, for min/max values TJ is the operating junction temperature range that applies [Note 2], unless otherwise noted.)LM2596-3.3 ([ Note 1]. Test Circuit Figure 2 )73 LM2596-5.0 ([ Note 1]. Test Circuit Figure 2 ) 180 LM2596-12 ([ Note 1]. Test Circuit Figure 2 )90 LM2596-15 ([ Note 1]. Test Circuit Figure 2 )98 LM2596-ADJ ([ Note 1]. Test Circuit Figure 2 )73HTC3Oct 2004 - Rev 0元器件交易网/doc/a66360844.html,3.0A, 15V, Step-Down Switching RegulatorELECTRICAL CHARACTERISTICS / Device ParametersLM2596(Unless otherwise specified, Vin = 12 V for the 3.3 V, 5.0 V, and Adjustable version, Vin = 25 V for the 12 V version, and Vin = 30 V for the 15 V version. ILoad = 500 mA. For typical values Tj = 25°C, for min/max values Tj is the operating junction temperature range that applies [Note 2], unless otherwise noted.)10 0 127 110 15050 100 173 1731.16 01.4 1.53.6 3.4100 4.5 6.9 7.5 50 30 102 5 00 2 0 2.0 2.0 2 V LOGIC = 2.5V (Regulator OFF) V LOGIC = 0.5V (Regulator ON) 5 0.02 1.3 1.32500.6 0.6 15 5.01. External components such as the catch diode, inductor, input and output capacitors can affect switching regulator system performance. When the LM2596 is used as shown in the Figure 1 test circuit, system performance will be as shown in system parameters section .2. Tested junction temperature range for the LM2596 : TLOW = –0°C THIGH = +125°C3. The oscillator frequency reduces to approximately 18 kHz in the event of an output short or an overload which causes the regulated output voltage to drop approximately 40% from the nominal output voltage. This self protection feature lowers the average dissipation of the IC by lowering the minimum duty cycle from 5% down to approximately 2%.4. Output (Pin 2) sourcing current. No diode, inductor or capacitor connected to output pin.5. Feedback (Pin 4) removed from output and connected to 0 V.6. Feedback (Pin 4) removed from output and connected to +12 V for the Adjustable, 3.3 V, and 5.0V ersions, and +25 V for the 12 V and15 V versions, to force the output transistor “off”.7. Vin = 40 V.HTC4Oct 2004 - Rev 0元器件交易网/doc/a66360844.html,3.0A, 15V, Step-Down Switching RegulatorTYPICAL PERFORMANCE CHARACTERISTICS (Circuit ofFigure 2)LM2596HTC5Oct 2004 - Rev 0元器件交易网/doc/a66360844.html,3.0A, 15V, Step-Down Switching RegulatorTYPICAL PERFORMANCE CHARACTERISTICS (Circuit of Figure 2)Feedback Pin Bias CurrentLM2596HTC6Oct 2004 - Rev 0元器件交易网/doc/a66360844.html,3.0A, 15V, Step-Down Switching RegulatorTest Circuit and Layout GuidelinesLM2596Figure 2. Typical Test Circuits and Layout GuideAs in any switching regulator, layout is very important. Rapidly switching currents associated with wiring inductance can generate voltage transients which can cause problems. For minimal inductance and ground loops, the wires indicated by heavy lines should be wide printed circuit traces and should be kept as short as possible. For best results, external components should be located as close to the switcher lC as possible using ground plane construction or single point grounding. If open core inductors are used, special care must be taken as to thelocation and positioning of this type of inductor. Allowing the inductor flux to intersect sensitive feedback, lC groundpath and COUT wiring can cause problems. When using the adjustable version, special care must be taken as to the location of the feedback resistors and the associated wiring. Physically locate both resistors near the IC, and route the wiring away from the inductor, especially an open core type of inductor.HTC7Oct 2004 - Rev 0元器件交易网/doc/a66360844.html,3.0A, 15V, Step-Down Switching RegulatorLM2596PIN FUNCTION DESCRIPTION Symbol 1VinDescription This pin is the positive input supply for the LM2596 step–down switching23 45regulator.In order to minimize voltage transients and to supply the switching currents needed by the regulator, a suitable input bypass capacitor must be present .(Cin in Figure 1). Output This is the emitter of the internal switch. The saturation voltage Vsat of this output switch is typically 1.5 V. It should be kept in mind that the PCB area connected to this pin should be kept to a minimum in order to minimize coupling to sensitive circuitry. Circuit ground pin. See the information about the printed circuit board layout. Gnd Feedback This pin senses regulated outputvoltage to complete the feedback loop. The signal is divided by the internal resistor divider network R2, R1 and applied to the non–inverting input of the internal error amplifier. In the Adjustable version of the LM2596 switching regulator this pin is the direct input of the error amplifier and the resistor network R2, R1 is connected externally to allow programming of the output voltage. ON/OFF It allows the switching regulator circuit to be shut down using logic level signals, thus dropping the total input supply current to approximately 80 mA. The threshold voltage is typically 1.4 V. Applying a voltage above this value (up to +Vin) shuts the regulator off. If the voltage applied to this pin is lower than 1.4V or if this pin is left open, the regulator will be in the "on" conditionHTC8Oct 2004 - Rev 0元器件交易网/doc/a66360844.html,3.0A, 15V, Step-Down Switching RegulatorLM2596PACKAGES DIMENSION : TO220-5LHTC9Oct 2004 - Rev 0元器件交易网/doc/a66360844.html,3.0A, 15V, Step-Down Switching RegulatorPACKAGES DIMENSION : TO220V-5LLM2596HTC10Oct 2004 - Rev 0元器件交易网/doc/a66360844.html, 3.0A, 15V, Step-Down Switching RegulatorLM2596PACKAGES DIMENSION : TO263-5LHTC11Oct 2004 - Rev 0。

西门子S7-200系列CPU224XP компакт单元数据表说明书

西门子S7-200系列CPU224XP компакт单元数据表说明书

0.75 A 5W
L+ (-0.4 V (5 V / 20.4 V for A 0.0 to A 0.4; 20.4 V A 0.5 to A1.1))
01.08.2015
Changes preserved © Copyright Siemens AG
● for signal "1" rated value ● for signal "0" residual current, max. Output delay with resistive load ● "0" to "1", max.
Yes; I 0.0 to I 0.3
Yes; (E 0.0 to E 1.5) up to 200 kHz
500 m; Standard input: 500 m, high-speed counters: 50 m 300 m; not for high-speed signals
10; Transistor No; to be provided externally 1W
1 ms 54 min; 4 timers: 1 ms to 30 s; 16 timers: 10 ms to 5 min; 236 timers: 100 ms to 54 min
32 byte Yes; M 0.0 to M 31.7 0 to 255, via high-performance capacitor or battery, adjustable
100 h; (min. 70 h at 40 °C); 200 days (typ.) with optional battery module
0.22 µs
南天自助终端产品手册

南天自助终端产品手册

南天自助终端产品手册2014年南天自助产品中心产品部2014年4月目录1传统自助终端 (3)1.1大堂式多功能自助终端 (3)1.1.1Nantian BST-4200/C20 (3)1.1.2Nantian BST-5200 A20 (11)1.2穿墙式多功能自助终端 (20)1.2.1Nantian BST-4230/C21 (20)1.3壁挂式多功能自助终端 (27)1.3.1Nantian BST-3340/C22 (27)2自助发卡机 (33)2.1大堂式发卡机 (33)2.1.1Nantian BST-5200 B20 (33)2.2台式发卡机 (42)2.2.1Nantian BST-3340 H10 (42)3自助回单机 (48)3.1大堂式自助回单机 (48)3.1.1Nantian BST-5810A (48)4排队机 (55)4.1大堂式排队机 (55)4.1.1Nantian BST-5200/E10 (55)5其他 (59)5.1网银终端 (59)5.1.1Nantian BST-4200/G20 (59)5.2预填单机 (62)5.2.1Nantian BST-5200/B10 (62)5.3智能服务终端 (69)5.3.1Nantian BST-4210 A24 (69)5.4存折补登机 (75)5.4.1Nantian BST-1100 (75)1传统自助终端1.1大堂式多功能自助终端1.1.1N antian BST-4200/C201.1.1.1效果图1.1.1.2结构尺寸图1.1.1.3功能特点外形新颖：整机采用流线型设计；全注塑面板，美观大方；整机色调协调统一；全功能配置：支持存折补登、银行卡查询及转账等多种传统业务功能的同时，能够播放多媒体广告信息，并支持凭条/账单/发票等多种票据的自助打印功能；可扩展型强：支持激光打印机、发票打印机、条码扫描、非接触式IC卡等多种模块扩展功能；强大的卡业务处理功能：支持磁卡、IC、非接触式IC卡等多种卡片的读写功能；数据安全性高：采用硬件加密键盘；配备读卡器异型卡口及密码键盘防窥式设计，大大提高了用户个人信息的安全性；1.1.1.4标准配置1.1.1.5可扩展配置1.1.2N antian BST-5200 A201.1.2.1效果图1.1.2.2结构尺寸图1.1.2.3功能特点外形新颖：整机采用流线型设计；全注塑面板，美观大方；整机色调协调统一；全功能配置：支持存折补登、银行卡查询及转账等多种传统业务功能的同时，能够播放多媒体广告信息，并支持凭条/账单/发票等多种票据的自助打印功能；可扩展型强：支持激光打印机、发票打印机、条码扫描、非接触式IC卡等多种模块扩展功能；强大的卡业务处理功能：支持磁卡、IC、非接触式IC卡等多种卡片的读写功能；数据安全性高：采用硬件加密键盘；配备读卡器异型卡口及密码键盘防窥式设计，大大提高了用户个人信息的安全性；1.1.2.4标准配置1.1.2.5可扩展配置1.2穿墙式多功能自助终端1.2.1N antian BST-4230/C211.2.1.1效果图1.2.1.2安装尺寸图1.2.1.3功能特点户外穿墙式应用设计：高附着力，防酸碱腐蚀户外型塑粉喷塑；防水、防尘、防暴；超强的高低温适应能力；功能布局合理：引用ATM 导轨式拉出设计，前面框及各模块可拉出进行维护，方便、快捷；全功能配置：支持存折补登、银行卡查询及转账等多种传统业务功能的同时，能够播放多媒体广告信息，并支持凭条/账单/发票等多种票据的自助打印功能；可扩展型强：支持激光打印机、发票打印机、条码扫描、非接触式IC卡等多种模块扩展功能；数据安全性高：采用硬件加密键盘；配备读卡器异型卡口及密码键盘防窥罩，大大提高了用户个人信息的安全性；智能电源管理：掉电监控、掉电保护、自动维护、自动关机；1.2.1.4标准配置1.2.1.5可扩展配置1.3壁挂式多功能自助终端1.3.1N antian BST-3340/C221.3.1.1效果图1.3.1.2安装尺寸图1.3.1.3功能特点壁挂式设计：不受安装空间限制，可做离行式设备使用；强大的卡业务处理功能：支持磁卡、IC、非接触式IC卡等多种卡片的读写功能；多种扩展功能：条码扫描、非接触式IC卡、发票打印机、GPRS或CDMA无线通信模块；机身色彩个性化定制：机身颜色可根据用户需求进行个性化定制；数据安全：EPP硬件加密键盘，采用凹陷型设计，设计时充分考虑了用户信息安全性；1.3.1.4标准配置1.3.1.5可扩展配置2自助发卡机2.1大堂式发卡机2.1.1N antian BST-5200 B202.1.1.1效果图2.1.1.2安装尺寸图2.1.1.3功能特点先进的自助发卡模块，保障自助发卡的可靠性和安全性。

PA2561L1-1(NEC)光耦规格书

PA2561L1-1(NEC)光耦规格书

DATA SHEETThe information in this document is subject to change without notice.©1992Document No. P12989EJ4V0DS00 (4th edition)(Previous No. LC-2225)Date Published August 1997 NS Printed in JapanPHOTOCOUPLERPS2561-1,-2, PS2561L-1,-2HIGH ISOLATION VOLTAGE SINGLE TRANSISTOR TYPE MULTI PHOTOCOUPLER SERIESThe mark shows major revised points.DESCRIPTIONThe PS2561-1, -2 and PS2561L-1, -2 are optically coupled isolators containing a GaAs light emitting diode and an NPN silicon phototransistor.PS2561-1, -2 are in a plastic DIP (Dual In-line Package) and PS2561L-1, -2 are lead bending type (Gull-wing) for surface mount.FEATURES•High isolation voltageBV = 5 000 Vr.m.s.: standard productsBV = 3 750 Vr.m.s.: VDE0884 approved products (Option)•High collector to emitter voltage (V CEO = 80 V)•High current transfer ratio (CTR = 200 % TYP.)•High-speed switching (t r = 3 µs TYP., t f = 5 µs TYP.)•UL approved (File No. E72422 (S) )•CSA approved (No. CA 101391)•BSI approved (BS415, BS7002) No. 7112•SEMKO approved (SS4410165) No. 9317144•NEMKO approved (NEK-HD 195S6) No. A21409•DEMKO approved (Section 101, 137) No. 300535•FIMKO approved (E69-89) No. 167265-08•VDE0884 approved (Option)APPLICATIONS•Power supply •Telephone/FAX.•FA/OA equipment•Programmable logic controller2PACKAGE DIMENSIONS (in millimeters)DIP Type5.1 MAX.6.53.8M A X .4.55M A X .2.8M I N .0.652.547.620.50 ± 0.100.25M4312PS2561-1 (New Package)10.2 MAX.1.25±0.156.53.8M A X .4.55M A X .2.8M I N .0.652.547.620.50 ± 0.100.25M871265340 to 15˚PS2561-20 to 15˚PS2561-14.6 ± 0.351.25±0.156.53.8M A X .4.55M A X .2.8M I N .0.650.50 ± 0.100.25M0 to 15˚7.622.5443121.25±0.15PS2561L1-15.1 MAX.6.53.8M A X .4.25M A X .2.8M I N .0.352.547.620.50 ± 0.100.25M0 to 15˚43121.25±0.1510.161. Anode 2. Cathode 3. Emitter 4. Collector 1, 3. Anode 2, 4. Cathode 5, 7. Emitter 6, 8. Collector1. Anode2. Cathode3. Emitter4. Collector 1. Anode 2. Cathode 3. Emitter 4. Collector Caution New package 1ch only3Lead Bending Type5.1 MAX.6.53.8M A X .2.547.620.25M4312PS2561L-1 (New Package)10.2 MAX.1.25±0.156.53.8M A X .2.547.6287126534PS2561L-2PS2561L-14.6 ± 0.351.25±0.156.53.8M A X .0.25M7.622.5443121.25±0.150.05 t o 0.29.60 ± 0.40.90 ± 0.250.05 t o 0.29.60 ± 0.40.90 ± 0.250.25M0.05 t o 0.29.60 ± 0.40.90 ± 0.255.1 MAX.6.53.8M A X .2.547.620.25MPS2561L2-143121.25±0.150.05 t o 0.210.160.9 ± 0.2512.0 MAX.1. Anode2. Cathode3. Emitter4. Collector1, 3. Anode 2, 4. Cathode 5, 7. Emitter 6, 8. Collector 1. Anode 2. Cathode 3. Emitter 4. Collector 1. Anode 2. Cathode 3. Emitter 4. Collector Caution New package 1ch only4ORDERING INFORMATIONPart NumberPackageSafety Standard ApprovalApplication partnumber *1PS2561-1PS2561L-1PS2561L1-1PS2561L2-14-pin DIP4-pin DIP (lead bending surface mount)4-pin DIP (for long distance)4-pin DIP (for long distance surfacemount)Standard products PS2561-1PS2561-2PS2561L-28-pin DIP8-pin DIP (lead bending surface mount)PS2561-2PS2561-1-V PS2561L-1-V PS2561L1-1-V PS2561L2-1-V 4-pin DIP4-pin DIP (lead bending surface mount)4-pin DIP (for long distance)4-pin DIP (for long distance surfacemount)VDE0884 approved products (Option)PS2561-1PS2561-2-V PS2561L-2-V8-pin DIP8-pin DIP (lead bending surface mount)PS2561-2*1 As applying to Safety Standard, following part number should be used.ABSOLUTE MAXIMUM RATINGS (T A = 25 °C, unless otherwise specified)ParameterSymbolRatingsUnitPS2561-1,PS2561L-1PS2561-2,PS2561L-2DiodeReverse Voltage V R 6V Forward Current (DC)I F80mAPower Dissipation Derating ∆P D /°C 1.5 1.2mW/°C Power Dissipation P D 150120mW/ch Peak Forward Current*1I FP 1A TransistorCollector to Emitter Voltage V CEO 80V Emitter to Collector Voltage V ECO 7V Collector CurrentI C50mA/chPower Dissipation Derating ∆P C /°C 1.5 1.2mW/°C Power DissipationP C 150120mW/ch Isolation Voltage*2BV5 0003 750*3Vr.m.s.Operating Ambient Temperature T A –55 to +100°C Storage TemperatureT stg–55 to +150°C*1PW = 100 µs, Duty Cycle = 1 %*2AC voltage for 1 minute at T A = 25 °C, RH = 60 % between input and output *3VDE0884 approved products (Option)•UL approved •CSA approved •BSI approved•NEMKO approved •DEMKO approved •SEMKO approved•FIMKO approved5ELECTRICAL CHARACTERISTICS (T A = 25 °C)ParameterSymbol Conditions MIN.TYP.MAX.Unit DiodeForward Voltage V F I F = 10 mA 1.171.4VReverse Current I R V R = 5 V5µA Terminal CapacitanceC t V = 0 V, f = 1.0 MHz 50pFTransistorCollector to Emitter Dark CurrentI CEOV CE = 80 V, I F = 0 mA100nACoupled Current Transfer Ratio *1CTR I F = 5 mA, V CE = 5 V 80200400%Collector Saturation VoltageV CE (sat)I F = 10 mA, I C = 2 mA0.3V Isolation Resistance R I-O V I-O = 1.0 kV 1011ΩIsolation Capacitance C I-O V = 0 V, f = 1.0 MHz0.5pFRise Time *2t r V CC = 10 V, I C = 2 mA, R L = 100 Ω3µsFall Time*2t f5*1CTR rank (only PS2561-1, PS2561L-1)*2Test circuit for switching timeL: 200 to 400 (%)M : 80 to 240 (%)D : 100 to 300 (%)H : 80 to 160 (%)W : 130 to 260 (%)V CCV OUTR L = 100 Ω50 ΩI F µPulse InputPW = 100 sDuty Cycle = 1/106TYPICAL CHARACTERISTICS (T A = 25 °C, unless otherwise specified)150100500255075100125150 1.5 mW/˚C1.2 mW/˚C15010050255075100125150010 0001001 000100101755025–25–50V CE = 80 V10 1.00.80.60.40.20510.50.110 m A401.5 mW/˚C1.2 mW/˚C20 m A 50 m A 2 m AI F = 1 mA5 m A 70260504030201004681020 m A I F = 5 mA10m A 50 m A 40 V 24 V 10 V 5 VPS2561-1PS2561L-1PS2561-2PS2561L-2PS2561-1PS2561L-1PS2561-2PS2561L-2100 1.51.41.31.21.11.00.90.80.75010510.50.10 ˚C –25 ˚C –55 ˚C+60 ˚C +25 ˚CT A = +100 ˚CD i o d e P o w e r D i s s i p a t i o n P D (m W )T r a n s i s t o r P o w e r D i s s i p a t i o n P C (m W )Ambient Temperature T A (˚C)F o r w a r d C u r r e n t I F (m A )Forward Voltage V F (V)C o l l e c t o r C u r r e n t I C (m A )Collector to Emitter Voltage V CE (V)C o l l e c t o r t o E m i t t e rD a r k C u r r e n t I CE O (n A )Collector Saturation Voltage V CE(sat) (V)Ambient Temperature T A (˚C)Ambient Temperature T A (˚C)DIODE POWER DISSIPATION vs.AMBIENT TEMPERATURETRANSISTOR POWER DISSIPATION vs. AMBIENT TEMPERATUREFORWARD CURRENT vs.FORWARD VOLTAGECOLLECTOR CURRENT vs.COLLECTOR TO EMITTER VOLTAGECOLLECTOR TO EMITTER DARKCURRENT vs. AMBIENT TEMPERATURECOLLECTOR CURRENT vs.COLLECTOR SATURATION VOLTAGEC o l l e c t o r C u r r e n t I C (m A )7PS2561-1,-2,PS2561L-1,-21.2–501.00.80.60.40.20–252550751004504003503002502001501005000.050.10.5151050501010.110 k5 k 1 k50010050101 000100101100 k50 k 10 k5 k 1 k5001000–5–10–15–200.5125102050100200500I C = 2 mA,V CC = 10 V,CTR = 290 %t f t rt dt sI F = 5 mA,V CC = 5 V,CTR = 290 %t st dt rt fI F = 5 mA,V CE = 5 V100 Ω300 ΩR L = 1 k ΩI F = 5 mA T A = 25 ˚CI F = 5 mA T A = 60 ˚C 1.21.00.80.60.40.2102103104105Normalized to 1.0at T A = 25 ˚C,I F = 5 mA, V CE = 5 VForward Current I F (mA)Ambient Temperature T A (˚C)Load Resistance R L (Ω)Frequency f (kHz)N o r m a l i z e d C u r r e n t T r a n s f e r R a t i o C T RC u r r e n t T r a n s f e r R a t i o C T R (%)N o r m a l i z e d G a i n G VLoad Resistance R L (Ω)S w i t c h i n g T i m e t ( s )µNORMALIZED CURRENT TRANSFER RATIO vs. AMBIENT TEMPERATURECURRENT TRANSFER RATIO vs.FORWARD CURRENTSWITCHING TIME vs.LOAD RESISTANCESWITCHING TIME vs.LOAD RESISTANCEFREQUENCY RESPONSELONG TIME CTR DEGRADATIONS w i t c h i n g T i m e t ( s )µTYP.Time (Hr)C T R (R e l a t i v e V a l u e )8TAPING SPECIFICATIONS (in millimeters)Taping DirectionPS2561L-1-E3PS2561L-1-F3PS2561L-1-E4PS2561L-1-F4Outline and Dimensions (Tape)1.55±0.12.0±0.14.0±0.11.55±0.11.75±0.14.3±0.210.3±0.10.37.5±0.116.0±0.35.6±0.18.0±0.1Outline and Dimensions (Reel)Packing: PS2561L-1-E3, E4 1 000 pcs/reel2.0±0.5R 1.013.0±0.5φ21.0±0.8φ16.4+2.0–0.0P S 2561L -1-E 3, E 4: 250P S 2561L -1-F 3, F 4: 330φ80.0±5.0φφPS2561L-1-F3, F4 2 000 pcs/reel9Taping DirectionPS2561L-2-E3PS2561L-2-E4Outline and Dimensions (Tape)1.55±0.12.0±0.14.0±0.11.55±0.11.75±0.14.3±0.210.3±0.10.37.5±0.116.0±0.310.4±0.112.0±0.1Outline and Dimensions (Reel)Packing: 1 000 pcs/reel16.4+2.0–0.080.0±5.0φ330φ2.0±0.5R 1.013.0±0.5φ21.0±0.8φ10RECOMMENDED SOLDERING CONDITIONS(1) Infrared reflow soldering • Peak reflow temperature235 °C (package surface temperature)• Time of temperature higher than 210 °C 30 seconds or less • Number of reflows Three• FluxRosin flux containing small amount of chlorine (The flux with a maximum chlorine content of 0.2 Wt % is recommended.)60 to 90 s (preheating)210 ˚C120 to 160 ˚CP a c k a g e S u r f a c e T e m p e r a t u r e T (˚C )Time (s)(heating)to 10 sto 30 s235 ˚C (peak temperature)Recommended Temperature Profile of Infrared ReflowPeak temperature 235 ˚C or belowCaution Please avoid to removed the residual flux by water after the first reflow processes.(2) Dip soldering • Temperature 260 °C or below (molten solder temperature)• Time10 seconds or less • Number of times One• FluxRosin flux containing small amount of chlorine (The flux with a maximum chlorine content of 0.2 Wt % is recommended.)11SPECIFICATION OF VDE MARKS LICENSE DOCUMENT (VDE0884)ParameterSymbolSpeckUnitApplication classification (DIN VDE 0109)for rated line voltages ≤ 300 Vr.m.s.for rated line voltages ≤ 600 Vr.m.s.IV III Climatic test class (DIN IEC 68 Teil 1/09.80)55/100/21Dielectric strength maximum operating isolation voltageTest voltage (partial discharge test procedure a for type test and random test)U pr = 1.2 × U IORM , P d < 5 pCU IORM U pr 8901 068V peak V peakTest voltage (partial discharge test procedure b for random test)U pr = 1.6 × U IORM , P d < 5 pC U pr 1 424V peakHighest permissible overvoltage U TR 6 000V peakDegree of pollution (DIN VDE 0109)2Clearance distance > 7.0mm Creepage distance> 7.0mmComparative tracking index (DIN IEC 112/VDE 0303 part 1)CTI 175Material group (DIN VDE 0109)III a Storage temperature range T stg –55 to +150°C Operating temperature rangeT A –55 to +100°C Isolation resistance, minimum value V IO = 500 V dc at T A = 25 °CV IO = 500 V dc at T A MAX. at least 100 °CRis MIN.Ris MIN.10121011ΩΩSafety maximum ratings (maximum permissible in case of fault, see thermal derating curve)Package temperatureCurrent (input current I F , Psi = 0)Power (output or total power dissipation)Isolation resistanceV IO = 500 V dc at T A = 175 °C (Tsi)Tsi Isi Psi Ris MIN.175********9°C mA mW ΩCAUTIONWithin this device there exists GaAs (Gallium Arsenide) material which is aharmful substance if ingested. Please do not under any circumstances break thehermetic seal.No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document.NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others.While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features.NEC devices are classified into the following three quality grades:"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application.Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronicequipment and industrial robotsSpecial: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designedfor life support)Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc.The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.Anti-radioactive design is not implemented in this product.M4 96. 5。