Efficient multi-level modeling technique for determining effective board drop reliability of PCB

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In this paper, we develop a new and computationally efficient multi-level approach to investigate board level drop reliability of printed circuit board (PCB) assembly. The approach is composed of two levels of finite element (FE) simulations: solder joint level and board level. Initially, static simulations of the solder joint level were used to obtain the homogenized property of the solder-underfill interconnection. This was followed by explicit FE simulations of the board assembly. The results of the proposed multi-level approach were compared with commonly adopted FE analysis and good correspondence is revealed between the two. Through drop test simulations that involved fifteen Integrated Circuit (IC) packages, as per the standard JESD22-B111 of Joint Electron Device Engineering Council (JEDEC), the critical board locations and interconnection in each location were identified and analyzed. The results reveal that peak stresses occur at the corner of the central package. They also show that the interconnection stresses result mainly from the dynamic bending of the PCB.
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1. Introduction
Motivated by the demand for increased portability and functionality, miniaturization has become the tendency in the portable electronic industry [1]. For example, highly integrated packages, such as fine-pitched flip chip ball grid array (FCBGA), is interconnected to PCB using surface mount technology (SMT) instead of through-hole technology (THT). Because of its reduced compliance, SMT interconnection is more vulnerable to impact loads and thermal shock compared to THT [1,2]. The interconnection integrity becomes a main reliability concern.
Computer simulations are widely used to study the drop reliability of PCB assembly. Some authors [8–10,19] modeled the entire test apparatus and simulated the complete impact process. Others [10,20,21,30] followed the so-called input-G method where only the PCB assembly was modeled and a predefined shock pulse is directly imposed to the PCB at the supporting positions to significantly save the computations cost. Yeh and Lai [31] developed the support excitation scheme by converting the acceleration loads to inertial body forces with the aid of an implicit solver. Luan and Tee [20] concluded that the implicit and explicit input-G methods were comparable in terms of solution time and accuracy. Qiang et al. [32] indicated that the flexural response of the PCB was dominated by its fundamental modes. Several parametric studies were also carried out. For example, Lai et al. [22] investigated packageon-package stacking assemblies of different configurations. Groothuisa et al. [19] examined the effect of the acceleration magnitude, solder ball diameter and underfill material upon the reliability of the PCB assembly. Lai et al. [15] concluded that decreasing the die thickness, the die size, or using larger solder joints and joint pitch would benefit the drop reliability.
et al. in [25]. Modal tests were also used to obtain material properties and assist in the design of PCB for drop reliability [14,26]. Besides the drop tests, other techniques were also developed such as high speed bending tests [27,28] which were designed to investigate fatigue failure of interconnections. Component level tests such as ball impact shear and solder ball pull [4,12,29] were also used to investigate the strength and failure mechanisms of solder joints. Yeh and Lai correlated the package-level ball impact test characteristics to the board-level drop reliability in [17].
Efficient multi-level modeling technique for determining effective board drop reliability of PCB assembly
Fan Yang, Shaker A. Meguid ⇑
Mechanics and Aerospace Design Laboratory, Universilege Road, Toronto Ontario, Canada M5S 3G8
article info
Article history: Received 22 January 2013 Received in revised form 13 March 2013 Accepted 29 March 2013 Available online 24 April 2013
abstract
A number of attempts have been made to investigate the interconnection reliability in the literature. Typically, these reliability assessments are determined using board-level drop tests of the PCB–IC assembly [3,4]. The tests can be categorized into two types: the free drop test [5–8] and the pulse-controlled drop test [3,4,9– 11]. The latter category provides a controlled shock pulse profile and has advantages over the preceding one for data consistency and reproducibility [12]. It is for this reason that the pulsecontrolled drop test is commonly adopted by industry subject to JESD22-B111 standard of JEDEC [3,9–11,13–22]. Dynamic electrical resistance was used to monitor the crack initiation, propagation and damage evolution of the daisy-chained solder joints [9,11,23]. Strain measurement carried out in [24] indicated that PCB bending instead of inertial force was the main driver for the failure of solder joints, which was analytically confirmed by Wong