CY24212SC-1中文资料

MediaClock™MPEG Clock Generator with VCXOCY24212PRELIMINARYFeaturesBenefits•Integrated phase-locked loop (PLL)Highest-performance PLL tailored for multimedia applications •Low jitter, high-accuracy outputs Meets critical timing requirements in complex system designs •VCXO with analog adjust Large ±150-ppm range, better linearity •3.3V operation Enables application compatibilityPart Number OutputsInput Frequency Range Output FrequenciesCY24212-1113.5 MHz/27 MHz (selectable)27 MHzCY24212-2213.5 MHz/27 MHz (selectable)Two copies of 27 MHz CY24212-3227 MHz 27 MHz/27.027 MHz (-1 ppm)CY24212-5227 MHz27 MHz/27.027 MHz (0 ppm)Table 1.CY24212 (-1, -2) Frequency Select OptionFSEL Reference CLKA/CLKB 013.5 MHz 27 MHz 127 MHz27 MHzTable 2.CY24212 (-3, -5) Frequency Select OptionFSEL Reference CLKA CLKB 027 MHz 27 MHz 27 MHz 127 MHz27 MHz27.027 MHz8-pin SOICCY24212-1Pin Configurations1234XOUT XIN VCXO CLKA 27 MHzVSSVSSFSEL5678VDD 8-pin SOICCY24212-21234XOUT XIN VCXO CLKA 27 MHzVSSCLKB 27 MHz FSEL5678VDD 8-pin SOICCY24212-3,-51234XOUTXIN VCXO CLKA 27 MHzVSSCLKB (27/27.027 MHz)FSEL5678VDDPin DescriptionName Pin Number DescriptionXIN1Reference Input.VDD2Voltage Supply.VCXO3Input Analog Control for VCXO.VSS4Ground.CLKA527-MHz Clock Output.FSEL (-1,-2)6Input Frequency Select, Weak Internal Pull-up.FSEL = 0, XIN = 13.5 MHzFSEL = 1, XIN = 27 MHzFSEL (-3,-5)6Output Frequency Select, Weak Internal Pull-up.FSEL = 0, CLKA = 27 MHz, CLKB = 27 MHzFSEL = 1, CLKA = 27 MHz, CLKB = 27.027 MHzVSS (-1)7Ground.CLKB (-2)727 MHz.CLKB (-3,-5)727 MHz/27.027 MHz.XOUT[1]8Reference Output.Pullable Crystal SpecificationsParameter Name Min Typ Max Unit CR load Crystal Load Capacitance14pF C0/C1240ESR Equivalent Series Resistance3550ΩT o Operating Temperature070°C Crystal Accuracy Crystal Accuracy+ 20ppm TT s Stability over Temperature and Aging+ 50ppmAbsolute Maximum ConditionsParameter Description Min Max Unit V DD Supply Voltage–0.57.0V T S Storage Temperature[2]–65125°C T J Junction Temperature125°C Digital Inputs V SS– 0.3V DD + 0.3VElectrostatic Discharge2kVRecommended Operating ConditionsParameter Description Min Typ Max Unit V DD Operating Voltage 3.135 3.3 3.465VT A Ambient Temperature070°CC LOAD Max. Load Capacitance 15pFf REF Reference Frequency13.527MHz Notes:1.Float XOUT if XIN is externally driven.2.Rated for ten years.DC Electrical SpecificationsParameter Name Description Min Typ Max Unit I OH Output High Current V OH = V DD– 0.5, V DD = 3.3V (source)1224mA I OL Output Low Current V OL = 0.5, V DD = 3.3V (sink)1224mA C IN Input Capacitance7pF I IH Input High Current V IH = V DD–510µA I IL Input Low Current V IL = 0V––50µA f∆XO VCXO Pullability Range+150ppm V VCXO VCXO Input Range0V DD V I DD Supply Current Sum of Core and Output Current35mA V IH Input High Voltage CMOS levels, 70% of V DD0.7V DD V IL Input Low Voltage CMOS levels, 30% of V DD0.3V DD R UP Pull-up resistor on inputs V DD = 3.14 to 3.47V, measured V IN = 0V100150kΩAC Electrical Specifications (V DD = 3.3V)Parameter[3]Name Description Min Typ Max Unit DC Output Duty Cycle Duty Cycle is defined in Figure 1, 50% of V DD455055% ER Rising Edge Rate Output Clock Edge Rate, Measured from 20%to 80% of V DD, C LOAD = 15 pF. See Figure 2.0.8 1.4V/nsEF Falling Edge Rate Output Clock Edge Rate, Measured from 80%to 20% of V DD, C LOAD = 15 pF. See Figure 2.0.8 1.4V/ns t9Clock Jitter Peak-to-peak period jitter300ps t10PLL Lock Time3ms Test and Measurement Set-upNote:3.Not 100% tested.0.1µFV DDsOutputsC LOADGNDDUTOrdering InformationOrdering Code Package Name Package Type Operating Range Operating Voltage CY24212SC-1S88-Pin SOICCommercial 3.3V CY24212SC-1T S88-Pin SOIC -Tape and ReelCommercial 3.3V CY24212SC-2S88-Pin SOICCommercial 3.3V CY24212SC-2T S88-Pin SOIC -Tape and Reel Commercial 3.3V CY24212SC-3S88-Pin SOICCommercial 3.3V CY24212SC-3T S88-Pin SOIC -Tape and Reel Commercial 3.3V CY24212SC-5S88-Pin SOICCommercial 3.3V CY24212SC-5TS88-Pin SOIC -Tape and ReelCommercial3.3VFigure 1.Duty Cycle DefinitionFigure 2.ER = (0.6 x V DD ) /t3, EF = (0.6 x V DD ) /t4Package Drawing and Dimensions8-Lead(150-Mil)SOIC S851-85066-*AMediaClock is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders.Document History PageDocument Title: CY24212 MediaClock™ MPEG Clock Generator with VCXO Document Number: 38-07402REV.ECN NO.IssueDateOrig. ofChange Description of Change**11708909/09/02CKN New Data Sheet *A12088812/06/02CKN Added -3*B12306402/19/03CKN Added -5。